JP2014049945A - Data reception circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reception circuit and a semiconductor device that precisely acquire a data signal corresponding to information data from signals by high speed and high density transmission.SOLUTION: In sending an amplified amplitude signal that is an amplified amplitude of received signals onto a first line and converting the signal on the first line to a binary one to be output as a received data signal, a current is injected onto the first line or a current is drawn from the first line in response to the received data signal to control the waveform of the amplified amplitude signal.

Description

  The present invention relates to a data receiving circuit for performing various signal processing on a received signal received via a transmission line, and a semiconductor device in which the data receiving circuit is formed.

  In recent years, high-speed and high-density data transmission has been desired, and a differential transmission system has been proposed as a data transmission system that satisfies such requirements.

  In the differential transmission method, information data is converted into a pair of differential signals having different polarities, and these are transmitted via a balanced transmission line. As a data receiving circuit for receiving such a differential signal, a pair of received differential signals are captured by a differential input stage, and the level of the signal captured by the differential input stage can be used in a logic circuit by a level conversion stage. There has been proposed one that outputs a signal converted into a level as a data signal (see, for example, FIG. 1 of Patent Document 1). In this data receiving circuit, the received pair of differential signals (IN1, IN2) are taken in through the gate terminals of the transistors M81 and M82 of the differential input stage (M80 to M84), and the difference value between them is amplified. A signal is supplied to the level conversion stage (M85 to M88) via lines 3 and 4.

  However, due to the influence of the parasitic capacitance existing in the data receiving circuit, for example, the capacitance component parasitic on the lines 3 and 4, the signal in the receiver may be delayed or blunted. Therefore, it has been difficult to obtain a data signal with high accuracy from a received signal transmitted at high speed.

JP 2008-1224697 A

  The present invention solves the above problems, and a data receiving circuit capable of accurately obtaining a data signal corresponding to information data from a received signal transmitted at high speed and the data receiving circuit are formed. An object of the present invention is to provide a semiconductor device.

  The data receiving circuit according to the present invention binarizes the signal on the first line and sends out the amplified signal obtained by amplifying the amplitude of the received signal onto the first line, and outputs the signal as a received data signal. And a data receiving circuit including an output unit, wherein the waveform of the amplitude amplification signal is controlled by discharging current onto the first line or sucking current from the first line according to the received data signal. Includes a waveform controller.

  The semiconductor device according to the present invention includes a data receiving circuit and a driving circuit that generates a control signal for driving the display device in accordance with the output of the data receiving circuit.

  The data receiving circuit according to the present invention transmits an amplitude amplified signal obtained by amplifying the amplitude of the received signal onto the first line, binarizes the signal on the first line, and outputs it as a received data signal. In accordance with the received data signal, the waveform of the amplitude amplified signal is controlled by discharging current on the first line or sucking current from the first line. By suppressing the amplitude of the amplitude amplification signal by such waveform control or by making the level transition with time elapse at the edge portion of the amplitude amplification signal, an amplitude amplification signal with little delay or waveform dullness is generated.

  Therefore, according to the present invention, it is possible to acquire a binary data signal with high accuracy from a signal transmitted at high speed.

1 is a circuit diagram showing an example of a data receiving circuit 10 according to the present invention. 6 is a time chart for explaining the operation of the waveform control stage 4; FIG. 6 is a circuit diagram showing a modification of the data receiving circuit 10 shown in FIG. 1. 6 is a circuit diagram showing a modification of the waveform control stage 4. FIG. It is a circuit diagram which shows another example of the data receiving circuit 10 which concerns on this invention. 6 is a time chart for explaining the operation of the waveform control stage 4 shown in FIG. 5.

  FIG. 1 is a circuit diagram showing an example of the configuration of a data receiving circuit 10 according to the present invention.

  In FIG. 1, the data receiving circuit 10 is formed on a semiconductor substrate as a semiconductor device, and includes a differential amplification stage 1, a level conversion stage 2, an output stage 3, and a waveform control stage 4. The data receiving circuit 10 receives a pair of differential signals having different polarities from each other via the balanced transmission lines BL1 and BL2. The pair of differential signals is generated on the transmission side (not shown) based on information data to be transmitted. At this time, a pair of differential signals IN and INB as received signals received via the balanced transmission lines BL1 and BL2 are respectively converted into p-channel MOS (Metal Oxide Semiconductor) type transistors 11 and 12 of the differential amplification stage 1. Are respectively supplied to the gate terminals. The constant current source 13 generates a predetermined constant current Ia based on the power supply voltage VCC and supplies it to the source terminals of the transistors 11 and 12. The drain terminal of the transistor 11 is connected to the drain terminal and the gate terminal of the n-channel MOS transistor 14. The ground voltage VSS is applied to the source terminal of the transistor 14, and the gate terminal and drain terminal thereof are connected to the level conversion stage 2 via the relay line RL1. The drain terminal of the transistor 12 is connected to the drain terminal and the gate terminal of the n-channel MOS transistor 15. The ground voltage VSS is applied to the source terminal of the transistor 15, and the gate terminal and drain terminal thereof are connected to the level conversion stage 2 via the relay line RL2.

  With the above configuration, the differential amplifier stage 1 causes the differential signal ANB obtained by amplifying a signal corresponding to the level difference between the differential signal IN and the differential signal INB to be supplied to the level conversion stage 2 via the relay line RL1. At the same time, the differential signal AN obtained by amplifying the signal obtained by inverting the phase of the differential signal ANB is supplied to the level conversion stage 2 via the relay line RL2.

  A power supply voltage VCC is applied to the source terminals of the p-channel MOS transistors 21 and 22 in the level conversion stage 2, and the respective gate terminals are connected to each other. The gate terminal and the drain terminal of the transistor 21 are connected to the drain terminal of the n-channel MOS transistor 23 via a line LL1. The differential signal AN supplied from the differential amplifier stage 1 via the relay line RL2 is supplied to the gate terminal of the transistor 23, and the ground voltage VSS is applied to its source terminal. The drain terminal of the transistor 22 is connected to the drain terminal of the n-channel MOS transistor 24 via the line LL2. The differential signal ANB supplied from the differential amplifier stage 1 via the relay line RL1 is supplied to the gate terminal of the transistor 24, and the ground voltage VSS is applied to its source terminal.

  With the configuration described above, the level conversion stage 2 amplifies the amplitude of the signal corresponding to the difference between the differential signal AN and the differential signal ANB and converts the level of the signal within the range of the ground voltage VSS to the power supply voltage VCC. The signal is an amplitude amplified signal RN, which is supplied to the output stage 3 and the waveform control stage 4 via the line LL2.

The output stage 3 first binarizes the amplitude amplified signal RN supplied from the level conversion stage 2. That is, the output stage 3 corresponds to a logic level 1 indicating a high level when the signal level of the amplitude amplification signal RN is higher than the threshold value Vth of the transistor, and a logic level 0 indicating a low level when the signal level is equal to or lower than the threshold value Vth. Generate a value signal. Then, the output stage 3 outputs the binary signal delayed by a predetermined time t while supplying it to the waveform control stage 4 as the reception data signal RDS. The output stage 3 is composed of n parts (n is an even number) inverters 31 _{1 to} 31 _n connected in series, and the total element delay time of each of these inverters 31 _{1 to} 31 _n is the predetermined time. t.

The waveform control stage 4 includes p-channel MOS transistors 41 and 42 and n-channel MOS transistors 43 and 44. The drain terminal of the transistor 41 is connected to the line LL2, to its gate terminal, the bias voltage VB ₁ fixed for setting the drain current the transistor 41 is transmitted to the predetermined current is supplied. The source terminal of the transistor 41 is connected to the drain terminal of the transistor 42. The power supply voltage VCC is applied to the source terminal of the transistor 42, and the reception data signal RDS sent from the output stage 3 is supplied to the gate terminal. The drain terminal of the transistor 43 is connected to the line LL2, to its gate terminal, the bias voltage VB ₂ fixed for setting the drain current the transistor 43 is transmitted to the predetermined current is supplied. The source terminal of the transistor 43 is connected to the drain terminal of the transistor 44. The ground voltage VSS is applied to the source terminal of the transistor 44, and the reception data signal RDS sent from the output stage 3 is supplied to the gate terminal. That is, the waveform control stage 4 is obtained by adding output current adjusting transistors 41 and 43 to a complementary circuit composed of transistors 42 and 44 that operate complementarily in accordance with the received data signal RDS.

  With the configuration described above, the transistor 42 in the waveform control stage 4 is turned on when the received data signal RDS is at a logic level 0 indicating a low level equal to or lower than the threshold Vth, and is based on the power supply voltage VCC that is a high voltage. The current is discharged through the transistor 41 onto the line LL2. Accordingly, the line LL2 is charged by the current, and the voltage of the line LL2, that is, the signal level of the amplitude amplification signal RN is shifted to the higher level by that amount. On the other hand, when the received data signal RDS is at a logic level 1 indicating that the level is higher than the threshold value Vth, the transistor 44 in the waveform control stage 4 is turned on, and current is sucked from the line LL2 side through the transistor 43. . By drawing the current, the voltage of the line LL2, that is, the signal level of the amplitude amplified signal RN is shifted to the low level side.

  Here, the amplitude of the amplitude amplification signal RN becomes maximum when the change period is long as shown in the section T1 or T3 in FIG. 2, and becomes small as shown in the section T2 in FIG. 2 when the change period is short. .

  During this time, according to the operation of the waveform control stage 4 as described above, as shown in FIG. 2, the minimum value of the amplitude amplification signal RN is shifted to the high level side by the voltage VU with respect to the ground voltage VSS, and the maximum value is The power supply voltage VCC is shifted to the lower level by the voltage VD.

  In short, the waveform control stage 4 absorbs current from the line LL2 when the received data signal RDS is higher than the threshold value Vth, and discharges current to the line LL2 when the received data signal RDS is lower than the threshold value Vth. As shown in FIG. 2, the amplitude of the amplified signal RN is suppressed to an amplitude F smaller than the amplitude (VCC-VSS). Since the amplitude reduction amount by the waveform control stage 4 increases as the amplitude of the amplitude amplification signal RN increases, the interval in which the amplitude decreases due to the short change period of the amplitude amplification signal RN as shown in the interval T2 in FIG. Then, the amount of amplitude reduction by the waveform control stage 4 is small.

  Therefore, according to the waveform control stage 4, at the rising edge portion (or falling edge portion) of the amplitude amplified signal RN, the signal level changes from the peak value on the low level side (or high level side) to the high level side (or low level). The time for transitioning to the peak value on the level side is shortened. As a result, the signal level is immediately brought to the threshold value, particularly in the initial period in which the level transition of the amplitude amplification signal RN is started after the section (eg, T1) in which the amplitude amplification signal RN has a long change period ends. Is possible.

  Therefore, according to the data receiving circuit 10 shown in FIG. 1, the amplitude amplified signal RN with less delay or waveform dullness is generated by the operation of the waveform control stage 4 described above, and therefore, the received signal (IN, INB) can obtain a binary data signal (RDS) with high accuracy.

  FIG. 3 is a circuit diagram showing a modification of the data receiving circuit 10 shown in FIG.

  In the data receiving circuit 10 shown in FIG. 3, the configuration other than the internal configuration of the waveform control stage 4 is the same as that shown in FIG.

In the waveform control stage 4 shown in FIG. 3, the power supply voltage VCC is applied to the source terminal of the transistor 41 to which the bias voltage VB _{1 as} described above is supplied to the gate terminal, and the drain terminal is the source terminal of the transistor 42. It is connected to the. A reception data signal RDS is supplied to the gate terminal of the transistor 42, and its drain terminal is connected to the line LL2. The ground voltage VSS is applied to the source terminal of the transistor 43 to which the bias voltage VB ₂ as described above is supplied to the gate terminal, and the drain terminal is connected to the source terminal of the transistor 44. A reception data signal RDS is supplied to the gate terminal of the transistor 44, and its drain terminal is connected to the line LL2.

  That is, the waveform control stage 4 shown in FIG. 3 sets the connection positions of the transistor 42 (44) and the transistor 41 (43) connected in series between the power supply voltage VCC (ground voltage VSS) and the line LL2 in FIG. It has been replaced. At this time, the operation of the waveform control stage 4 itself is the same as when the configuration shown in FIG. 1 is adopted. However, in the configuration shown in FIG. 3, the power supply voltage VCC (ground voltage VSS) is always supplied to the transistor 41 (43) without passing through the transistor 42 (44) that is controlled to be turned on / off according to the received data signal RDS. The parasitic capacitance of the transistor 41 (43) is charged in advance. Therefore, when the configuration shown in FIG. 3 is adopted as the waveform control stage 4, it becomes possible to suppress the waveform dullness with respect to the amplitude amplified signal RN more than when the configuration shown in FIG. 1 is adopted.

Further, in the waveform control stage 4 shown in FIG. 1 or FIG. 3, in order to set the current sent to the line LL2 or sucked from the line LL2 to a predetermined current, the bias voltage VB ₁ (VB ₂ ) is supplied to its gate terminal. However, the present invention is not limited to this configuration.

  For example, in place of the transistors 41 and 43 in the waveform control stage 4 shown in FIG. 3, the p-channel as shown in FIG. 4A manufactured so that the above-described predetermined current flows between the source and drain terminals in the on state. A MOS transistor 410 and an n-channel MOS transistor 430 may be employed.

  In the waveform control stage 4 shown in FIG. 4A, the power supply voltage VCC is applied to the source terminal of the transistor 410, and the source terminal of the transistor 42 is connected to its drain terminal. A ground voltage VSS for fixing the transistor 410 to an ON state is applied to the gate terminal of the transistor 410. On the other hand, the ground voltage VSS is applied to the source terminal of the transistor 430, and the source terminal of the transistor 44 is connected to the drain terminal thereof. A power supply voltage VCC for fixing the transistor 430 to the ON state is applied to the gate terminal of the transistor 430. The reception data signal RDS is supplied to the gate terminals of the transistors 42 and 44, and both drain terminals are connected to the line LL2.

  Further, for example, in place of the transistors 41 and 43 in the waveform control stage 4 shown in FIG. 3, the above-described predetermined current is produced between the source and drain terminals when the diode is connected, as shown in FIG. 4B. A channel MOS transistor 411 and an n channel MOS transistor 431 may be employed.

  In the waveform control stage 4 shown in FIG. 4B, the power supply voltage VCC is applied to the source terminal of the transistor 411, and its drain terminal and gate terminal are connected to the source terminal of the transistor 42. On the other hand, the ground voltage VSS is applied to the source terminal of the transistor 431, and its drain terminal and gate terminal are connected to the source terminal of the transistor 44. The reception data signal RDS is supplied to the gate terminals of the transistors 42 and 44, and both drain terminals are connected to the line LL2.

As described above, if the internal configuration as shown in FIG. 4A or 4B is adopted as the waveform control stage 4, the bias voltage VB ₁ required when the configuration shown in FIG. 1 or 3 is adopted. And a wiring pattern for supplying VB ₂ is not necessary. Therefore, the chip occupation area can be reduced as compared with the case where the configuration shown in FIG. 1 or FIG. 3 is adopted.

  In the above embodiment, the waveform control stage 4 performs waveform control to limit the amplitude of the amplitude amplified signal RN, but the rising (or falling) edge portion of the amplitude amplified signal RN is steep. You may make it perform the waveform control of making.

  FIG. 5 is a circuit diagram showing another example of the configuration of the data receiving circuit 10 according to the present invention made in view of the above point.

In the data reception circuit 10 shown in FIG. 5, instead of the reception data signal RDS, a signal transmitted from the inverter 31 _n-1 of the output stage 3, that is, inverted reception data obtained by inverting the logic level of the reception data signal RDS. The signal RDV is supplied to the waveform control stage 4, and the other configuration is the same as that shown in FIG.

  That is, in the configuration shown in FIG. 5, the waveform control stage 4 discharges a predetermined current to the line LL2 when the received data signal RDS indicates logic level 1, as shown in FIG. Is drawn in a predetermined current from the line LL2.

  Therefore, while the rising edge portion of the amplitude amplification signal RN is generated by the level conversion stage 2, the waveform control stage 4 discharges current on the line LL2. Therefore, at this time, not only the level conversion stage 2 but also the waveform control stage 4 sends out current to the line LL2, so that the rising edge portion of the amplitude amplified signal RN as shown by the one-dot chain line in FIG. The level transition with the passage of time in the region becomes steep. Further, while the falling edge portion of the amplitude amplified signal RN is generated by the level conversion stage 2, the waveform control stage 4 sucks current from the line LL2. Therefore, at this time, not only the level conversion stage 2 but also the waveform control stage 4 draws the current from the line LL2, so that, as shown by the one-dot chain line in FIG. The level transition with the passage of time becomes steep.

  Therefore, according to the configuration shown in FIG. 5, the rising and falling edges of the amplitude amplified signal RN are steep, so that a binary data signal (IN, INB) with high accuracy can be obtained from the received signal (IN, INB) transmitted at high speed. RDS) can be acquired.

  In the above embodiment, the p-channel transistors 11 and 12 are used as the transistors that receive the differential signals IN and INB. However, n-channel MOS transistors are used as the transistors 11 and 12. Anyway. One of the transistors 11 and 12 may be an n-channel MOS transistor and the other may be a p-channel MOS transistor.

Further, in the embodiment shown in FIG. 1 or FIG. 3, as the reception data signal RDS supplied to the gate terminals of the transistors 42 and 44 of the waveform control stage 4, the final stage of the inverters 31 _{1 to} 31 _n of the output stage 3 is used. it is used the output signal of the inverter 31 _n, if the output signal of the even-numbered inverters of the inverter 31 ₁ to 31 _n, may be any one.

In the embodiment shown in FIG. 5, the output signal of the inverter 31 _{n−1 in} the output stage 3 is used as the inverted reception data signal RDV supplied to the gate terminals of the transistors 42 and 44 in the waveform control stage 4. Any of the output signals of the odd-numbered inverters among the inverters 31 _{1 to} 31 _n may be used.

  In short, the data receiving circuit (10) according to the present invention sends an amplitude amplified signal (RN) obtained by amplifying the amplitude of the received signal (IN, INB) onto the first line (LL2), and on the first line. When the signal is binarized and output as a received data signal (RDS), waveform control is performed on the amplitude amplified signal as follows. That is, according to the received data signal, the amplitude of the amplitude amplified signal is suppressed by discharging the current on the first line or sucking the current from the first line, or with the passage of time at the edge of the amplitude amplified signal. Waveform control that makes the level transition steep is performed on the amplitude amplified signal. As a result, an amplitude amplified signal with less delay or waveform dullness is generated, so that a binary data signal can be obtained with high accuracy even from a received signal transmitted at high speed.

  Note that the data receiving circuit according to the present invention can be used for a semiconductor device having a driving circuit that generates a signal for controlling driving of the display device in accordance with an output of the data receiving circuit, for example.

1 differential amplification stage 2 level conversion stage 3 output stage 4 waveform control stage

Claims (8)

A data receiving circuit including an amplifying unit that sends an amplitude-amplified signal obtained by amplifying the amplitude of the received signal onto a first line, and an output unit that binarizes the signal on the first line and outputs the signal as a received data signal Because
A data receiving circuit comprising: a waveform control unit that controls a waveform of the amplitude amplified signal by discharging a current on the first line or sucking a current from the first line according to the received data signal .   The waveform controller sucks current from the first line when the received data signal is higher than a predetermined threshold value, and discharges current to the first line when the received data signal is lower than the predetermined threshold value. The data receiving circuit according to claim 1, further comprising a complementary circuit that suppresses an amplitude of the amplitude amplified signal. The waveform controller includes a first MOS transistor having a drain terminal connected to the first line and a gate terminal applied with a predetermined first bias voltage;
A second MOS transistor for supplying a high voltage to the source terminal of the first MOS transistor in response to the received data signal;
A third MOS transistor having a drain terminal connected to the first line and a predetermined second bias voltage applied to the gate terminal;
3. The data receiving circuit according to claim 1, further comprising a fourth MOS transistor that supplies a low voltage to a source terminal of the third MOS transistor in accordance with the received data signal. The waveform control unit includes a first MOS transistor in which a high voltage is supplied to a source terminal and a predetermined first bias voltage is applied to a gate terminal;
A second MOS transistor for applying a voltage at the drain terminal of the first MOS transistor to the first line in response to the received data signal;
A third MOS transistor in which a low voltage is supplied to the source terminal and a predetermined second bias voltage is applied to the gate terminal;
3. The data receiving circuit according to claim 1, further comprising: a fourth MOS transistor that applies a voltage at a drain terminal of the third MOS transistor to the first line in accordance with the received data signal.   5. The data receiving circuit according to claim 3, wherein the first bias voltage is the low voltage and the second bias voltage is the high voltage. The waveform control unit includes a first MOS transistor in which a high voltage is supplied to a source terminal and a gate terminal and a drain terminal are connected to each other;
A second MOS transistor for applying a voltage at the drain terminal of the first MOS transistor to the first line in response to the received data signal;
A third MOS transistor in which a low voltage is supplied to the source terminal and the gate terminal and the drain terminal are connected to each other;
3. The data receiving circuit according to claim 1, further comprising: a fourth MOS transistor that applies a voltage at a drain terminal of the third MOS transistor to the first line in accordance with the received data signal.   The waveform controller discharges current to the first line when the received data signal is higher than a predetermined threshold value, and sucks current from the first line when the received data signal is lower than the predetermined threshold value. 2. The data receiving circuit according to claim 1, wherein a level transition with a lapse of time at a rising edge portion and a falling edge portion of the amplitude amplified signal is made steep. A data receiving circuit according to any one of claims 1 to 7,
A semiconductor device comprising: a drive circuit that generates a control signal for driving the display device in accordance with an output of the data receiving circuit.

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