JP2014049501A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit defects caused by a short-circuit between a wire for a semiconductor chip in an upper stage and a wire for a semiconductor chip in a lower stage in a mold process of a semiconductor device in which semiconductor chips of the same kind are stacked on a wiring board in a step-like manner.SOLUTION: A semiconductor device manufacturing method comprises a mold process of stacking a plurality of semiconductor chips of the same kind each of which has a plurality of bonding pads which are formed along a first edge and have metal layers on surfaces in a step-like manner, respectively, and connecting the other end of a wire connected to the bonding pad of the semiconductor chip in an upper stage to a bonding lead of the wiring board without being routed through the bonding pad of the semiconductor chip in a lower stage. In the mold process, an encapsulation resin is supplied from a second edge side opposite to the first edge toward the first edge side.

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, a semiconductor in which semiconductor chips of the same type are stacked on a wiring board, and the electrode pads of these semiconductor chips and the electrode pads of the wiring board are electrically connected via wires. The present invention relates to a technique effective when applied to the manufacture of a device.

  Patent Document 1 discloses nickel (Ni) as a constituent material of a bonding pad (electrode pad) to which a wire made of gold (Au) is connected in a semiconductor device in which different types of semiconductor chips are stacked stepwise on a wiring board. A metal layer in which a gold (Au) film is laminated on the top of the film is disclosed.

  Also, semiconductor chips of the same type (for example, memory chips) are stacked on the wiring board in a stepped manner, and the bonding pads of these semiconductor chips and the bonding leads (electrode pads) of the wiring board are electrically connected via wires. Semiconductor devices are known (see, for example, FIG. 18 of Patent Document 2, FIG. 3 of Patent Document 3, and FIG. 42 of Patent Document 4).

JP 2003-152014 A JP 2008-251917 A JP 2007-103423 A JP 2007-19415 A

  In the case of a semiconductor device in which semiconductor chips of the same type are stacked on a wiring board in a step-like manner as in Patent Document 2 to Patent Document 4 described above, bonding pads of the upper semiconductor chip and bonding leads of the wiring board are connected via wires. There are two bonding methods that can be used for electrical connection.

  The first method is to connect the other end of the wire, one end of which is connected to the bonding pad of the upper semiconductor chip, to the same type of bonding pad of the lower semiconductor chip, and the wiring board via this bonding pad. This is a method of connecting to a bonding lead (see FIGS. 6 to 8 of Patent Document 4). The second method is a method of directly connecting the other end of the wire whose one end is connected to the bonding pad of the upper semiconductor chip to the bonding lead of the wiring board.

  In recent years, the bonding pad diameter of a semiconductor chip tends to be reduced due to the downsizing of a semiconductor device. As a result, the diameter of the wire to be used is also reduced, so that the bonding area between the wire and the bonding pad, and hence the bonding strength, is reduced, and the wire is easily peeled off from the bonding pad. In particular, when the above-described first method is adopted, bonding is performed a plurality of times to the bonding pads of the lower semiconductor chip to which the upper semiconductor chip wire and the lower semiconductor chip wire are respectively connected. Since an impact is applied, peeling of the wire easily occurs on the surface.

  One cause of the decrease in bonding strength between the wire and the bonding pad is an oxide film formed on the surface of copper (Cu) or aluminum (Al) constituting the bonding pad. Therefore, the inventor of the present application examined the formation of a metal film for preventing oxidation on the surface (outermost surface) of the bonding pad as a measure for suppressing the surface oxidation of the bonding pad. At this time, as a material for the metal film, aluminum (Al) or expensive gold (Au) should not be used in consideration of the manufacturing cost of the semiconductor device or a bonding form other than wire bonding (for example, solder bonding). It was investigated.

  However, it has been found that when a material other than gold (Au) or aluminum (Al) is used as the material of the metal film, an alloying reaction with a wire made of gold (Au) hardly occurs. Therefore, when a material other than gold (Au) or aluminum (Al) is used as the metal film for preventing oxidation and the first bonding method described above is adopted, gold (Au) is formed on the surface of the bonding pad of the lower semiconductor chip. Wire peeling occurred.

  On the other hand, when the second method, which has a smaller impact on the bonding pad than the first method, is adopted, a material other than gold (Au) or aluminum (Al) is used as a metal film for preventing oxidation. Moreover, it became possible to suppress peeling of the gold (Au) wire.

  However, when the second method is adopted, the upper semiconductor chip wire becomes long, so that in the subsequent molding process, the upper semiconductor chip wire and the lower semiconductor chip wire are short-circuited. There has occurred.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the means for solving the problems disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method for manufacturing a semiconductor device according to an embodiment of the present application is as follows.
(A) preparing a wiring board having a plurality of bonding leads formed on the upper surface;
(B) A first semiconductor chip having a plurality of first bonding pads formed along the first side of the first surface, and a first metal layer formed on each surface of the plurality of first bonding pads. Mounting on the upper surface of the wiring board such that the first back surface of the first semiconductor chip faces the upper surface of the wiring board;
(C) having a plurality of second bonding pads formed along the first side of the second surface, and a second metal layer formed on each surface of the plurality of second bonding pads, and A second semiconductor chip of the same type as the one semiconductor chip, the second back surface of the second semiconductor chip facing the first surface of the first semiconductor chip and in the same direction as the first semiconductor chip; And mounting on the first surface of the first semiconductor chip such that the plurality of first bonding pads of the first semiconductor chip are exposed from the second semiconductor chip;
(D) electrically connecting the plurality of first bonding pads of the first semiconductor chip and the plurality of bonding leads of the wiring board via a plurality of first wires;
(E) electrically connecting the plurality of second bonding pads of the second semiconductor chip and the plurality of bonding leads of the wiring board via a plurality of second wires;
(F) sealing the upper surface of the wiring board, the first and second semiconductor chips, and the plurality of first and second wires with a resin;
Have
In the step (f), the first side of the first surface from the second side of the first surface facing the first side of the first surface on which the plurality of first bonding pads are formed. Toward the substrate.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In manufacturing a semiconductor device in which semiconductor chips of the same type are stacked stepwise on a wiring board, an anti-oxidation metal film made of a material other than gold (Au) or aluminum (Al) is formed on the surface of the bonding pads of the semiconductor chip. Even when formed, it is possible to suppress both the peeling of the wire during wire bonding and the short circuit between the wires during molding.

1 is a partially broken plan view of a semiconductor device according to a first embodiment. 2 is a plan view of the lower surface side of the semiconductor device of First Embodiment; FIG. 2 is a cross-sectional view of the semiconductor device of First Embodiment. FIG. 4 is a partial enlarged cross-sectional view of the semiconductor device of First Embodiment; FIG. It is a top view of the semiconductor chip mounted in the upper surface of a wiring board. It is a partial expanded sectional view of the semiconductor chip mounted in the upper surface of a wiring board. 3 is a plan view showing an upper surface of a large wiring board used for manufacturing the semiconductor device of the first embodiment. FIG. 4 is a plan view showing a lower surface of a large wiring board used for manufacturing the semiconductor device of the first embodiment. FIG. It is the sectional view on the AA line of FIG. 4 is a plan view of a semiconductor wafer used for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a plan view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. FIG. 6 is a partially enlarged cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 12 is a plan view illustrating a method for manufacturing the semiconductor device following FIG. 11. FIG. 13 is a partially enlarged cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 12. FIG. 14 is a partially enlarged plan view illustrating the method for manufacturing the semiconductor device following FIG. 13. FIG. 15 is a partially enlarged cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 14; FIG. 16 is a partially enlarged plan view illustrating the method for manufacturing the semiconductor device following FIG. 15; FIG. 17 is a partial enlarged cross-sectional view showing the manufacturing method of the semiconductor device following FIG. 16; It is a schematic plan view of the shaping die used at a molding process. It is a schematic sectional drawing of the shaping die used at a molding process. FIG. 18 is a schematic plan view showing the method for manufacturing the semiconductor device following FIG. 17. FIG. 19 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 18. FIG. 22 is a schematic plan view illustrating the method for manufacturing the semiconductor device following FIG. 21. FIG. 23 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device following FIG. 22. It is a top view which shows the large sized wiring board taken out from the shaping die. It is a schematic sectional drawing which shows the large sized wiring board taken out from the shaping die. FIG. 27 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 26; FIG. 28 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 27; 7 is a schematic plan view of a semiconductor device which is a modification of the first embodiment. FIG. FIG. 6 is a schematic plan view of a semiconductor device according to a second embodiment. FIG. 10 is a partially broken plan view of a semiconductor device that is a modification of the second embodiment. 7 is a partially broken plan view of a semiconductor device according to Modification 1. FIG. 6 is a partially enlarged cross-sectional view of a semiconductor device according to Modification 1. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. Furthermore, in the drawings for describing the embodiments, hatching may be applied even in a plan view or hatching may be omitted even in a cross-sectional view for easy understanding of the configuration.

(Embodiment 1)
<Semiconductor device>
FIG. 1 is a partially broken plan view of the semiconductor device of the first embodiment. FIG. 2 is a bottom plan view of the semiconductor device. FIG. 3 is a cross-sectional view of this semiconductor device. FIG. 4 is a partially enlarged sectional view of this semiconductor device.

  In the semiconductor device 10A according to the first embodiment, two semiconductor chips 12 (12A, 12B) are stacked on the upper surface (surface, chip mounting surface) of the wiring substrate 11, and the lower surface of the wiring substrate 11 (on the opposite side to the upper surface). This is a BGA (Ball Grid Array) type semiconductor device in which a plurality of solder balls (solder materials) 14 are connected to a surface, a back surface, and a mounting surface. The planar shape of the semiconductor device 10A is a quadrangle, the length of one side is, for example, 17 mm, and the thickness is, for example, 0.8 mm.

  For example, the wiring board 11 having a quadrangular planar shape includes a core layer (insulating base material) 15 in which resin is impregnated with glass fiber or carbon fiber, and four-layer wirings 16L, 17L, 18L made of copper (Cu), 19L, a through-hole wiring 20 that electrically connects the four-layer wirings 16L to 19L to each other, and a two-layer solder resist (insulating layer) 21 that protects the uppermost wiring 16L and the lowermost wiring 19L. ing. In FIG. 1, the illustration of the wiring 16L in the region covered with the solder resist 21 is omitted, and the illustration of the wiring 19L in the region covered with the solder resist 21 is omitted in FIG.

  A semiconductor chip (first semiconductor chip) 12A is mounted on the central portion (chip mounting region) of the upper surface of the wiring board 11, and a semiconductor chip (second semiconductor chip) 12B is mounted on the semiconductor chip 12A. Are stacked. A plurality of bonding leads (electrode pads) 16 are formed on the upper surface of the wiring substrate 11 at the periphery of the area where the two semiconductor chips 12 (12A, 12B) are mounted.

  The plurality of bonding leads 16 are arranged in a line along one side of the wiring board 11. These bonding leads 16 are formed by opening a part of the solder resist 21 covering the upper surface of the wiring substrate 11 and exposing one end of each of the plurality of wirings 16L. As shown in FIG. 4, a metal layer 22 in which a gold (Au) film is laminated on a nickel (Ni) film, for example, is formed on the surface of these bonding leads 16 by a plating method.

  On the other hand, a plurality of bump lands (electrode pads) 19 are formed on the lower surface of the wiring board 11. These bump lands 19 are arranged in an array over almost the entire lower surface of the wiring board 11. These bump lands 19 are formed by opening a part of the solder resist 21 covering the lower surface of the wiring substrate 11 and exposing one end of each of the plurality of wirings 19L. On the surface of these bump lands 19, for example, a metal layer 23 in which a gold (Au) film is laminated on a nickel (Ni) film is formed by a plating method.

  A solder ball (solder material) 14 constituting an external terminal of the semiconductor device 10A is connected to the surface of each of the plurality of bump lands 19. The semiconductor device 10A according to the first embodiment is mounted on a mounting board (motherboard) (not shown) via these solder balls 14. That is, the wiring substrate 11 of the semiconductor device 10A functions as an interposer substrate for connecting the two semiconductor chips 12 (12A, 12B) mounted on the upper surface thereof to the mounting substrate (motherboard).

  The plurality of solder balls 14 are made of so-called lead-free solder substantially free of lead (Pb), for example, only tin (Sn), tin-bismuth (Sn-Bi) alloy, or tin-copper-silver. (Sn—Cu—Ag) alloy or the like. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of Hazardous Substances) directive.

<Semiconductor chip>
FIG. 5 is a plan view of the semiconductor chip 12 mounted on the upper surface of the wiring board 11. FIG. 6 is a partially enlarged cross-sectional view of the semiconductor chip 12.

  The semiconductor chip 12 (12A, 12B) is a memory chip in which a flash memory (not shown) is formed on the main surface (surface, element formation surface) of a single crystal silicon substrate having a square planar shape. A plurality of bonding pads (electrode pads) 24 constituting external terminals of the flash memory are formed in the peripheral portion. These bonding pads 24 are arranged in a line along one side of the semiconductor chip 12. That is, the two semiconductor chips 12 (12A, 12B) mounted on the upper surface of the wiring substrate 11 are the same type of memory chip, and are bonding pads that constitute independent signal terminals such as chip select terminals, for example. Except for 24, the type (signal, power supply) and arrangement of the bonding pads 24 are also the same.

  As shown in FIG. 6, for example, a silicon substrate 30 having p-type conductivity is exposed on the back surface (surface opposite to the main surface) of the semiconductor chip 12. A p-type well 31 and an element isolation trench 32 are formed in the silicon substrate 30, and an n-channel MOS transistor (Qn) is formed in the p-type well 31. Note that other semiconductor elements constituting the flash memory, such as a p-channel MOS transistor, are also formed on the actual silicon substrate 30, but these are not shown.

  A wiring for connecting the semiconductor elements is formed above the n-channel MOS transistor (Qn). The wiring connecting the semiconductor elements generally has a multilayer wiring structure of about 3 to 10 layers, but in FIG. 6, as an example of the multilayer wiring, the wiring is composed of a metal film made of copper (Cu). Three-layer wiring (first-layer wiring 33, second-layer wiring 34, and third-layer wiring 35) is shown. Further, between the n-channel MIS transistor (Qn) and the first layer wiring 33, between the first layer wiring 33 and the second layer wiring 34, and between the second layer wiring 34 and the third layer wiring 35. Interlayer insulating films 36, 37, and 38 each formed of a silicon oxide film or the like are formed.

  A surface protective film (passivation film) 39 for protecting the integrated circuit (flash memory) is formed on the upper part of the third layer wiring 35 (the surface of the semiconductor chip 12). The surface protective film 39 is made of, for example, an insulating film in which a silicon oxide film and a silicon nitride film are stacked. Further, a plurality of the bonding pads 24 described above are formed on the surface of the semiconductor chip 12 by opening a part of the surface protection film 39 and exposing one end of the third layer wiring 35.

  On each surface (wire connection surface) of the plurality of bonding pads 24, for example, a metal layer 25 in which a palladium (Pd) film is laminated on a nickel (Ni) film is formed by a plating method. One end of a wire 26 made of gold (Au) is electrically connected to the surface of the bonding pad 24 on which the metal layer 25 is formed. That is, the bonding pad 24 and the wire 26 are electrically connected by a gold (Au) -palladium (Pd) bond. The material of the metal layer 25 is not limited to palladium (Pd). For example, platinum (Pt) may be used as the same platinum group element. However, in consideration of manufacturing costs, palladium (Pd) is more preferable. preferable.

  As shown in FIGS. 3 and 4, of the two semiconductor chips 12 </ b> A and 12 </ b> B mounted on the upper surface of the wiring substrate 11, the lower semiconductor chip 12 </ b> A has the back surface (first back surface) as the upper surface of the wiring substrate 11. And is mounted on the upper surface of the wiring substrate 11 with an adhesive (die bond material) 27 interposed therebetween. The adhesive 27 provided between the back surface of the semiconductor chip 12A and the upper surface (solder resist 21) of the wiring board 11 is a function of a die bond material called a die attach film (DAF), for example, and a dicing tape. It is a film adhesive that also functions. Although Embodiment 1 describes the use of a film-like adhesive, a paste-like adhesive may be used.

  The other end of the wire (first wire) 26 electrically connected to the bonding pad (first bonding pad) 24 on the main surface of the semiconductor chip 12 </ b> A is electrically connected to the bonding lead 16 on the upper surface of the wiring substrate 11. It is connected.

  The upper semiconductor chip 12B stacked on top of the semiconductor chip 12A is oriented so that the back surface (second back surface) faces the main surface of the lower semiconductor chip 12A, and the semiconductor chip 12A is interposed via an adhesive 27. It is mounted on the main surface. The adhesive 27 is the same type of adhesive (die attach film) as the adhesive 27 provided between the back surface of the semiconductor chip 12 </ b> A and the top surface of the wiring substrate 11.

  The semiconductor chip 12B is mounted at a position shifted from the semiconductor chip 12A so that the bonding leads 16 formed on the main surface of the lower semiconductor chip 12A are exposed. The other end of the wire (second wire) 26 electrically connected to the bonding pad (second bonding pad) 24 on the main surface of the semiconductor chip 12B is electrically connected to the bonding lead 16 on the upper surface of the wiring substrate 11. It is connected.

  That is, the other end of the wire 26 electrically connected to the bonding pad 24 of the upper semiconductor chip 12B does not pass through the bonding pad 24 formed on the main surface of the lower semiconductor chip 12A. It is directly connected to the bonding lead 16.

  The two semiconductor chips 12A and 12B and the plurality of wires 26 are sealed by a resin sealing body 28 that covers the entire top surface of the wiring board 11. The resin sealing body 28 is made of, for example, a thermosetting epoxy resin containing a silicon filler.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device 10A of the first embodiment having the above configuration will be described.

1. Substrate and chip preparation process:
FIG. 7 is a plan view showing the upper surface of a large-sized wiring board used for manufacturing the semiconductor device of the first embodiment. FIG. 8 is a plan view showing the lower surface of the large wiring board. FIG. 9 is a cross-sectional view showing a device region (AA line in FIG. 7) of this large-sized wiring board.

  The large-sized wiring board 100 is a wiring board having a rectangular planar shape, and is divided into a plurality of (here, six) device regions by dicing lines DL indicated by two-dot chain lines in FIGS. The large wiring board 100 is also called a MAP (Mold Array Package) board or a multi-wiring board.

  Each of the plurality of device regions is a region that becomes the wiring substrate 11 of the semiconductor device 10A described above when the large wiring substrate 100 is cut along the outer edge (dicing line DL) of the device region. Have the same structure. That is, the central portion of the upper surface of each device region is a chip mounting region (first chip mounting region), and a plurality of bonding leads 16 are formed in a row around the chip mounting region. A plurality of bump lands 19 are formed in an array on the lower surface of each device region. Further, the upper and lower surfaces of each device region are covered with a solder resist 21 except for the region where the bonding leads 16 and the bump lands 19 are formed.

  Further, in parallel with the step of preparing the large wiring substrate 100, the semiconductor wafer 13 shown in FIG. 10 is diced (cut) to be separated into a plurality of semiconductor chips 12. The semiconductor wafer 13 before dicing is partitioned into a plurality of chip regions, and a flash memory is formed on the main surface of each chip region by a normal wafer process (previous process).

  A plurality of bonding pads 24 are formed on the main surface of each chip region by a normal wafer process (previous process). Then, on each surface of the plurality of bonding pads 24, a metal layer 25 (FIG. 6) in which a palladium (Pd) film is laminated on a nickel (Ni) film, for example, by immersing the semiconductor wafer 13 in an electrolytic plating bath. Reference) is formed.

  When the semiconductor wafer 13 is diced, the die attach film (adhesive 27) is attached to the back surface of the semiconductor wafer 13, and the semiconductor wafer 13 and the die attach film (adhesive 27) are cut simultaneously. Thereby, the die attach film (adhesive 27) of the same dimension as the semiconductor chip 12 remains on the back surface of each of the semiconductor chips 12 separated into pieces.

2. Die bonding process:
The large wiring substrate 100 and the semiconductor chip 12 are transferred to a die bonding process. In the die bonding process, first, as shown in FIGS. 11 and 12, a semiconductor chip 12A is mounted on the upper surface (chip mounting area of each device area) of the large-sized wiring board 100.

  The semiconductor chip 12A is mounted by a so-called face-up mounting method in which the back surface of the semiconductor chip 12A (the surface on which the adhesive 27 is attached) is opposed to the upper surface of the large-sized wiring board 100. That is, after attaching the back surface of the semiconductor chip 12A to the upper surface of the large-sized wiring board 100 via the adhesive 27, the large-sized wiring board 100 is heated to cure the adhesive 27, whereby the semiconductor chip 12A is fixed to the large-sized wiring board. It fixes to the upper surface of 100.

  Next, as shown in FIGS. 13 and 14, the semiconductor chip 12B is mounted on the main surface of each semiconductor chip 12A. The semiconductor chip 12B is mounted by a face-up mounting method in which the back surface of the semiconductor chip 12B (the surface to which the adhesive 27 is attached) is opposed to the main surface of the lower semiconductor chip 12A.

  Specifically, first, the back surface of the semiconductor chip 12B is attached to the main surface of the lower semiconductor chip 12A via the adhesive 27. At that time, the direction of the semiconductor chip 12B is made the same as that of the lower semiconductor chip 12A. Further, the semiconductor chip 12B is stacked with being shifted from the semiconductor chip 12A so that the plurality of bonding pads 24 formed on the main surface of the lower semiconductor chip 12A are exposed. Next, the large-sized wiring substrate 100 is heated to cure the adhesive 27, thereby fixing the semiconductor chip 12B to the main surface of the lower semiconductor chip 12A.

3. Wire bonding process:
The large-sized wiring board 100 on which the mounting of the semiconductor chips 12A and 12B is completed is transferred to the wire bonding process. In the wire bonding step, first, as shown in FIGS. 15 and 16, a plurality of bonding leads 16 formed in each device region of the large-sized wiring board 100 and a plurality of bonding leads 16 formed on the main surface of the lower semiconductor chip 12A. The bonding pad 24 is electrically connected by a low loop wire (first wire) 26.

  This bonding is performed by a well-known ball bonding method using heat and ultrasonic waves. This bonding is performed by a positive bonding method in which the bonding pad 24 side of the semiconductor chip 12A is the first bonding and the bonding lead 16 side of the large-sized wiring substrate 100 is the second bonding. That is, a ball portion is first formed at the tip of the wire 26, the ball portion is connected to the bonding pad 24 of the semiconductor chip 12 A, and then the other end of the wire 26 is connected to the bonding lead 16 of the large-sized wiring board 100.

  Next, as shown in FIGS. 17 and 18, a plurality of bonding leads 16 formed in each device region of the large-sized wiring substrate 100, and a plurality of bonding pads 24 formed on the main surface of the upper semiconductor chip 12B, Are electrically connected by a high loop wire (second wire) 26.

  This bonding is performed by a well-known ball bonding method using heat and ultrasonic waves as in the low-loop bonding described above. This bonding is performed by a positive bonding method in which the bonding pad 24 side of the semiconductor chip 12B is the first bonding and the bonding lead 16 side of the large-sized wiring substrate 100 is the second bonding. That is, a ball portion is first formed at the tip of the wire 26, the ball portion is connected to the bonding pad 24 of the semiconductor chip 12 </ b> B, and the other end of the wire 26 is connected to the bonding lead 16 of the large wiring substrate 100. In other words, the other end of the wire 26 electrically connected to the bonding pad 24 of the upper semiconductor chip 12B does not go through the bonding pad 24 formed on the main surface of the lower semiconductor chip 12A, and the large wiring board. Directly connected to 100 bonding leads 16.

  As described above, the lower semiconductor chip 12A and the upper semiconductor chip 12B are the same type of memory chips. Accordingly, wires connected to the bonding pads 24 constituting the terminals (signal terminals, power supply terminals) common to the semiconductor chips 12A and 12B, excluding the bonding pads 24 constituting the signal terminals independent of each other such as chip select terminals. Each other end of 26 is connected to the same (common) bonding lead 16 of the large-sized wiring board 100.

4). Molding process:
The large-sized wiring board 100 in which the bonding of the wire 26 is completed is transferred to a molding process. FIG. 19 is a schematic plan view of a molding die used in the molding process. FIG. 20 is a schematic cross-sectional view of this molding die.

  In the molding process, first, the large-sized wiring board 100 on which the plurality of semiconductor chips 12 are mounted is mounted on the molding die 40 shown in FIGS. The molding die 40 has an upper die 41 having an inner surface provided with a cavity 45, and a lower die 42 facing the upper die 41. The large wiring substrate 100 is fixed to the lower mold 42 so that the upper surface thereof is exposed in the cavity 45. In other words, the large wiring board 100 is disposed between the upper mold 41 and the lower mold 42 so that the plurality of semiconductor chips 12 are positioned in one cavity 45.

  The upper mold 41 of the molding die 40 has a rectangular planar shape, and a plurality of gates 43 are provided on one of the long sides. Sealing resin melted in an injection sleeve (not shown) outside the molding die 40 is press-fitted into the cavity 45 through these gates 43. On the other hand, a plurality of air vents 44 for discharging the gas in the cavity 45 are provided on the other long side of the upper mold 41. That is, the molding die 40 employs a so-called side gate method in which a sealing resin is injected from one side of the rectangular cavity 45 toward the other side facing the one side.

  As shown in FIG. 19, when the large wiring board 100 is mounted on the molding die 40, the long side of the large wiring board 100 whose planar shape is a rectangle is the upper side of the upper mold 41 provided with the gate 43 and the air vent 44. The long side is parallel to the long side, and the short side of the large wiring substrate 100 is parallel to the short side of the upper die 41.

  At this time, each of the plurality of semiconductor chips 12A and 12B mounted on the upper surface of the large-sized wiring substrate 100 is parallel to the arrangement direction (bonding pad row direction) of the plurality of bonding pads 24 and close to the bonding pads 24. One side is arranged at a position away from the gate 43, and the other side opposite to the one side is arranged at a position near the gate 43.

  In other words, each of the plurality of semiconductor chips 12A and 12B is arranged such that two sides parallel to the bonding pad row direction are perpendicular to the flow direction of the sealing resin injected into the cavity 45. Therefore, the extending direction of the plurality of wires 26 that electrically connect the plurality of bonding pads 24 formed on each of the semiconductor chips 12A and 12B and the plurality of bonding leads 16 formed on the upper surface of the large-sized wiring substrate 100 is as follows. It becomes substantially parallel to the flow direction of the sealing resin.

  Next, as shown in FIGS. 21 to 24, the molten sealing resin 28 </ b> A is injected into the cavity 45 through a plurality of gates 43 provided in the upper mold 41, so that the upper surface of the large-sized wiring board 100 is mounted. All the semiconductor chips 12A and 12B and all the wires 26 thus formed are molded together. At this time, the upper surface of a dicing region (for example, a region adjacent to each other among a plurality of device regions) of the large wiring substrate 100 is also covered with the resin. Here, FIGS. 21 and 22 show the flow of the sealing resin 28 </ b> A immediately after being injected from the gate 43 into the cavity 45. 23 and 24 show a state in which the cavity 45 is filled with the sealing resin 28A thereafter.

  As described above, when the large wiring board 100 is mounted on the molding die 40, each of the plurality of semiconductor chips 12A and 12B mounted on the upper surface of the large wiring board 100 is parallel to the bonding pad row direction and bonded. One side close to the pad 24 is arranged at a position away from the gate 43. The extending direction of the plurality of wires 26 connecting the plurality of bonding pads 24 formed on each of the semiconductor chips 12A and 12B and the plurality of bonding leads 16 formed on the upper surface of the large-sized wiring board 100 is set in the cavity 45. It becomes substantially parallel to the flow direction of the sealing resin 28A injected into.

  As a result, since the resin is supplied from the other side opposite to the side close to the bonding pad 24, the influence of the injection pressure of the sealing resin 28A on the wire 26 can be minimized. In particular, the upper semiconductor chip 12B The deformation of the high-loop wire (second wire) 26 connected to the bonding pad 24 and having a long wire length can be effectively suppressed.

  Next, after the sealing resin 28 </ b> A filled in the cavity 45 is cured and the resin sealing body 28 is formed, the large wiring board 100 is taken out from the molding die 40. FIG. 25 is a plan view showing the large wiring board 100 taken out from the molding die 40. FIG. 26 is a schematic cross-sectional view showing this large-sized wiring board 100.

5. Ball mounting process:
The large-sized wiring board 100 that has completed the molding process is transported to the ball mounting process. Here, as shown in FIG. 27, the solder balls 14 are connected to the respective surfaces of the plurality of bump lands 19 formed on the lower surface of the large wiring substrate 100.

6). Individualization (dicing) process:
Next, as shown in FIG. 28, the dicing blade 46 is used to cut (dicing) the large-sized wiring board 100 and the resin sealing body 28 that covers the entire upper surface thereof. The large wiring substrate 100 and the sealing resin 28 are cut along a dicing line DL indicated by a two-dot chain line in FIGS. Thereby, the semiconductor device 10 </ b> A shown in FIGS. 1 to 4 is separated from the large wiring substrate 100.

  Thereafter, the separated semiconductor device 10 </ b> A is transported to the electrical characteristic inspection process, and the operation of the flash memory including whether the wire 26 is disconnected or short-circuited is checked. Subsequently, by performing an appearance inspection of the semiconductor device 10A, the semiconductor device 10A determined to be non-defective is selected. Through the steps so far, the manufacturing process of the semiconductor device 10A is completed.

  As described above, in the manufacturing method according to the first embodiment, of the two semiconductor chips 12A and 12B stacked stepwise on the upper surface of the wiring substrate 11, the connection is made to the bonding pad 24 of the upper semiconductor chip 12B. The other end of the formed wire 26 is directly connected to the bonding lead 16 of the wiring board 11 without going through the bonding pad 24 formed on the main surface of the lower semiconductor chip 12A.

  Thereby, in the wire bonding process, the impact applied to the bonding pad 24 of the lower semiconductor chip 12B can be reduced. Therefore, palladium (Pd) is used as the metal layer 25 for oxidation prevention formed on the bonding pad 24 of the semiconductor chip 12. Even in this case, it is possible to suppress a defect that the wire 26 peels from the surface of the bonding pad 24.

  Further, in the manufacturing method of the first embodiment, since the influence of the injection pressure of the sealing resin 28A on the wire 26 can be minimized in the molding process, the connection is particularly made to the bonding pad 24 of the upper semiconductor chip 12B. The deformation of the high loop wire 26 can be effectively suppressed.

  As a result, even when a system in which the other end of the wire 26 electrically connected to the bonding pad 24 of the upper semiconductor chip 12B is directly connected to the bonding lead 16 of the wiring substrate 11 is adopted, the wires 26 are short-circuited. Defects can be suppressed.

  In the case where the same type of semiconductor chips 12A and 12B are mounted on the upper surface of the wiring substrate 11, even if the wires 26 that are the paths through which the same signal or power supply (power supply potential, reference potential) flows are short-circuited, There is no particular problem. However, since deformation of the wire 26 to such an extent that the same type of wires 26 come into contact with each other may also be in contact with different types of wires 26, basically the same type of wires 26 are in contact with each other. However, it is preferable that they are not in contact with each other.

  In the present embodiment, the metal layer 25 for preventing oxidation formed on the surface of the bonding pad 24 of the semiconductor chip 12B is exemplified by a palladium (Pd) film laminated on the nickel (Ni) film. Any material other than those described above can be used as the metal layer 25 as long as it is a material mainly composed of palladium (Pd). The main component means a main material constituting the metal layer 25 and means that the metal layer 25 includes a case where a minute impurity or another metal material is contained.

  Further, the wire material that hardly causes an alloying reaction with the metal layer 25 containing palladium (Pd) as a main component is not limited to gold (Au), and is made of, for example, copper (Cu) or a copper (Cu) alloy. Even when a wire material is used, it is desirable to apply the manufacturing method of the present embodiment.

<Modification of Embodiment 1>
The semiconductor device 10A described above has two semiconductor chips 12 (12A, 12B) on which a flash memory is formed mounted on the upper surface of the wiring board 11. A different third semiconductor chip may be mounted on the upper surface of the wiring board 11 together with the two semiconductor chips 12 (12A, 12B).

  For example, in the semiconductor device 10B shown in FIG. 29, two semiconductor chips 12 (12A, 12B) on which flash memories are formed are mounted stepwise on the first chip mounting area on the upper surface of the wiring board 11, and the first chip mounting is performed. This is a SIP (System In Package) type semiconductor device in which a logic chip 50 for controlling each of the two semiconductor chips 12 (12A, 12B) is mounted in a second chip mounting area adjacent to the area.

  The logic chip 50 is made of a single crystal silicon substrate having a substantially square planar shape. The logic chip 50 is mounted (face-up mounting) on the upper surface of the wiring substrate 11 via an adhesive (not shown) so that the back surface thereof faces the upper surface of the wiring substrate 11. On the main surface of the logic chip 50, a control circuit for controlling the flash memory formed in the semiconductor chips 12A and 12B is formed.

  In addition, a plurality of bonding pads (electrode pads) 51 are formed along the four sides of the logic chip 50 at the periphery of the main surface of the logic chip 50. Although illustration is omitted, on each surface (wire connection surface) of the plurality of bonding pads 51, for example, a metal layer in which a gold (Au) film is laminated on a nickel (Ni) film is provided. Further, from the viewpoint of reducing the manufacturing cost of the semiconductor device, the metal layer on the surface of the bonding pad 51 may be made of a metal material in which a palladium (Pd) film is laminated on a nickel (Ni) film.

  On the upper surface of the wiring substrate 11, a plurality of bonding leads (electrode pads, bonding lead group) 52 are formed in the vicinity of each of the four sides of the logic chip 50. Although not shown, a metal layer in which a gold (Au) film is stacked on a nickel (Ni) film, for example, is provided on each surface of the plurality of bonding leads 52.

  The plurality of bonding pads 51 formed on the main surface of the logic chip 50 and the plurality of bonding leads 52 formed on the upper surface of the wiring substrate 11 are electrically connected to each other via a wire 53 made of, for example, gold (Au). Has been. The plurality of bonding leads (bonding lead group) 52 electrically connected to the logic chip 50 are connected to the plurality of bonding leads (bonding lead group) 16 electrically connected to the semiconductor chip 12 and the wiring substrate 11. They are connected to each other through a plurality of formed wirings (not shown).

  The manufacturing method of the semiconductor device 10B includes a step of mounting the logic chip 50 on the upper surface of the wiring substrate 11, and a step of electrically connecting the bonding pads 51 of the logic chip 50 and the bonding leads 52 of the wiring substrate 11 with the wires 53. Except for the added points, the method is basically the same as the method for manufacturing the semiconductor device 10A described above, and a description thereof will be omitted.

(Embodiment 2)
In the first embodiment, the semiconductor device 10A on which two semiconductor chips 12 (12A, 12B) of the same type are mounted on the upper surface of the wiring board 11 has been described. In the second embodiment, four semiconductor chips 12 of the same type are mounted. A semiconductor device in which the semiconductor chip 12 is mounted on the upper surface of the wiring board 11 will be described.

  Here, when the four semiconductor chips 12 are continuously stacked on the upper surface of the wiring board 11 in a staircase pattern, the wires connected to the second and third semiconductor chips 12 have different wires above and below them. Will exist. Therefore, the clearance between the wire 26 connected to the upper semiconductor chip 12 and the wire 26 connected to the lower semiconductor chip 12 is narrowed, and a short circuit easily occurs between the wires 26 in the vertical direction.

  Therefore, in such a case, as shown in FIG. 30, two semiconductor chips 12 (12A, 12B) of the same type are stacked stepwise on the first chip mounting region on the upper surface of the wiring board 11, In the second chip mounting area adjacent to the first chip mounting area, two semiconductor chips 12 (12C, 12D) of the same type as the semiconductor chip 12 (12A, 12B) are stacked stepwise.

  Even when four semiconductor chips 12 having flash memories formed on the upper surface of the wiring substrate 11 are mounted by manufacturing a semiconductor device according to the steps described in the first embodiment, The same effect as in the first mode can be obtained.

  In the second embodiment, the two semiconductor chips 12 (12A, 12B) are electrically connected to the bonding lead group provided in the first chip mounting area, and the other two semiconductor chips 12 (12C) are connected. , 12D) is electrically connected to a bonding lead group provided in the second chip mounting area.

<Modification of Embodiment 2>
In the second embodiment described above, the four semiconductor chips 12 having the flash memory formed on the upper surface of the wiring substrate 11 are mounted. However, as shown in FIG. 31, for example, the third chip is mounted on the upper surface of the wiring substrate 11. A logic chip 50 on which a control circuit for controlling a flash memory formed on the four semiconductor chips 12 (12A, 12B, 12C, 12D) is formed is mounted on the third chip mounting area. Also good.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments described so far, and various modifications can be made without departing from the scope of the invention. Needless to say.

(Modification 1)
For example, in the first and second embodiments, the two wires 26 drawn from the same type of bonding pads 24 (two electrode pads of the same type) of the two semiconductor chips 12 stacked in two stages are used. The configuration for connecting to one (common) bonding lead (bonding lead group) 16 of the wiring board 11 has been described.

  On the other hand, as shown in FIGS. 32 and 33, for example, a plurality of bonding leads (first bonding leads) 16 connected to the bonding pads 24 of the lower semiconductor chip 12A and the bonding pads 24 of the upper semiconductor chip 12B are connected. A plurality of bonding leads (second bonding leads) 16 may be formed independently. That is, you may use the wiring board 11 in which the bonding lead group which has the some 1st bonding lead 16 and the some 2nd bonding lead 16 was formed.

  However, when such a configuration is adopted, the occupied area of the bonding leads 16 on the upper surface (chip mounting surface) of the wiring substrate 11 and the wiring density inside the wiring substrate 11 increase, so that the size of the wiring substrate 11 increases. To do. Therefore, when considering downsizing of the semiconductor device, it is preferable to adopt the configuration of the first and second embodiments described above.

(Modification 2)
In the first and second embodiments, the case where the bonding pad 24 of the memory chip (semiconductor chip 12) is made of copper (Cu) has been described. However, the bonding pad is made of a material mainly composed of aluminum (Al). Even when it is configured, it is preferable to form a metal layer for preventing oxidation on the surface.

  However, even in this case, if palladium (Pd), which hardly causes an alloying reaction with gold (Au), is used as the metal layer for preventing oxidation, the bonding strength of the wire is reduced on the surface of the bonding pad. Therefore, even when using a semiconductor chip in which a metal layer made of palladium (Pd) is formed on the surface of a bonding pad containing aluminum (Al) as a main component, as in the first and second embodiments, in the molding process, It is preferable to supply the sealing resin from the side opposite to the side where the bonding pad is formed (arranged).

(Modification 3)
In the first and second embodiments, a ball (spherical) solder material (solder ball) is formed on the bump land (electrode pad) on the lower surface (mounting surface) of the wiring board as the external terminal of the semiconductor device. Although a so-called BGA (Ball Grid Array) type semiconductor device has been described, it is a so-called LGA (Land Grid Array) type semiconductor device in which the surface of a bump land is covered with a small amount of solder material instead of a solder ball. May be.

(Modification 4)
In the first and second embodiments, the memory chip having a so-called single-sided pad structure in which a plurality of bonding pads are formed only on one side of the main surface has been described. However, the memory chip having the one-sided pad structure described here excludes a memory chip in which another bonding pad is formed on a side (second side) other than the side (first side) on which a plurality of bonding pads are formed. Not what you want.

  That is, even in such a memory chip, the bonding pad on the second side is connected to the bonding pad on the first side via the wiring on the chip surface, and the wire is connected to the bonding pad on the first side. In this case, it is included in the memory chip having a one-sided pad structure. In other words, even a memory chip in which bonding pads are formed on a plurality of sides, a memory chip in which a bonding pad to which wires are connected is formed on only one side is referred to as a memory chip having a single-sided pad structure. included.

  Further, the memory chip mounted on the upper surface of the wiring board is not limited to the chip on which the flash memory is formed, and any DRAM (Dynamic Random Access Memory) or SRAM can be used as long as it has the one-side pad structure described above. It may be a memory chip in which (Static Random Access Memory) or the like is formed.

  In addition, a part of the contents described in the embodiment will be described below.

  (1) A method of manufacturing a semiconductor device including the following steps: (a) preparing a wiring board having an upper surface, a plurality of bonding leads formed on the upper surface, and a lower surface opposite to the upper surface; ) A first surface, a plurality of first bonding pads formed along a first side of the first surface, a metal layer formed on each surface of the plurality of first bonding pads, and the first surface Mounting a first semiconductor chip having a first back surface opposite to the top surface of the wiring board such that the first back surface of the first semiconductor chip faces the top surface of the wiring board; (C) a second surface, a plurality of second bonding pads formed along a first side of the second surface, a metal layer formed on each surface of the plurality of second bonding pads, and the first 2 A second back surface opposite to the first surface, the second semiconductor chip of the same type as the first semiconductor chip, and the second back surface of the second semiconductor chip being connected to the first surface of the first semiconductor chip. The first surface of the first semiconductor chip is opposed to and in the same orientation as the first semiconductor chip, and the plurality of first bonding pads of the first semiconductor chip are exposed from the second semiconductor chip. (D) electrically connecting the plurality of first bonding pads of the first semiconductor chip and the plurality of bonding leads of the wiring board via a plurality of first wires; Electrically connecting the plurality of second bonding pads of the second semiconductor chip and the plurality of bonding leads of the wiring board via a plurality of second wires.

  (2) Each of the metal layers of the first and second semiconductor chips is made of palladium, and each of the first and second wires is made of gold.

10A, 10B Semiconductor device 11 Wiring substrate 12 Semiconductor chip 12A Semiconductor chip (first semiconductor chip)
12B Semiconductor chip (second semiconductor chip)
14 Solder balls (solder material)
15 Core layer 16 Bonding lead (electrode pad)
16L wiring 17L wiring 18L wiring 19 Bump land (electrode pad)
19L wiring 20 through-hole wiring 21 solder resist (insulating film)
22, 23 Metal layer 24 Bonding pad (electrode pad)
25 Metal layer 26 Wire 27 Adhesive (die bond material)
28 resin sealing body 28A sealing resin 30 silicon substrate 31 p-type well 32 element isolation trench 33 first layer wiring 34 second layer wiring 35 third layer wirings 36, 37, 38 interlayer insulating film 39 surface protection film (passivation film) )
40 Molding die 41 Upper die 42 Lower die 43 Gate 44 Air vent 45 Cavity 46 Dicing blade 50 Logic chip 51 Bonding pad (electrode pad)
52 Bonding lead (electrode pad)
53 Wire 100 Large wiring board

Claims (10)

A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring board having an upper surface, a plurality of bonding leads formed on the upper surface, and a lower surface opposite to the upper surface;
(B) a first surface, a plurality of first bonding pads formed along a first side of the first surface, a first metal layer formed on each surface of the plurality of first bonding pads, and the A first semiconductor chip having a first back surface opposite to the first surface is mounted on the top surface of the wiring board such that the first back surface of the first semiconductor chip faces the top surface of the wiring board. The step of:
(C) a second surface, a plurality of second bonding pads formed along a first side of the second surface, a second metal layer formed on each surface of the plurality of second bonding pads, and the A second semiconductor chip having a second back surface opposite to the second surface and having the same type as the first semiconductor chip is formed, and the second back surface of the second semiconductor chip is the first semiconductor chip. The first semiconductor chip is opposed to the first surface and in the same orientation as the first semiconductor chip, and the plurality of first bonding pads of the first semiconductor chip are exposed from the second semiconductor chip. Mounting on the first surface;
(D) electrically connecting the plurality of first bonding pads of the first semiconductor chip and the plurality of bonding leads of the wiring substrate via a plurality of first wires;
(E) electrically connecting the plurality of second bonding pads of the second semiconductor chip and the plurality of bonding leads of the wiring substrate via a plurality of second wires;
(F) sealing the upper surface of the wiring board, the first and second semiconductor chips, and the plurality of first and second wires with a resin;
here,
In the step (f), the first side of the first surface from the second side of the first surface facing the first side of the first surface on which the plurality of first bonding pads are formed. Toward the substrate. Each of the first and second metal layers is made of palladium,
The method of manufacturing a semiconductor device according to claim 1, wherein each of the first and second wires is made of gold. Each of the first and second semiconductor chips is a memory chip;
The method for manufacturing a semiconductor device according to claim 2, wherein a logic chip for controlling each of the first and second semiconductor chips is mounted next to the first semiconductor chip on the upper surface of the wiring board. The plurality of bonding leads of the wiring board have a plurality of first bonding leads and a plurality of second bonding leads,
In the step (d), the plurality of first bonding pads of the first semiconductor chip and the plurality of first bonding leads of the wiring substrate are electrically connected via the plurality of first wires,
The step (e) includes electrically connecting the plurality of second bonding pads of the second semiconductor chip and the plurality of second bonding leads of the wiring board via the plurality of second wires. 3. A method for manufacturing a semiconductor device according to 2. A plurality of bump lands electrically connected to the plurality of bonding leads are formed on the lower surface of the wiring board prepared in the step (a),
The method for manufacturing a semiconductor device according to claim 2, wherein after the step (f), a solder material constituting an external terminal of the semiconductor device is connected to each surface of the plurality of bump lands. A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring board having an upper surface, a first bonding lead group formed on the upper surface, a second bonding lead group formed on the upper surface, and a lower surface opposite to the upper surface;
(B) a first surface, a plurality of first bonding pads formed along a first side of the first surface, a first metal layer formed on each surface of the plurality of first bonding pads, and the A first semiconductor chip having a first back surface opposite to the first surface is mounted on the top surface of the wiring board such that the first back surface of the first semiconductor chip faces the top surface of the wiring board. The step of:
(C) a second surface, a plurality of second bonding pads formed along a first side of the second surface, a second metal layer formed on each surface of the plurality of second bonding pads, and the A second semiconductor chip having a second back surface opposite to the second surface and having the same type as the first semiconductor chip is formed, and the second back surface of the second semiconductor chip is the first semiconductor chip. The first semiconductor chip is opposed to the first surface and in the same orientation as the first semiconductor chip, and the plurality of first bonding pads of the first semiconductor chip are exposed from the second semiconductor chip. Mounting on the first surface;
(D) a third surface, a plurality of third bonding pads formed along the first side of the third surface, a third metal layer formed on each surface of the plurality of third bonding pads, and the A third semiconductor chip having a third back surface opposite to the third surface and having the same type as the first semiconductor chip is disposed, and the third back surface of the third semiconductor chip is opposed to the upper surface of the wiring substrate. And mounting on the upper surface of the wiring board and next to the first semiconductor chip in the same direction as the first semiconductor chip;
(E) a fourth surface, a plurality of fourth bonding pads formed along the first side of the fourth surface, a fourth metal layer formed on each surface of the plurality of second bonding pads, and the A fourth semiconductor chip having a fourth back surface opposite to the fourth surface and having the same type as the first semiconductor chip is formed, and the fourth back surface of the fourth semiconductor chip is the third semiconductor chip. The third semiconductor chip is opposed to the third surface, is in the same orientation as the third semiconductor chip, and is exposed from the fourth semiconductor chip so that the plurality of third bonding pads of the third semiconductor chip are exposed. Mounting on the third surface;
(F) electrically connecting the plurality of first bonding pads of the first semiconductor chip and the first bonding lead group of the wiring substrate via a plurality of first wires;
(G) electrically connecting the plurality of second bonding pads of the second semiconductor chip and the first bonding lead group of the wiring board via a plurality of second wires;
(H) electrically connecting the plurality of third bonding pads of the third semiconductor chip and the second bonding lead group of the wiring board via a plurality of third wires;
(I) electrically connecting the plurality of fourth bonding pads of the fourth semiconductor chip and the second bonding lead group of the wiring board via a plurality of fourth wires;
(J) sealing the upper surface of the wiring board, the first, second, third and fourth semiconductor chips and the plurality of first, second, third and fourth wires with a resin. ;
here,
In the step (j), the first side of the first surface from the second side of the first surface facing the first side of the first surface on which the plurality of first bonding pads are formed. Toward the substrate. The first, second, third and fourth metal layers are each composed of palladium;
The method of manufacturing a semiconductor device according to claim 6, wherein each of the first, second, third, and fourth wires is made of gold. Each of the first, second, third and fourth semiconductor chips is a memory chip;
The logic chip for controlling each of the first, second, third, and fourth semiconductor chips is mounted next to each of the first and third semiconductor chips on the upper surface of the wiring board. 8. A method for producing a semiconductor device according to 7. The first bonding lead group of the wiring board has a plurality of first bonding leads and a plurality of second bonding leads,
The second bonding lead group of the wiring board has a plurality of third bonding leads and a plurality of fourth bonding leads.
In the step (f), the plurality of first bonding pads of the first semiconductor chip and the plurality of first bonding leads of the wiring substrate are electrically connected via the plurality of first wires,
In the step (g), the plurality of second bonding pads of the second semiconductor chip and the plurality of second bonding leads of the wiring substrate are electrically connected via the plurality of second wires,
In the step (h), the plurality of third bonding pads of the third semiconductor chip and the plurality of third bonding leads of the wiring substrate are electrically connected via the plurality of third wires,
The step (i) includes electrically connecting the plurality of fourth bonding pads of the fourth semiconductor chip and the plurality of fourth bonding leads of the wiring board via the plurality of fourth wires. 8. A method for producing a semiconductor device according to 7. A plurality of bump lands electrically connected to the plurality of bonding leads are formed on the lower surface of the wiring board prepared in the step (a),
The method for manufacturing a semiconductor device according to claim 7, wherein after the step (j), a solder material constituting an external terminal of the semiconductor device is connected to the surface of each of the plurality of bump lands.

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