JP2014045064A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a process of removing first and second insulation films formed on lateral faces of a pillar.SOLUTION: A semiconductor device manufacturing method comprises: forming a pillar by forming a plurality of trenches on a semiconductor substrate; forming a first insulation film on lateral faces of the pillar and on bottom faces of the trenches; forming a second insulation film on the first insulation film formed on the lateral faces of the pillar; introducing an impurity into the bottom faces of the trenches by an ion implantation method; and forming a third insulation film on the first insulation film on the bottom faces of the trenches by an HDP (High Density Plasma) method and removing the second insulation film and the first insulation film on the lateral faces of the pillar.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a vertical transistor.

  In a related method of manufacturing a semiconductor device, a pillar surrounded by a groove is formed on a semiconductor substrate, and the side surface of the pillar is covered with an oxide film and a nitride film. Then, a thermal oxide film is formed at the bottom of the trench, and a bottom diffusion layer serving as one of the source / drain regions is formed at the bottom of the trench. Thereafter, the oxide film and nitride film on the pillar side surface are removed, and a gate oxide film is formed again on the pillar side surface.

JP 2011-23483 A

  In the related semiconductor device manufacturing method, when the bottom diffusion layer is formed, an oxide film and a nitride film are formed to cover the side surface of the pillar so that ions do not enter the inside from the side surface of the pillar. These oxide films and nitride films need to be removed after the bottom diffusion layer is formed. Therefore, the related semiconductor device manufacturing method has a problem that the number of manufacturing steps is large. In addition, the oxide film and nitride film covering the side surfaces of the pillar do not completely block the entry of ions into the pillar, so that the ions that have entered the pillar may affect the characteristics of the transistor. There is also.

  In a method of manufacturing a semiconductor device according to an embodiment of the present invention, a pillar is formed by forming a plurality of trenches in a semiconductor substrate, and a first insulating film is formed on a side surface of the pillar and on a bottom surface of the trench. And forming a second insulating film on the first insulating film formed on the side surface of the pillar, and forming the second insulating film on the bottom surface of the trench by HDP (High Density Plasma) method. And a third insulating film is formed, and the second insulating film and the first insulating film on the side surface of the pillar are removed.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a pillar is formed by forming a plurality of trenches in a semiconductor substrate, and a bottom diffusion layer serving as a bit line is formed at the bottom of the trench. Then, an HDP film is formed by repeating film formation and etching, a gate oxide film is formed on the side surface of the pillar, a gate conductive film is formed on the gate oxide film, and an SD diffusion layer is formed on the pillar. And a capacitor connected to the SD diffusion layer is formed.

  According to the present invention, by using the HDP method, the third insulating film can be formed and the second insulating film and the first insulating film on the side surface of the pillar can be removed. This eliminates the need for an independent process for removing the second insulating film and the first insulating film, thereby simplifying the manufacturing process of the semiconductor device. In addition, since the impurity diffusion layer formed on the side surface of the pillar can be removed, a semiconductor device with stable characteristics can be manufactured.

It is a figure which shows arrangement | positioning of the horizontal direction of the principal part of the semiconductor device which concerns on the 1st Embodiment of this invention. It is A-A 'line sectional drawing of FIG. 1A. FIG. 1B is a sectional view taken along line B-B ′ of FIG. 1A. It is a figure for demonstrating the characteristic process in the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the characteristic process in the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the characteristic process in the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the problem in the manufacturing method of a related semiconductor device. It is a figure for demonstrating the problem in the manufacturing method of a related semiconductor device. It is a figure for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. It is a figure for demonstrating the process following the process shown in FIG. FIG. 24 is a diagram for explaining a process following the process depicted in FIG. 23. It is a figure for demonstrating the process following the process shown in FIG. FIG. 26 is a diagram for describing a process following the process illustrated in FIG. 25. FIG. 27 is a diagram for describing a process following the process illustrated in FIG. 26. It is a figure for demonstrating the process following the process shown in FIG. FIG. 29 is a diagram for describing a process following the process illustrated in FIG. 28. FIG. 30 is a diagram for explaining a process following the process depicted in FIG. 29. FIG. 31 is a diagram for explaining a process following the process depicted in FIG. 30. It is a cross-sectional schematic diagram of the HDP-CVD apparatus used with the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The present invention is applied to a semiconductor device including a vertical transistor (pillar transistor). The vertical transistor is used, for example, as a cell transistor of a semiconductor memory device, particularly a DRAM (Dynamic Random Access Memory).

  FIG. 1A is a diagram showing a horizontal arrangement of main parts of the semiconductor device according to the first embodiment of the present invention. Although the illustrated semiconductor device is a DRAM, for the sake of easy understanding, a portion above the capacitor contact 6, for example, a (cell) capacitor or the like is not shown. FIG. 1A shows a part of the memory cell region, and the peripheral circuit region is omitted.

  As illustrated, a plurality of element isolation regions 2 extending in the Y direction are repeatedly arranged in the X direction. Each element isolation region 2 is formed by embedding an element isolation trench formed in a semiconductor substrate with an insulating film. By forming the plurality of element isolation regions 2, a plurality of active regions 1a are defined in the semiconductor substrate. That is, the plurality of element isolation regions 2 and the plurality of active regions 1a are alternately and repeatedly arranged in the X direction.

  A plurality of gate trenches 3c extending in the X direction are repeatedly arranged in the Y direction. The active region 1a is divided by the gate trench 3c to form a pillar 3d.

  A bottom diffusion layer bit line 3g is formed below the active region 1a (the back side in the figure). The bottom diffusion layer bit line 3g is formed by introducing impurities such as As and P at a high concentration through the bottom of the gate trench 3c and diffusing them into the lower part of the adjacent pillar 3d. In other words, the impurity diffusion layers formed at the bottoms of the gate trenches located on both sides of each pillar 3d are connected to each other under the pillars 3d to form the bottom diffusion layer bit line 3g. The element isolation region 2 reaches deeper than the bottom diffusion layer bit line 3g, and the adjacent bottom diffusion layer bit lines 3g are separated from each other.

  Embedded word lines 3k1 and 3k2 are formed on the side surfaces of the gate trench 3c. The buried word lines 3k1 and 3k2 are in contact with the side surface in the Y direction of the pillar 3d through a gate oxide film (3i in FIG. 1B). A side surface of the pillar 3d in the Y direction becomes a channel of the pillar transistor (3 in FIG. 1B).

  An upper diffusion layer 3p connected to the upper part of the pillar 3d is formed above the pillar 3d. A capacitor contact 6 is formed immediately above the upper diffusion layer 3p so as to be connected to the upper diffusion layer 3p. A capacitor is connected to the capacitance contact 6 as will be described later.

  Next, with reference to FIG. 1B and FIG. 1C, the semiconductor device according to the present embodiment will be further described.

  1B is a cross-sectional view taken along line A-A ′ in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line B-B ′ in FIG. 1A. In these figures, unlike FIG. 1A, a capacitor 8 and the like are shown.

  As illustrated, a bottom protective oxide film 3h is formed at the bottom of the gate trench 3c. A space between the buried word lines 3k1 and 3k2 formed on the side surface of the gate trench 3c is filled with the first interlayer insulating film 4.

  An SD (source / drain) diffusion layer 3m is formed on the pillar 3d. The SD (source / drain) diffusion layer 3m is formed by introducing impurities such as AS and P at a medium concentration by ion implantation.

  An upper diffusion layer 3p is formed on the upper surface of the SD diffusion layer 3m. The upper diffusion layer 3p is formed by introducing, for example, AS and P at a high concentration into the silicon layer that has been selectively epitaxially grown by ion implantation. The surface of the upper diffusion layer 3p is covered with a cobalt silicide Co—Si layer 3q.

  The pillar transistor 3 is composed of layers from the bottom diffusion layer bit line 3g to the Co—Si layer 3q, with the bottom diffusion layer bit line 3g as the bottom layer and the Co—Si layer 3q as the top layer.

  A capacitor contact 6 connected to the upper diffusion layer 3p via the Co—Si layer 3q is formed immediately above the upper diffusion layer 3p. The space between the capacitor contacts 6 and the space between the upper diffusion layers 3p are filled with the second interlayer insulating film 5.

  A third interlayer insulating film 7 is formed thick on the capacitor contact 6 and the second interlayer insulating film 5. A lower electrode 8b is formed on the bottom and inside of a cylinder hole 8a formed so as to penetrate the third interlayer insulating film 7 and reach the capacitor contact 6. A capacitive insulating film 8c is formed so as to cover the surfaces of the lower electrode 8b and the third interlayer insulating film 7, and an upper electrode 8d is formed on the surface. The upper surface of the upper electrode 8d is flattened, and a protective insulating film 9 covering the whole is formed thereon.

  In the above embodiment, an example of a capacitor that uses the inside of the crown-shaped lower electrode 8b as a capacitor has been shown, but the type of the capacitor is not limited to this.

  Next, with reference to FIGS. 2A to 2C, an outline of characteristic steps in the above-described semiconductor device manufacturing method will be described.

  FIG. 2A is a detailed view around the pillar 3d showing a state before the bottom protective oxide film 3h is formed. As shown in the figure, a sacrificial oxide film 3e is formed on the bottom and side walls (side surfaces in the Y direction of the pillar 3d) of the gate trench 3c. A sidewall nitride film 3f is formed on the surface of the sacrificial oxide film 3e formed on the side surface in the Y direction of the pillar 3d. Further, on the side surface portion in the Y direction of the pillar 3d, when the bottom diffusion layer bit line 3g is formed, the pillar side surface diffusion formed by impurities penetrating the sidewall nitride film 3f and the sacrificial oxide film 3e and entering the pillar 3d. A layer 3g ′ is formed.

  In the state of FIG. 2A, a bottom protective oxide film (HDP film) 3h is formed by HDP-CVD (High Density Plasma-Chemical Vapor deposition). At that time, film forming conditions are set so that film formation and etching are periodically repeated. For example, after the film formation is performed for 10 to 25 seconds, the process of performing the etching for 5 to 20 seconds is repeated. By doing so, an oxide film (bottom protective oxide film 3h) is formed on the surface (horizontal plane) perpendicular to the film forming direction, and the film thickness increases, while the direction perpendicular to the film forming direction (vertical). Surface) is sputter-etched.

  As a result, as shown in FIG. 2B, the bottom protective oxide film 3h is formed on the bottom surface of the gate trench 3c, and the sidewall nitride film 3f is removed. At this time, the bottom protective oxide film 3h is also formed on the mask nitride film 3b. Thereafter, as shown in FIG. 2C, the bottom protective oxide film 3h formed on the bottom surface of the gate trench 3c is increased in thickness, while not only the sacrificial oxide film 3e but also the pillar side diffusion layer 3g 'is removed.

  Thus, the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side surface diffusion layer 3g 'can be removed.

  In the related semiconductor device manufacturing method, when the bottom protective oxide film 3h is formed by, for example, CVD, as shown in FIG. 3A, the pillar side surface protection is simultaneously provided on the side wall nitride film 3f on the side surface of the pillar 3d. An oxide film 3h ′ is formed. In this case, in order to expose the side surface of the pillar 3d again, the pillar side surface protective oxide film 3h ′ is removed by an oxide film wet etch, then the sidewall nitride film 3f is removed by a nitride film wet etch, The sacrificial oxide film 3e must be removed by an oxide film wet etch. In the present embodiment, these three steps can be eliminated.

  In the related semiconductor device manufacturing method, as shown in FIG. 3B, the pillar side diffusion layer 3g 'remains on the exposed side surface of the pillar 3d, which deteriorates the characteristics of the transistor. In the present embodiment, the pillar side diffusion layer 3g ′ can be removed without performing an independent removal step.

  Hereinafter, with reference to FIGS. 4 to 32, the method of manufacturing the semiconductor device according to the present embodiment will be described in detail.

  First, as shown in FIG. 4, a mat oxide film 2a and a mask nitride film 2b are formed in this order on the surface of a semiconductor substrate 1, for example, a Si substrate. Then, a resist R is applied to the entire surface of the mask nitride film 2b, and the resist R is patterned into a pattern corresponding to the element isolation region 2. That is, the resist R is patterned in a pattern in which a plurality of line-shaped openings linearly extend in the Y direction and repeat in the X direction. If the processing dimension is small, a double patterning method may be used.

  Next, as shown in FIG. 5, the mask nitride film 2b, the mat oxide film 2a, and the semiconductor substrate 1 are etched in this order by dry etching to form a shallow trench 2c. The resist R is thinned and disappears as the etching progresses.

  Next, the exposed surface of the semiconductor substrate 1, that is, the inner surface of the shallow trench 2c is oxidized by thermal diffusion to form a protective oxide film (not shown). Subsequently, as shown in FIG. 6, an element isolation insulating film 2d is formed so as to fill the inside of the shallow trench 2c, and the surface of the element isolation insulating film 2d is CMP (Chemical Mechanical Polishing) until the surface of the semiconductor substrate 1 is exposed. ) And etching. As the element isolation insulating film 2d, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof can be used.

  Thus, an element isolation region (hereinafter referred to as STI: Shallow Trench Isolation) 2 is formed. As a result, a repetitive pattern of active regions 1 a and STI 2 extending in the Y direction and repeating in the X direction is formed on the surface of the semiconductor substrate 1.

  Next, as shown in FIG. 7, a mat oxide film 3a and a mask nitride film 3b are formed in this order on the surfaces of the semiconductor substrate 1 and the STI 2. Then, a resist R is applied to the entire surface of the mask nitride film 3b, and the resist R is patterned into a pattern corresponding to the gate trench 3c. That is, the resist R is patterned in a pattern in which a plurality of line-shaped openings linearly extend in the X direction and repeat in the Y direction. If the processing dimension is small, a double patterning method may be used.

  Next, as shown in FIG. 8, the mask nitride film 3b, the mat oxide film 3a, and the active layers 1a and STI2 are etched in this order by dry etching to form a gate trench 3c. The width of the gate trench 3c is desirably about 130 nm, and the depth of the gate trench 3c is desirably about half of STI2.

  Active layers 1a and STI2 appear in stripes on the bottom and side surfaces of the gate trench 3c. In the active layer 1a, a pillar 3d surrounded by the STI 2 and the gate trench 3c is formed.

  Next, as shown in FIG. 9, the surface of the active region 1a exposed on the bottom and side surfaces of the gate trench 3c is oxidized by thermal oxidation to form a sacrificial oxide film 3e (first insulating film). Here, the thickness of the sacrificial oxide film 3e is desirably about 2.5 nm.

  Next, as shown in FIG. 10, a thin sidewall nitride film 3f is formed on the entire exposed surface including the bottom and side surfaces of the gate trench 3c. Here, the thickness of the sidewall nitride film 3f is preferably about 15 nm.

  Next, as shown in FIG. 11, a part of the sidewall nitride film 3f is removed by etch back, and the sidewall nitride film 3f (second insulating film) is left on the side surface of the gate trench 3c. The sidewall nitride film 3f left on the side wall of the gate trench 3c serves as a mask that prevents ions from entering the side wall of the pillar 3d in the next ion implantation.

  Next, as shown in FIG. 12, the bottom diffusion layer bit line 3g is formed. The bottom diffusion layer bit line 3g is formed, for example, by introducing and diffusing impurities such as As and P into the bottom of the gate trench 3c at a high concentration by ion implantation. Diffusion layers (high concentration regions) respectively formed at the bottoms of the adjacent gate trenches 3c are connected to each other at the lower part of the pillar 3d located between them. The implantation energy is adjusted so that the bottom diffusion layer bit line 3g does not extend deeper than STI2. At this time, impurities are also implanted into the side surface of the pillar 3d through the sidewall nitride film 3f and the sacrificial oxide film 3e, and the pillar side diffusion layer 3g 'is formed.

  Next, a bottom insulating oxide film 3h (third insulating film) is formed on the bottom of the gate trench 3c, and the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side surface diffusion layer 3g 'are removed. This can be realized by repeatedly performing film formation for 10 to 25 seconds and etching for 5 to 20 seconds under the conditions described later using an HDP-CVD apparatus.

  In a film forming process using an HDP-CVD apparatus, a film is easily formed on a horizontal plane as compared with a side wall. Therefore, the bottom protective oxide film 3h is formed mainly on the upper surface of the mask nitride film 3b and the bottom surface of the gate trench 3c.

  On the other hand, in the etching process using the HDP-CVD apparatus, the side walls are also sputter-etched in the same manner as the horizontal plane. The bottom protective oxide film 3h formed at the bottom of the gate trench 3c is left by making the etched film thickness smaller than the film thickness of the bottom protective oxide film 3h formed on the horizontal surface in the film forming process, The side wall of the gate trench 3c can be etched.

  By repeating the film forming process and the etching process using the HDP-CVD apparatus, the sidewall nitride film 3f and the sacrificial oxide film are increased while increasing the thickness of the bottom protective oxide film 3h formed at the bottom of the gate trench 3c. 3e and the pillar side diffusion layer 3g ′ can be sequentially sputter-etched. As a result, the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side diffusion layer 3g 'can be removed.

  FIG. 13 shows a state in which the side wall nitride film 3f on the side surface of the gate trench 3c is removed by repeating the film forming process and the etching process using the HDP-CVD apparatus several times. FIG. 14 shows a state in which the process using the HDP-CVD apparatus is finished.

  Referring to FIG. 14, since the upper surface of mask nitride film 3b and the bottom surface of gate trench 3c are horizontal surfaces, bottom protective oxide film 3h is formed on these surfaces. The bottom protective oxide film 3h is necessary to separate the lower diffusion layer 3g from the gate electrode film (3j in FIG. 16) to be formed later. The thickness of the bottom protective oxide film 3h is preferably about 40 nm.

  Further, the side surface of the gate trench 3c including the side surface of the pillar 3d is sputter-etched, and none of the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side surface diffusion layer 3g 'is present.

  Thus, in the present embodiment, the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side surface diffusion layer 3g 'can be removed by the step of forming the bottom protective oxide film 3h. That is, the pillar side insulating oxide film 3h ′, the sacrificial oxide film 3e, the sidewall nitride film 3f, and the pillar side diffusion layer 3g ′ formed on the side surface of the pillar 3d, which are required in the related semiconductor device manufacturing method, are removed. The process for doing so can be omitted.

  Next, as shown in FIG. 15, the surface of the active region 1a exposed on the side surface of the gate trench 3d (the side surface in the Y direction of the pillar 3d) is oxidized by thermal oxidation to form a gate oxide film 3i. Here, the thickness of the gate oxide film 3i is desirably about 5 nm. Further, instead of forming the oxide film, a Hi-K film may be formed as a gate insulating film.

  Next, as shown in FIG. 16, a gate conductive film 3j is formed on the entire exposed surface including the bottom and side surfaces of the gate trench 3c. Here, the gate conductive film 3j is preferably a metal film such as W using P-doped polysilicon or a TiN film as a barrier film.

  Next, as shown in FIG. 17, the gate conductive film 3j is etched back so that the gate conductive film 3j remains on the side surface of the gate trench 3c, and the bottom insulating oxide film 3h on the upper surface of the mask nitride film 3b is removed. Thereby, buried word lines 3k1 and 3k2 extending in the X direction on the side surface of the gate trench 3c and separated into two in the Y direction in each gate trench 3c are formed. Note that the etch back conditions are adjusted so that the upper ends of the buried word lines 3k1 and 3k2 are lower than the upper surface of the mask nitride film 3b.

  Next, as shown in FIG. 18, the first interlayer insulating film 4 filling the gate trench 3c is formed. The first interlayer insulating film 4 can be formed by depositing an insulating film such as a silicon oxide film over the entire surface and planarizing the upper surface by CMP using the nitride film 3b as a stop film. SOD (Spin-On Dielectric) can also be used as the first interlayer insulating film 4. In this case, after filling the gate trench 3c with SOD, the SOD is modified by heat treatment to form an SOD film.

  Next, as shown in FIG. 19, the mask nitride film 3b is removed by etching by wet nitride film etching. Then, an impurity such as P or As is thinly implanted at a medium concentration above the pillar 3d by ion implantation to form an SD diffusion layer 3m.

  Next, as shown in FIG. 20, the thickness of the mat oxide film 3a is etched back by oxide film etch-back, and the upper surface of the pillar 3d (SD diffusion layer 3m) and the upper surface of the STI 2 are exposed. At this time, the first interlayer insulating film 4 is also etched back by the same thickness.

  Next, as shown in FIG. 21, a sidewall nitride film 3n is formed on the entire exposed surface including the upper surface of the pillar 3d (SD diffusion layer 3m) and the STI 2 upper surface.

  Next, as shown in FIG. 22, the upper surface (SD diffusion layer 3m) of the pillar 3d, the upper surface of the STI 2, etc. and the sidewall nitride film 3n on the upper surface of the first interlayer insulating film 4 are removed by etch back. Sidewall nitride films 3n are left on the side surfaces of the film 4 and the upper side surfaces of the buried word lines 3k1 and 3k2.

  Next, as shown in FIG. 23, an epitaxial growth layer 3p 'is formed on the upper surface (SD diffusion layer 3m) of the pillar 3d by selective epitaxial growth. The epitaxial growth layer 3p 'is regulated by the sidewall insulating film 3n in the Y direction and has a vertical surface in contact with the sidewall insulating film 3n. On the other hand, in the X direction, it has a free growth surface, and a gap is opened between the adjacent epitaxial growth layers 3p '.

  Next, by ion implantation, an irregular material such as As or P is implanted into the entire epitaxial growth layer 3p 'at a high concentration, that is, at a concentration higher than that of the SD diffusion layer 3m, thereby forming the upper diffusion layer 3p.

  Next, as shown in FIG. 24, a Co (cobalt) film 3q 'is formed on the entire exposed surface including the surface of the upper diffusion layer 3p.

  Next, heat treatment is performed to silicide the Co film 3q '. The silicidation of the Co film 3q 'occurs on the surface of the upper diffusion layer 3p, but does not occur on other portions such as the surface of the first interlayer insulating film 4. Thereafter, the Co film 3q 'that has not reacted is removed by wet etching, whereby a CoSi layer 3q can be formed on the upper diffusion layer 3p as shown in FIG.

  Next, as shown in FIG. 26, a thick second interlayer insulating film 5 such as a silicon oxide film is formed on the entire exposed surface including the space between adjacent upper diffusion layers 3p, and the surface thereof is flattened by CMP.

  Next, as shown in FIG. 27, a capacitor contact plug 6 penetrating the second interlayer insulating film 5 is formed. In order to form the capacitor contact plug 6, first, a capacitor contact hole 6 a is opened in the second interlayer insulating film 5 immediately above the upper diffusion layer 3 p using lithography and dry etching. As a result, the surface of the CoSi layer 3q on the upper diffusion layer 3p is exposed at the bottom of the capacitor contact hole 6a. Next, a conductive film 6b such as tungsten is formed by CVD so as to fill the capacitor contact hole 6a. Then, the surface of the conductive film 6b is planarized by WCMP until the second interlayer insulating film 5 is exposed, and the capacitor contact plug 6 is formed.

  Next, as shown in FIG. 28, a thick third interlayer insulating film 7 is formed by CVD. The thickness of the third interlayer insulating film 7 determines the height of the lower electrode (8b in FIG. 30) of the capacitor (8 in FIG. 1B and FIG. 1C) to be formed next.

  Next, as shown in FIG. 29, a cylinder hole 8a is formed in the third interlayer insulating film 7 immediately above the capacitor contact by lithography and dry etching. At the bottom of the cylinder hole 8a, the upper surface of the capacitor contact 6 and the surface of the second interlayer insulating film 5 around it are exposed.

  Next, as shown in FIG. 30, an ALD (Atomic Layer Deposition) -TiN (titanium nitride) film is formed on the entire exposed surface including the bottom and side surfaces of the cylinder hole 8a. Subsequently, the ALD-TiN film formed on the third interlayer insulating film 7 is removed, leaving the ALD-TiN film on the bottom and side surfaces of the cylinder hole 8a. The ALD-TiN film left on the bottom and side surfaces of the cylinder hole 8a constitutes the lower electrode 8b.

  Next, as shown in FIG. 31, a capacitor insulating film 8c such as a Hi-K film is formed on the entire exposed surface including the inside of the lower electrode 8b by CVD. Subsequently, an upper electrode film 8d, for example, P-doped polysilicon is formed by CVD so as to fill the cylinder hole 8a and cover the entire surface of the capacitor insulating film 8c. As a result, the capacitor 8 that uses the inside of the lower electrode 8b as a capacitor is formed. Next, the protective insulating film 9 is formed so as to cover the upper surface of the upper electrode film 8d.

  In the present embodiment, the capacitor 8 that uses the inner side of the lower electrode 8b as a capacitor is used. However, the present invention is not limited to this type of capacitor, and other types of capacitors such as a crown type may be used.

  As described above, the semiconductor device described with reference to FIGS. 1A to 1C is completed.

  Next, with reference to FIG. 32, an HDP-CVD apparatus used in the above-described semiconductor device manufacturing method will be described.

  FIG. 32 is a schematic cross-sectional view showing an example of the configuration of the HDP-CVD apparatus.

  As shown in the figure, the HDP-CVD apparatus includes a chamber 323 provided with a stage 322 on which a wafer 321 is placed, a turbo molecular pump 324 that maintains the interior of the chamber 323 at a predetermined pressure, and a raw material in the chamber 323. A top nozzle 325 and a side nozzle 326 as supply pipes for supplying gas, and a top coil 327 and a side coil 328 arranged around the chamber 323 are provided.

  An RF (Radio Frequency) generator (not shown) is connected to the top coil 327 and the side coil 328, respectively. Also, another RF generator is connected to the stage 322.

  In the illustrated HDP-CVD apparatus, a wafer 321 is placed on a stage 322 in a chamber 323. The wafer 321 placed on the stage 322 is heated by a heater or the like (not shown).

  Source gas is introduced into the chamber 323 through the top nozzle 325 and the side nozzle 326. The pressure in the chamber 323 is maintained at a predetermined pressure by the turbo molecular pump 324. After the reaction, the source gas and surplus gas are discharged from the turbo molecular pump 324 to the outside of the chamber through a discharge pipe (not shown).

  When high-frequency power (source power) is supplied to the top coil 327 and the side coil 328 in a state where the source gas is introduced into the chamber 323, plasma due to inductive coupling is generated in the chamber 323. Further, independent high frequency power (bias power) for control can be applied to the stage 322. By independently controlling the source power and the bias power, the movement of ions contributing to film formation can be controlled, and the state of the film deposited on the wafer 321 can be adjusted.

  In the present embodiment, a silicon oxide film is deposited as the bottom protective oxide film 3h. Further, by supplying an etching gas in place of the source gas into the chamber 323, the sidewall nitride film 3f, the sacrificial oxide film 3e, and the pillar side surface diffusion layer 3g 'are etched.

  The conditions for forming the bottom protective oxide film 3h can be set as follows, for example.

Setting value Film formation O ₂ : 65 sccm (top nozzle 325),
SiH ₄ : 0 sccm (top nozzle 325) +25 sccm (side nozzle 326),
H ₂ : 560 sccm (top nozzle 325) +470 sccm (side nozzle 326),
Source power: 9000 W (top coil 327) +6000 W (side coil 328),
Bias power: 3000W.

Etching O2: 50 sccm (top nozzle 325),
NF ₃ : 40 sccm (top nozzle 325) +80 sccm (side nozzle 326),
H ₂ : 330 sccm (top nozzle 325) +320 sccm (side nozzle 326),
Source power: 6000 W (top coil 327) +4000 W (side coil 328),
Bias power: 2000 W.

Processing time Repetition of film formation 15 seconds + etching 10 seconds.

  The above set value is an example, and the conditions for forming the bottom protective oxide film 3h are preferably in the following range.

Film formation O ₂ : 50 to 70 sccm (top nozzle 325) +0 to 10 sccm (side nozzle 326),
SiH _4: 0~10sccm (top nozzle 325) + 15~40sccm (side nozzle 326),
H ₂ : 550 to 580 sccm (top nozzle 325) +450 to 500 sccm (side nozzle 326),
Source power: 8500-9200W (top coil 327) + 5800-6400W (side coil 328),
Bias power: 2500-3500W.

Etching O ₂ : 50-70 sccm (top nozzle 325) + 0-10 sccm (side nozzle 326),
NF _3: 30~50sccm (top nozzle 325) + 70~100sccm (side nozzle 326),
H _2: 300~350sccm (top nozzle 325) + 300~350sccm (side nozzle 326),
Source power: 5500-6200W (top coil 327) + 3800-4400W (side coil 328),
Bias power: 1700-2400W.

Processing time Repetition of film formation 10 to 25 seconds + etching 5 to 20 seconds.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made without departing from the spirit of the present invention.

  For example, in processes other than the process using the HDP-CVD apparatus, various known film formation materials and film formation methods can be selected as appropriate.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Active region 2 Element isolation region (STI)
2a mat oxide film 2b mask nitride film 2c shallow trench 2d element isolation insulating film 3 pillar transistor 3a mat oxide film 3b mask nitride film 3c gate trench 3d pillar 3e sacrificial oxide film 3f sidewall nitride film 3g bottom diffusion layer bit line 3g 'pillar Side diffusion layer 3h Bottom protective oxide film 3h 'Pillar side protective oxide film 3i Gate oxide film 3j Gate conductive film 3k1, 3k2 Embedded word line 3m SD diffusion layer 3n Side wall nitride film 3p Upper diffusion layer 3p' Epitaxial growth layer 3q CoSi layer 3q 'Co film 4 First interlayer insulating film 5 Second interlayer insulating film 6 Capacitor contact 6a Capacitor contact hole 6b Conductive film 7 Third interlayer insulating film 8 Capacitor 8a Cylinder hole 8b Lower electrode 8c Capacitor insulating film 8d Upper electrode 9 Protective insulation 321 wafer 322 stage 323 chamber 324 turbo molecular pump 325 top nozzle 326 side nozzle 327 top coil 328 side coil

Claims (16)

Forming pillars by forming a plurality of trenches in a semiconductor substrate;
Forming a first insulating film on a side surface of the pillar and on a bottom surface of the trench;
Forming a second insulating film on the first insulating film formed on the side surface of the pillar;
A third insulating film is formed on the first insulating film on the bottom surface of the trench by HDP (High Density Plasma) method, and the second insulating film and the first insulating film on the pillar side surface are formed. Remove the membrane,
A method for manufacturing a semiconductor device.   The formation of the third insulating film and the removal of the second insulating film and the first insulating film on the side surface of the pillar are alternately and repeatedly performed by switching the introduced gas. Item 14. A method for manufacturing a semiconductor device according to Item 1.   The method for manufacturing a semiconductor device according to claim 2, wherein power supply is switched simultaneously with switching of the introduced gas.   Repeating the operation of forming the third insulating film for 10 to 25 seconds and removing the second insulating film and the first insulating film formed on the side surfaces of the trench for 5 to 20 seconds. The method of manufacturing a semiconductor device according to claim 2, wherein the method is a semiconductor device.   The formation of the third insulating film and the removal of the second insulating film and the first insulating film on the side surfaces of the pillar continue even after the first insulating film is removed, thereby 5. The method of manufacturing a semiconductor device according to claim 1, wherein a part of a side surface of the pillar is removed. Prior to forming the trench, a plurality of element isolation regions extending in a first direction are formed in the semiconductor substrate at a first interval along a second direction intersecting the first direction;
Forming the pillars by forming the plurality of trenches extending in the second direction at a second interval;
6. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. The formation of the trench is as follows:
A mat insulating film and a mask insulating film are sequentially formed on the semiconductor substrate,
Patterning the mat insulating film and the mask insulating film to form a mask layer;
Etching the semiconductor substrate using the mask layer as a mask;
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the mat insulating film is a silicon oxide film, and the mask insulating film is a silicon nitride film. The formation of the second insulating film is as follows.
Forming a material film of the second insulating film on the first insulating film and on the mask layer;
The method according to claim 7, wherein the material film on the first insulating film on the bottom surface of the trench and the material film on the mask layer are removed. A method for manufacturing a semiconductor device.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the third insulating film is a silicon oxide film.   5. The semiconductor device according to claim 1, further comprising a step of introducing an impurity by ion implantation at least on a bottom surface of the trench before forming the third insulating film. Production method.   The formation of the third insulating film and the removal of the second insulating film and the first insulating film on the side surfaces of the pillar continue even after the first insulating film is removed, thereby 14. The method of manufacturing a semiconductor device according to claim 13, wherein a portion including a region into which the impurity is implanted is removed from a side surface portion of the pillar.   15. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed on the side surface of the pillar by etch back after being formed on the first insulating film. Forming pillars by forming a plurality of trenches in a semiconductor substrate;
Forming a bottom diffusion layer to be a bit line at the bottom of the trench;
The HDP film is formed by repeating film formation and etching,
Forming a gate oxide film on the side surface of the pillar;
Forming a gate conductive film on the gate oxide film;
Forming an SD diffusion layer on top of the pillar;
Forming a capacitor connected to the SD diffusion layer;
A method for manufacturing a semiconductor device.

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