JP2014036104A - Pattern formation method and solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove a residual product including a fluorine (F) component generated by etching without a damage.SOLUTION: There is provided a pattern formation method for forming a pattern in a silicon layer of a processed substrate in which a semiconductor device is formed on a surface side thereof and the surface side is supported by a support substrate includes the steps of: etching the processed substrate by plasma via the mask formed in a prescribed pattern on a rear surface side of the silicon layer of the processed substrate; and cleaning the processed substrate by plasma using a cleaning gas which is a mixture of a CF-based gas and an inert gas after the etching step.

Description

  The present invention relates to a pattern forming method and a solid-state imaging device.

  A CMOS image sensor (CMOS solid-state imaging device) is configured by forming one unit (unit pixel) of a pixel by a photodiode serving as a light receiving unit and a plurality of image transistors, and arranging a large number of unit pixels two-dimensionally ( For example, see Patent Documents 1 and 2). In a CMOS image sensor, it is important to suppress color mixture due to leakage of photoelectrically converted charges to adjacent pixels. In view of this, a method has been proposed in which an element isolation region for physically separating unit pixels is formed in a silicon layer of a substrate to suppress charge leakage to adjacent pixels.

JP 2007-329336 A JP2012-338981A

  However, when the element isolation region is formed by etching, interface states are generated due to residual products at the etching interface, which may cause white spots. In addition, electrical noise may occur in the device due to the fluorine (F) component of the residual product deposited on the etching interface. Therefore, after the etching process, it is necessary to remove residual components deposited on the etching interface, particularly fluorine-based residual components.

  Here, in order to remove the fluorine-based residual component, a cleaning method using wet etching can be considered. However, when wet etching is performed after the etching process, the adhesive that bonds the substrate and the support substrate may melt in the structure in which the substrate on which the unit pixel is formed and the support substrate are bonded.

  A cleaning method is also conceivable in which a fluorine-based residual component deposited on the etching interface by heat treatment is vaporized. However, in the bonded structure, there is a concern that the unit pixel built in the substrate by heat treatment may be damaged.

  In view of the above problems, the present invention provides a pattern forming method and a solid-state imaging device capable of removing a residual product containing a fluorine (F) component generated by etching without causing damage.

In order to solve the above problems, according to one aspect of the present invention,
A pattern forming method in which a semiconductor device is formed on a front surface side, and a pattern is formed on a silicon layer of a substrate to be processed supported on the front surface side by a support substrate,
An etching step of etching the substrate to be processed by plasma through a mask formed in a predetermined pattern on the back side of the silicon layer of the substrate to be processed;
After the etching step, a cleaning step of cleaning the substrate to be processed with plasma using a cleaning gas in which a CF-based gas and an inert gas are mixed;
A pattern forming method is provided.

In order to solve the above problems, according to another aspect of the present invention,
A solid-state imaging device manufactured by the pattern forming method is provided.

  According to the present invention, it is possible to remove a residual product containing a fluorine (F) component generated by etching without causing damage.

1 is an overall configuration diagram of a plasma etching processing apparatus according to an embodiment. The cross-sectional view which showed the structure of the dipole ring magnet of FIG. The figure which showed the element isolation structure of the solid-state imaging device which concerns on one Embodiment. Sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on one Embodiment. Sectional drawing which showed the manufacturing process of the solid-state imaging device (continuation of FIG. 4) which concerns on one Embodiment. The figure which showed the reaction model of the cleaning process which concerns on one Embodiment. The figure which showed the gas kind and high frequency dependence in the cleaning process which concerns on one Embodiment. The figure which showed CD value before and behind the cleaning process of FIG. The graph which showed the high frequency dependence of CD value (difference) before and behind the cleaning process of FIG. 6 is a graph showing the cleaning time and the number of secondary ions in the depth direction of the substrate to be processed according to one embodiment. The figure which showed the gas type dependence in the cleaning process which concerns on one Embodiment. The figure which showed CD value before and behind the cleaning process of FIG. The graph which showed the gas type dependence of CD value (difference) before and behind the cleaning process of FIG.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

[Overall configuration of plasma etching system]
First, a configuration of a plasma etching apparatus that executes a pattern forming method according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a longitudinal sectional view showing the overall configuration of a plasma etching apparatus according to an embodiment. FIG. 2 is a cross-sectional view of the dipole ring magnet shown in FIG.

  In the plasma etching apparatus according to the present embodiment, first, through a mask formed in a predetermined pattern on the back side of a silicon layer of a substrate to be processed (for example, a silicon wafer (hereinafter simply referred to as “wafer”)), A step of etching the wafer with plasma is executed. After the etching process, a process of cleaning the wafer with plasma is performed using a cleaning gas in which a CF-based gas and an inert gas are mixed.

  The plasma etching apparatus 1 according to the present embodiment is configured as a magnetron reactive ion etching (RIE) type plasma etching apparatus, and includes a chamber C made of a metal such as aluminum or stainless steel. Yes.

  In the chamber C, for example, a susceptor 2 for mounting a wafer W is provided. The susceptor 2 is made of, for example, aluminum, and is supported by a support portion 4 made of a conductor via an insulating member 3. A focus ring 5 made of, for example, quartz is disposed around the upper surface of the susceptor 2. On the upper surface of the susceptor 2, an electrostatic chuck 6 for holding the wafer W by electrostatic attraction is provided. The susceptor 2 and the support part 4 can be moved up and down by a lifting mechanism including a ball screw 7, and a lifting drive part (not shown) provided below the support part 4 is covered with a bellows 8 made of stainless steel. Yes. A bellows cover 9 is provided outside the bellows 8. The lower surface of the focus ring 5 is connected to the baffle plate 10, and the focus ring 5 is electrically connected to the chamber C through the baffle plate 10, the support portion 4 and the bellows 8. Chamber C is grounded.

  The chamber C has an upper part 1a and a lower part 1b having a diameter larger than that of the upper part 1a. An exhaust port 11 is formed in the side wall of the lower portion 1b of the chamber C, and an exhaust device 12 is connected to the exhaust port 11 through an exhaust pipe. By operating the vacuum pump of the exhaust device 12, the processing space in the chamber C is depressurized to a predetermined degree of vacuum. A gate valve 13 that opens and closes the loading / unloading port for the wafer W is attached to the side wall of the lower portion 1 b of the chamber C.

  A first high frequency power supply 15 for plasma generation and reactive ion etching (RIE) is electrically connected to the susceptor 2 through a matching unit 14. The first high frequency power supply 15 supplies high frequency power having a frequency of, for example, 100 MHz to the lower electrode, that is, the susceptor 2 as high frequency power for plasma generation.

  A second high frequency power supply 26 is also electrically connected to the susceptor 2 via a matching unit 25. The second high frequency power supply 26 supplies high frequency power having a frequency of 400 kHz, for example, as a bias high frequency to the susceptor 2 in a superimposed manner.

  On the ceiling portion of the chamber C, a shower head 20 described later is provided as an upper electrode held at the ground potential. Accordingly, the first high frequency power from the first high frequency power supply 15 is supplied between the susceptor 2 and the shower head 20.

  The electrostatic chuck 6 is obtained by sandwiching an electrode 6a made of a conductive film between a pair of insulating sheets 6b. A DC power supply 16 is electrically connected to the electrode 6a. The wafer W is electrostatically attracted to the electrostatic chuck 6 by an electrostatic attractive force caused by a DC voltage from the DC power supply 16.

  Inside the susceptor 2, for example, a refrigerant chamber 17 extending in the circumferential direction is provided. Refrigerant at a predetermined temperature, such as cooling water, is circulated and supplied to the refrigerant chamber 17 from an external chiller unit (not shown) via pipes 17a and 17b. The wafer W on the susceptor 2 is controlled to a predetermined processing temperature by the temperature of the circulating refrigerant.

  Further, a cooling gas such as He gas from the gas introduction mechanism 18 is supplied between the upper surface of the electrostatic chuck 6 and the rear surface of the wafer W via the gas supply line 19. The gas introduction mechanism 18 can independently control the gas pressure, that is, the back pressure, at the wafer central portion and the wafer peripheral portion in order to improve the uniformity of the etching process within the wafer surface.

  The shower head 20 on the ceiling has a number of gas discharge ports 22 on the lower surface facing the upper surface of the susceptor 2 in parallel. A buffer chamber 21 is provided inside the gas discharge surface. A gas supply source 23 is connected to the gas inlet 20a of the buffer chamber 21 via a gas supply pipe 23a. A processing gas is supplied from the gas supply source 23.

  Around the upper part 1a of the chamber C, a dipole ring magnet 24 extending annularly or concentrically is disposed. As shown in the cross-sectional view of FIG. 2, the dipole ring magnet 24 has a plurality of, for example, sixteen anisotropic segment columnar magnets 31 arranged at regular intervals in the circumferential direction in a casing 32 made of a ring-shaped magnetic body. Do it. In FIG. 2, the arrow shown in each anisotropic segment columnar magnet 31 indicates the direction of magnetization, and the direction of magnetization of each anisotropic segment columnar magnet 31 is gradually changed along the circumferential direction as shown in the figure. By shifting, a uniform horizontal magnetic field B directed in one direction as a whole can be formed.

  Accordingly, in the space between the susceptor 2 and the shower head 20, an RF electric field is formed in the vertical direction by the high frequency power from the first high frequency power supply 15, and a magnetic field is formed in the horizontal direction by the dipole ring magnet 24. The Magnetron discharge using these orthogonal electromagnetic fields generates high-density plasma near the surface of the susceptor 2.

  The plasma etching apparatus having the above configuration is comprehensively controlled by the control unit 40. The control unit 40 includes a CPU 41 (Central Processing Unit), a ROM 42 (Read Only Memory), and a RAM 43 (Random Access Memory). The CPU 41 executes plasma processing according to various recipes stored in these storage areas. The recipe includes process time, process chamber temperature (upper electrode temperature, process chamber sidewall temperature, ESC temperature, etc.), pressure (gas exhaust), high-frequency power and voltage, and various process gases, which are control information of the apparatus with respect to process conditions. The flow rate, heat transfer gas flow rate, etc. are described.

  Note that the function of the control unit 40 may be realized by operating using software or may be realized by operating using hardware.

  In order to perform plasma etching in the plasma etching apparatus configured as described above, first, the gate valve 13 is opened, the wafer W is loaded into the chamber C, and placed on the susceptor 2. Next, the susceptor 2 on which the wafer W is placed is raised to the height position shown in the drawing, and the inside of the chamber C is exhausted through the exhaust port 11 by the vacuum pump of the exhaust device 12. Then, the processing gas is introduced into the chamber C from the gas supply source 23 at a predetermined flow rate, and the pressure in the chamber C is set to a set value. Further, high frequency power of a predetermined power is applied from the first high frequency power supply 15 to the susceptor 2. Further, a DC voltage is applied from the DC power source 16 to the electrode 6 a of the electrostatic chuck 6 to fix the wafer W to the susceptor 2. The processing gas introduced from the shower head 20 is ionized or dissociated by magnetron discharge to generate plasma. Then, the wafer W is etched by radicals and ions contained in the generated plasma.

  The overall configuration of the plasma etching apparatus 1 according to this embodiment has been described above. In the pattern formation method according to the present embodiment described below, the element isolation layer is formed by etching the silicon layer of the wafer W into a predetermined pattern using the plasma etching apparatus 1 according to the present embodiment described above. . Further, after the etching process, the etching surface of the element isolation layer is cleaned using a desired cleaning gas by using the plasma etching apparatus 1.

[Separation of CMOS image sensor elements]
3A and 3B show an element isolation structure formed in the silicon layer of the wafer W according to this embodiment. FIG.3 (b) is AA sectional drawing of Fig.3 (a). In the present embodiment, the wafer W having a structure in which the wafer W is turned upside down and the surface of the wafer W is bonded to the support substrate is etched.

  That is, the bonded wafer has a structure in which, for example, as shown in FIG. 4C, the wafer W is turned upside down and the surface Wa of the wafer W is bonded to the support wafer SW by the adhesive G. The wafer W is an example of a substrate to be processed on which a semiconductor device such as a transistor is formed on the surface Wa side. The support wafer SW is an example of a support substrate for reinforcing the thinned wafer W when the back surface Wb of the wafer W is ground and thinned.

  A resist is applied to the back surface Wb of the bonded wafer W thus configured, exposed, and developed, thereby forming a lattice-like resist pattern as shown in FIG. Then, using the resist as an etching mask M, an etching process of the present embodiment described later is performed, and the silicon layer of the wafer W is etched to form a lattice-shaped element isolation region 57. As a result, a unit pixel described below is separated, and a CMOS image sensor (corresponding to a solid-state imaging device) in which a large number of unit pixels are two-dimensionally arranged is manufactured. The mask M used for etching may be a polysilicon mask or a resist mask.

  In this embodiment, when a CMOS image sensor is manufactured, as shown in FIG. 5C, the wafer W has a unit pixel 50 including a photodiode PD serving as a light receiving unit and a plurality of image transistors Tr. Is formed. In this embodiment, the wafer W in which the unit pixel 50 and the wiring structure 53 are formed in this way is turned upside down, and the wafer W having a bonded structure in which the surface Wa of the wafer W is bonded to the support substrate Sw is etched. Then, the element isolation region 57 is formed.

[Production of CMOS image sensor]
Next, a method for manufacturing a CMOS image sensor will be described with reference to FIGS. In the manufacturing process of the CMOS image sensor to which the pattern forming method according to the present embodiment is applied, first, as shown in FIG. 4A, a transistor Tr is formed on the surface Wa of the wafer W made of a silicon wafer or the like. An interlayer insulating film 58 is formed on the wafer W on which the transistor Tr is formed.

  Next, as shown in FIG. 4B, the wiring structure 53 is formed on the interlayer insulating film 58. In the wiring structure 53, wiring layers 52 and insulating films 51 are alternately stacked on an interlayer insulating film 58, and via holes 54 that penetrate the insulating films 51 and electrically connect the upper and lower wiring layers 52 are formed. It is.

  Next, as shown in FIG. 4C, the wafer W is inverted, the front surface Wa side of the wafer W is bonded to the support substrate SW with the adhesive G, and the back surface Wb of the wafer W is ground and thinned.

  Thereafter, the silicon layer of the wafer W is etched by plasma through a mask patterned in a lattice form as shown in FIG. 3A, and element isolation is performed as shown in FIGS. 3B and 5A. Region 57 is formed. The depth of the element isolation region 57 is about 4.0 μm.

  Next, as shown in FIG. 5B, boron is implanted into the element isolation region 57 by implantation (ion implantation), which is opposite to the n-type charge accumulation region 60 of the photodiode PD in FIG. A conductive p-type semiconductor layer 59 is formed.

  Next, as shown in FIG. 5C, the support wafer W is peeled off from the wafer W. The CMOS image sensor manufactured by the pattern forming method according to the present embodiment has a pixel region in which unit pixels 50 are regularly arranged two-dimensionally on a thinned wafer W. The unit pixel 50 includes a photodiode PD serving as a photoelectric conversion unit and a plurality of pixel transistors Tr. The photodiode PD has an n-type charge accumulation region 60 that serves both as photoelectric conversion and charge accumulation over the entire region in the thickness direction of the wafer W. As the unit pixel, a so-called pixel sharing structure in which a plurality of photoelectric conversion units share a pixel transistor (excluding a transfer transistor) can be applied. The plurality of pixel transistors Tr can be configured by transfer transistors, reset transistors, amplification transistors, and selection transistors, four transistors, or three transistors in which the selection transistors are omitted. The transfer transistor forms a transfer gate electrode using the photodiode PD as a source.

  The back surface Wb opposite to the front surface Wa on which the wiring structure 53 of the wafer W is formed serves as a light receiving surface. A light shielding film (not shown) for blocking is formed. Further, a color filter 55 and an on-chip lens 56 are formed. Light is irradiated to the photodiode PD from the back surface Wb side of the wafer W through the on-chip lens 56.

[Residual products from the etching process]
In forming the element isolation region 57, the silicon layer of the wafer W is etched at a high speed. At this time, an etching process mainly using sulfur hexafluoride gas (SF ₆ ) is performed. As a result, a residual product R is formed on the side wall of the silicon after the etching process, as shown in FIG.

  The residual product R on the etched surface generates interface states, which may cause white spots. This white spot generation degrades the electrical characteristics of the image sensor of the CMOS image sensor. In particular, electrical noise may occur in the image sensor of the CMOS image sensor due to the fluorine (F) component contained in the residual product R. For this reason, it is important to remove the residual product R of SiO—F (SiFx) on the silicon surface by executing a cleaning process after the etching process.

  However, if wet cleaning is performed with a chemical solution in the state where the element isolation region 57 after the etching process shown in FIG. 5A is formed, the adhesive G between the wafer W and the support substrate SW is dissolved. End up. Therefore, wet etching cannot be employed in a structure in which the surface Wa side of the wafer W is bonded to the support substrate SW.

  On the other hand, a cleaning method is also conceivable in which the fluorine (F) component contained in the residual product is vaporized by heat treatment. However, in the bonded structure, the transistor Tr and the wiring structure 53 are formed on the surface Wa side of the wafer W. For this reason, if cleaning by heat treatment is performed in a state where the element isolation region 57 of FIG. 5A is formed, the transistor Tr and the wiring structure 53 formed by heat during cleaning are damaged. Therefore, cleaning by heat treatment cannot be employed in the above bonded structure.

  Therefore, in the pattern forming method according to the present embodiment, after the etching process, cleaning (treatment) by dry etching using plasma is performed in a state where the element isolation region 57 of FIG. 5A is formed. Thereby, after the etching process, a residual product containing a fluorine (F) component adhering to the silicon surface of the element isolation region 57 can be removed. As a result, it is possible to prevent deterioration of the electrical characteristics of the pixels of the CMOS image sensor. Below, the cleaning process performed using the plasma etching apparatus 1 of FIG. 1 after an etching process is demonstrated.

[Cleaning process]
Here, a method of forming a pattern on the silicon layer from the back surface Wa side of the wafer W in which a plurality of unit pixels 50 and a wiring structure 53 are formed on the front surface Wb side of the wafer W and the front surface Wb side is supported by the support substrate SW. The cleaning process of the pattern forming method according to this embodiment will be described with reference to an example in which a CMOS image sensor is manufactured. However, the device formed by the pattern forming method according to the present embodiment is not limited to a CMOS image sensor. For example, any device can be used as long as a semiconductor device is formed on the surface Wb side of the wafer W and the surface Wb side is formed by a method of forming a pattern on the silicon layer from the back surface Wa side of the wafer W supported by the support substrate. It is also applicable to the device.

In the pattern forming method according to the present embodiment, as shown in FIG. 6A, the residual product R of the silicon oxide film (SiO ₂ (F)) containing fluorine F on the side wall of the silicon after the etching process. Is formed.

In order to remove the residual product R, after the etching process, as shown in FIG. 6B, a cleaning gas in which tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) are mixed is supplied ( Cleaning process started). However, the cleaning gas is not limited to a mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) as long as it is a mixed gas of a CF-based gas and an inert gas. For example, the CF-based gas may be a gas that etches a silicon layer and has low reactivity with silicon. The inert gas may be a gas for etching the residual product isotropically. Examples include hydrogen gas (H ₂ ) and xenon gas (Xe).

The tetrafluoromethane gas (CF ₄ ) in the cleaning gas reacts with the fluorine-containing silicon oxide SiO ₂ (F) constituting the residual product R, and as shown in FIG. (SiF ₄ ), carbon dioxide gas (CO ₂ ), carbon monoxide gas (CO), oxygen gas (O ₂ ), and fluorine gas (F) are discharged. In this way, the residual product R deposited during the etching process is removed. A part of the tetrafluoromethane gas (CF ₄ ) reacts with silicon (Si) and is discharged as silicon tetrafluoride gas (SiF ₄ ) and carbon gas (C).

[Experimental result: cleaning process]
Next, the state of the element isolation region before and after the cleaning process according to the present embodiment is described with reference to FIGS. 7 to 9 by using a mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) as a cleaning gas. I will explain. FIG. 7 is a diagram showing the state of the element isolation region before and after the cleaning process when the high frequency HF for plasma generation is variable in the cleaning process according to the present embodiment. FIG. 8 is a diagram showing CD values of element isolation regions formed in the center portion and the edge portion of the wafer W before and after the cleaning process of FIG. FIG. 9 is a graph showing the difference in CD value before and after the cleaning process of FIG.

  In this embodiment, as shown in FIG. 7A, the top CD value of the element isolation region of the silicon layer formed on the wafer W is called a top CD (Critical Dimension), and the bottom of the element isolation region is The CD value is referred to as a bottom CD, and the portion having the maximum CD value in the intermediate region between the top CD and the bottom CD is referred to as a max CD.

The process conditions in the cleaning process at this time are shown below.
<Cleaning process: Process conditions>
Frequency of high frequency HF for plasma generation: 100 MHz
Power of high frequency HF for plasma generation: variable (500 to 2000 W: power per unit area 0.71 W / cm ^{2 to} 2.83 W / cm ² )
Low-frequency LF for bias: Gas type not applied and gas flow ratio: CF ₄ gas / Ar gas ≒ 2: 3
Cleaning process time: 1 minute As a result of the experiment, the cleaning shown in FIGS. 7B to 7E is performed based on the CD value of the element isolation region after the etching process shown in FIG. 7A and before the cleaning process. It can be visually confirmed that the CD value after the process increases. Further, in the cleaning process, the power of the plasma generating high frequency HF is changed to 500 W (0.71 W / cm ² ) in FIG. 7B, 1000 W (1.42 W / cm ² ) in FIG. 7C, and FIG. 1500W (2.12W / ^cm 2) of), comparing the 2000W (2.83W / cm ²⁾ in FIG. 7 (e), the I see the power of the plasma-generating high-frequency HF is large, CD values after the cleaning step is greater It can be confirmed visually.

  FIG. 8 shows the silicon etching depth, top CD, max CD, and bottom CD in the element isolation region at the center portion and the edge portion of the wafer W before and after the cleaning steps of FIGS. 7 (a) to 7 (e). It is a table. FIG. 9 is a graph showing differences in CD values before and after cleaning of the top CD, the maximum CD, and the bottom CD shown in FIG. The horizontal axis in FIG. 9 is the high frequency power for plasma generation (HF power: unit W), and the vertical axis is the CD difference (CDΔ: unit nm) before and after the cleaning process obtained when each power is applied. . Specifically, the T line indicates the difference before and after the top CD cleaning process (CDΔ), the M line indicates the difference before and after the Max CD cleaning process (CDΔ), and the B line indicates the difference before and after the bottom CD cleaning process (CDΔ). Show.

  According to this, it can be seen that the amount of the residual product R that can be scraped in one minute increases in both the center portion and the edge portion as the power of the plasma generating high frequency HF increases. This is because as the power of the plasma generating high frequency HF increases, the energy when ions are struck increases. Further, in all of CDΔ in the top CD, the maximum CD, and the bottom CD, the amount of the residual product R that can be scraped in one minute increases as the power of the high frequency HF for plasma generation increases, and the change in the amount of scraping is almost the same. is there.

  Further, when the CDΔ in the top CD, the maximum CD, and the bottom CD is seen, it can be seen that the residual product R on the bottom CD is most easily scraped.

Further, when the power of the high frequency HF for plasma generation is set to 500 W, all of CDΔ in the top CD, the maximum CD, and the bottom CD are scraped in the range of 30 to 60 nm by the cleaning for 1 minute, and the silicon layer Very little damage is expected. On the other hand, when the power of the plasma generating high frequency HF is set to 2000 W, all of CDΔ in the top CD, the maximum CD, and the bottom CD are scraped by 60 nm or more by cleaning for 1 minute, and the power of the plasma generating high frequency HF is set to 500 W. It is predicted that the silicon layer will be damaged more than the case. Therefore, the cleaning process according to the present embodiment plasmas the wafer W while applying a high frequency for plasma generation of 500 W to 1500 W (power per unit area: 0.71 W / cm ^{2 to} 2.12 W / cm ² ). It is preferable to perform cleaning. In this embodiment, the reason why a cleaning gas in which tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) are mixed is used is that tetrafluoromethane gas (CF ₄ ) has low reactivity with silicon. This is because the amount of fluoride (F) on the etching surface can be reduced while reducing the damage to silicon with less implantation into silicon.
(Secondary ion mass spectrometry)
Next, the composition of the residual product on the etched surface was confirmed using secondary ion mass spectrometry. The secondary ion mass spectrometry is a method for examining the chemical structure of the etching surface by analyzing secondary ions generated from the etching outermost surface by irradiation of ion pulses with a time-of-flight mass spectrometer. The result is shown in FIG.

The horizontal axis of FIG. 10 indicates the depth (nm) from the outermost surface of etching, and the vertical axis indicates the number of secondary ions (number / s) generated per second by ion pulse irradiation at each depth. Show. 10A shows the F component, FIG. 10B shows the Si component, and FIG. 10C shows the number of secondary ions (number / s) for the SiO ₃ component. Here, the cleaning process time is made variable. Specifically, A in each graph indicates that the cleaning is not performed (cleaning time is 0 second), B indicates that the cleaning time is 20 seconds, and C indicates that the cleaning time is 120 seconds.

  Referring to FIG. 10A and FIG. 10C, the F component concentration distribution after the etching process is present along with the SiO component at a depth of about 10 nm or 15 nm from the sidewall surface of the etched surface. Recognize.

When the cleaning process is performed for 20 seconds, the fluorine F concentration becomes about half of the depth of the etching surface (depth 0 nm) of A that is not cleaned at a depth of 5 nm from the etching surface. Generating secondary ions, at a level of approximately 10 ² number / s, it is considered to be background and equal level when almost no residual product (normal value the same level). Referring to B of FIG. 10 (a), by performing the cleaning process for 20 seconds, at a depth of 10 nm from the etching surface, the fluorine F concentration is equivalent to the background when there is no residual product (normal level). become.

  In this embodiment, the remaining product on the etching surface can be removed by about 10 nm on the side wall on one side by performing the cleaning process for 20 seconds. That is, when the cleaning process is executed for 20 seconds, the amount of etching (etching amount) on the side wall of the etching surface by cleaning corresponds to about 10 nm.

  Further, referring to C in FIG. 10A, by performing the cleaning process for 120 seconds, the F concentration reaches the same level as the normal value when there is no SiFx deposit at a depth of 2 nm to 3 nm from the etching surface. Can be reduced. When the cleaning process is executed for 120 seconds, the amount of etching (etching amount) of the side wall of the etching surface by cleaning corresponds to about 80 nm.

  However, referring to FIG. 10 (b), the silicon content in the lower layer of the residual product (wafer W) is almost the same regardless of the cleaning time if the residual product on the etching surface is removed by about 10 nm on one side wall. become. That is, when the residual product on the etching surface is removed by about 10 nm on one side wall, it is predicted that the residual product is almost removed and the silicon layer is exposed.

  Therefore, the process time of the cleaning process may be determined so that the remaining product deposited on the side wall of the pattern formed in the silicon layer by the etching process is removed by 5 nm to 10 nm on one side wall. The process time of the cleaning step may be set based on the number of fluorine F of secondary ions from the wafer W measured using secondary ion mass spectrometry after cleaning. Thereby, the residual product of the fluorine F component is from half the concentration to a concentration in which there is almost no fluorine residual product, and it is possible to prevent excessive damage to the silicon layer.

Actually, when the cleaning process according to the present embodiment was performed and the side wall was shaved from the etching outermost surface by 10 nm on one side and 20 nm on both sides of the side wall, light emission by secondary ion mass spectrometry was hardly seen. This means that secondary ions generated from the etching outermost surface by the irradiation of the ion pulse are almost eliminated. Thus, by controlling the process time of the cleaning as F residual amount scraping the etched surface to a level of about 10 ² number / s, the fluorine (F) component, possibly electrical noise to the device may occur Is almost gone.

[Gas selection]
In this embodiment, a mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) is used as the cleaning gas in the cleaning process.

Here, in the case of a single gas of argon gas (Ar), in the case of a single gas of hydrogen bromide gas (HBr), three patterns of mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar) Are selected as cleaning gases. And the cleaning process after the etching process which concerns on this embodiment is performed, and optimization of gas selection is aimed at.

FIG. 11 is a diagram showing the state of the element isolation region before and after the cleaning process when the three patterns of cleaning gas are used in the cleaning process according to the present embodiment. FIG. 11A shows the state of the element isolation region after the etching step, and FIGS. 11B to 11D show the state of the element isolation region after the cleaning step. The process conditions at this time are shown below.
<Process conditions>
Frequency of high frequency HF for plasma generation: 100 MHz
Power of high frequency HF for plasma generation: 2000 W (power per unit area 2.83 W / cm ² )
Low-frequency LF for bias: Gas type not applied and gas flow ratio: 3 patterns (Ar single gas, HBr single gas, CF ₄ / Ar mixed gas)
Cleaning process time: 5 minutes for Ar single gas
: 1 minute for single gas of HBr
In the case of a mixed gas of CF ₄ / Ar, 1 minute. FIG. 12 is a diagram showing the CD value of the element isolation region in the center portion and the edge portion of the wafer W before and after the cleaning step of FIG. FIG. 13 is a graph showing the CD value difference (CDΔ) for each cleaning gas before and after the cleaning step of FIG.

As a result of the experiment, from the CD value after the cleaning process in the case of the single gas of Ar shown in FIG. 11B and the case of the single gas of HBr shown in FIG. It can be visually confirmed that the CD value after the cleaning process in the case of the gas mixture of HCF ₄ / Ar shown in FIG.

  FIG. 13 is a graph showing the CD difference (CDΔ) before and after cleaning the top CD, the maximum CD, and the bottom CD in the center portion shown in FIG. In FIG. 13, the horizontal axis represents the above three patterns of cleaning gas, and the vertical axis represents CD Δ (nm) in the top CD, the maximum CD, and the bottom CD obtained before and after the cleaning process in the case of each cleaning gas.

  Considering FIG. 13, in the case of a single gas of argon gas (Ar), etching by sputtering is mainly performed. For this reason, etching is directional, and the etching effect on the sidewall of the etched surface is small. Further, the shoulder of the mask material is shaved (shoulder fall), and it is difficult to etch the upper part (top CD) of the element isolation region.

On the other hand, in the case of a single gas of hydrogen bromide gas (HBr) or a mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar), the top CD and max before and after the cleaning step CDΔ (nm) in CD and bottom CD is a value that is approximately approximate, and an effect of isotropically shaving the side wall is seen. In particular, in the case of a mixed gas of tetrafluoromethane gas (CF ₄ ) and argon gas (Ar), it was found that the etching rate was four times higher than that in the case of a single gas of hydrogen bromide gas (HBr).

This is probably because the reaction of the tetrafluoromethane gas (CF ₄ ) with the residual product SiO ₃ on the side wall and the silicon Si of the wafer W is larger than that of the hydrogen bromide gas (HBr). However, the reaction of tetrafluoromethane gas (CF ₄ ) with silicon Si is smaller than that of sulfur hexafluoride gas (SF ₆ ). Therefore, tetrafluoromethane gas (CF ₄ ) is used as the cleaning gas with less fluorine F hitting the wafer W and four times higher etching rate than hydrogen bromide gas (HBr) (that is, a higher cleaning effect). It turned out to be preferable.

  Further, in the present embodiment, in order to suppress the implantation of the plasma into the silicon layer by the plasma in the cleaning process, it is preferable to perform the cleaning with a high frequency HF lower than the etching process that is performed before the cleaning process and that etches the silicon layer at a high speed.

  The pattern forming method according to this embodiment has been described above. According to this pattern forming method, a cleaning gas in which a CF gas and an inert gas are mixed after an etching process for etching a silicon layer is performed on a wafer W having a structure in which the wafer W is turned upside down and bonded to a support substrate. A cleaning process for cleaning using is performed. Thereby, the residual product containing the fluorine (F) component generated by the etching process can be removed without damaging the device. Thereby, it is possible to prevent the electrical characteristics of the image sensor of the CMOS image sensor from deteriorating.

  The preferred embodiments of the pattern forming method according to the present invention have been described in detail above with reference to the accompanying drawings, but the technical scope of the pattern forming method according to the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field of the pattern forming method according to the present invention can conceive various changes or modifications within the scope of the technical idea described in the claims. These naturally belong to the technical scope of the pattern forming method according to the present invention.

  For example, the substrate to be processed of the present invention may be a disk-shaped wafer or a rectangular substrate. The size of the wafer may be 300 mm, 450 mm, or larger.

  1: plasma etching apparatus, 50: unit pixel, 51: insulating film, 52: wiring layer, 53: wiring structure, 54: via hole, 55: color filter, 56: on-chip lens, 57: element isolation region, 58: interlayer Insulating film, 59: p-type semiconductor layer, 60: n-type charge storage region, W: wafer, Wa: front surface of wafer, Wb: back surface of wafer, SW: support wafer, M: mask, G: adhesive

Claims (8)

A pattern forming method in which a semiconductor device is formed on a front surface side, and a pattern is formed on a silicon layer of a substrate to be processed supported on the front surface side by a support substrate,
An etching step of etching the substrate to be processed by plasma through a mask formed in a predetermined pattern on the back side of the silicon layer of the substrate to be processed;
After the etching step, a cleaning step of cleaning the substrate to be processed with plasma using a cleaning gas in which a CF-based gas and an inert gas are mixed;
A pattern forming method comprising:   2. The pattern forming method according to claim 1, wherein in the cleaning step, a process time of the cleaning step is determined so as to remove deposits deposited on side walls of the pattern formed on the silicon layer by the etching. . In the cleaning step, the substrate to be processed is cleaned with plasma using a cleaning gas obtained by mixing tetrafluoromethane gas (CF ₄ ) as a CF-based gas and argon gas (Ar) as an inert gas. The pattern forming method according to claim 1, wherein:   4. The process time of the cleaning step is set based on the number of secondary ion fluorine F from the substrate to be measured, which is measured after cleaning. 5. Pattern forming method.   5. The pattern formation according to claim 1, wherein the etching step is a step of separating a plurality of pixels as a semiconductor device formed on a substrate to be processed in a lattice shape. Method.   The pattern forming method according to claim 1, wherein the cleaning step supplies a high-frequency power lower than a high-frequency power for plasma generation applied in the etching step. In the kneading step, the substrate to be processed is kneaded with plasma while applying a high frequency for plasma generation of 500 W to 1500 W (power per unit area: 0.71 W / cm ^{2 to} 2.12 W / cm ² ). The pattern forming method according to claim 6.   The solid-state imaging device manufactured by the pattern formation method as described in any one of the said Claims 1-7.

Images