JP2014035617A - Image processing interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving efficiency of a bus band.SOLUTION: An image processing interface circuit 6R is connected to a module core 5 that executes predetermined processing. A read buffer 110 stores data read from an image supplying memory connected to a bus. A read management part 130 manages data transfer from the image supplying memory to the read buffer 110. A core input management part 150 supplies the data stored in the read buffer 110 to the module core 5 in the unit of an input block of a predetermined size. The read management part 130 manages reading of input image data to be processed in the module core 5 so that a plurality of input blocks are stored in the read buffer 110, and decides a read area on the image supplying memory according to a predetermined read condition so that the input image data is burst-transferred.

Description

  The present invention relates to an image processing interface circuit connected to a module core that executes predetermined image processing.

  Conventionally, in an image processing apparatus, a DMAC (Direct Memory Access Controller) is used for data transfer between an image processing module core and a DRAM (Dynamic Random Access Memory). For example, a dedicated DMAC is connected to each module core, and each DMAC is directly connected to the bus.

  A module core that performs image processing in units of so-called macroblocks is also known. For example, H.C. In H.264, a macroblock size can be selected from 16 × 16 pixels, 16 × 8 pixels, 8 × 16 pixels, 8 × 8 pixels, 8 × 4 pixels, 4 × 8 pixels, and 4 × 4 pixels. Such an image processing module core performs access to the DRAM, that is, reading and writing in units of macroblocks.

JP 2007-74412 A

  However, in a configuration in which a dedicated DMAC is provided for each module core, the presence of many DMACs increases the chip area.

  In addition, when the DRAM is accessed in units of macro blocks, the memory access efficiency is low. For example, in a macro block of 4 × 4 pixels of 8-bit YUV422, one line has only 8 bytes, so the DRAM ROW address must be switched by reading only 8 bytes. Also, if a read request is issued line by line in a macroblock, the bus bandwidth is increased due to the issue of many requests. The same applies to writing.

  An object of the present invention is to provide a technique capable of realizing the number control of DMAC, the efficiency improvement of a bus band, and the like.

  An image processing interface circuit according to a first aspect of the present invention is an image processing interface circuit connected to a module core that executes predetermined image processing, and reads data read from an image supply source memory connected to a bus. A read buffer for storing, a read manager for managing data transfer from the image supply source memory to the read buffer, and supplying stored data in the read buffer to the module core in units of input blocks of a predetermined size A core input management unit, wherein the read management unit manages reading of the input image data processed by the module core so that a plurality of input blocks are stored in the read buffer, and the input image data Read-out pairs on the image source memory so as to be burst transferred. It determines an area in accordance with a predetermined read condition.

  An image processing interface circuit according to a second aspect of the present invention is the image processing interface circuit according to the first aspect, wherein the input image data includes a plurality of pixels each corresponding to a pixel line or a pixel line group. An input image data sequence, and the input block is set for N input image data sequences (N is an integer of 2 or more) of the plurality of input image data sequences, and the read buffer It includes N read line FIFO units to which the N input image data sequences set with input blocks are respectively input, and the predetermined read condition cyclically selects the N input image data sequences. A circular selection condition indicating that the read target area is set in order from the top of the input image data string, and each input image data string. That setting of the reading target area, and a count condition to the effect that once each time it is selected.

  An image processing interface circuit according to a third aspect of the present invention is the image processing interface circuit according to the first aspect described above, wherein the input image data includes a plurality of pixels each corresponding to a pixel line or a pixel line group. Including the input image data sequence, the input block is set for one input image data sequence of the plurality of input image data sequences, and the read buffer is the 1 in which the input block is set In-column order condition that includes one read-line FIFO unit to which one input image data string is input, and that the predetermined read condition is to set the read target area in order from the head side of the input image data string including.

  An image processing interface circuit according to a fourth aspect of the present invention is the image processing interface circuit according to any one of the first to third aspects, wherein the predetermined readout condition is the readout A read alignment condition for matching the end address of the target area with the address alignment boundary of the image source memory is included.

  An image processing interface circuit according to a fifth aspect of the present invention is the image processing interface circuit according to the fourth aspect described above, wherein the predetermined read condition is that the read target area is the start of the input image data sequence. , A read size condition for setting the start address of the read target area so that the amount of data in the read target area is a multiple of the bus width of the bus is included.

  An image processing interface circuit according to a sixth aspect of the present invention is the image processing interface circuit according to the fifth aspect, wherein the predetermined read condition is that an unread portion in the input image data string is 1 When the maximum transfer amount that can be set in one burst transfer is exceeded, and the excess amount is based on the difference between the start address set under the read size condition and the start address of the input image data sequence Is larger, the first end address condition for setting the end address of the read target area according to the maximum transfer amount of the burst transfer, and the read target area when the excess amount is equal to or less than the difference And a second end address condition for setting the end address to the end address of the input image data sequence.

  An image processing interface circuit according to a seventh aspect of the present invention is the image processing interface circuit according to any one of the first to sixth aspects, wherein the predetermined read condition is the input When an unread portion in the image data sequence is equal to or less than the maximum transfer amount of the burst transfer, a third end address condition is set to set the end address of the read target region as the end address of the input image data sequence. Including.

  An image processing interface circuit according to an eighth aspect of the present invention is the image processing interface circuit according to any one of the first to seventh aspects, wherein the read buffer is configured to perform the burst transfer. The read management unit includes at least one read line FIFO unit having a capacity larger than 1 times and smaller than 2 times the maximum transfer amount, and the read management unit includes data already supplied to the module core in the read line FIFO unit. When the maximum transfer amount is exceeded, new data read from the image supply source memory is stored in the read line FIFO unit instead of the supplied data.

  An image processing interface circuit according to a ninth aspect of the present invention is an image processing interface circuit connected to a module core that executes predetermined image processing, and stores core output data output from the module core. A write buffer, a core output management unit that manages input of the core output data to the write buffer, and transfer of storage data in the write buffer to an image storage destination memory connected to a bus A write management unit, wherein the write buffer includes at least one write line FIFO (First In First Out) unit having a capacity larger than a maximum transfer amount that can be set in one burst transfer, and the write management unit For each write line FIFO unit, the data in the write line FIFO unit And write target data to be subjected to the burst transfer out, a write destination area on the image storage destination memory, to determine according to a predetermined write conditions.

  An image processing interface circuit according to a tenth aspect of the present invention is the image processing interface circuit according to the ninth aspect, wherein the predetermined write condition is the maximum transfer of the burst transfer of the write target data. At least one of a write size condition for setting the amount and a write alignment condition for aligning the write destination area with the address alignment boundary of the image storage destination memory.

  An image processing interface circuit according to an eleventh aspect of the present invention is the image processing interface circuit according to the ninth or tenth aspect, wherein the predetermined write condition is an output image output from the module core. A line end indicating that the write target data is delimited by a range up to the core output data corresponding to the end of the pixel line or pixel line group, and the write destination area is set corresponding to the delimited range Includes conditions.

  An image processing interface circuit according to a twelfth aspect of the present invention is the image processing interface circuit according to any one of the ninth to eleventh aspects, wherein the write line FIFO unit includes the burst transfer. The write management unit has a capacity that is greater than 1 and less than 2 times the maximum transfer amount, and the write management unit has transferred data for the image storage destination memory that is greater than or equal to the maximum transfer amount in the write line FIFO unit. If it does, new core output data is stored in the write line FIFO unit in place of the transferred data.

  According to the first to eighth aspects described above, a plurality of input blocks are read in advance into a buffer, and burst transfer is used for the reading. Therefore, the frequency of read requests can be suppressed as compared with a configuration in which an input block is read each time it is required by the module core. Thereby, the bus bandwidth can be used efficiently.

  According to the second to eighth aspects, the N input image data strings are read out partially and in parallel, and such reading is sequentially performed from the head side of the N input image data strings. proceed. For this reason, compared to the case where one input image data string is read from the beginning to the end and then reading of the other input image data string is started, delay in supplying data to the module core is less likely to occur. That is, in the latter case, for example, the time required to supply the input block set at the headmost side to the module core is substantially equal to the time for reading the entire N input image data strings. On the other hand, according to the partial and parallel reading described above, it is possible to finish supplying the most input block to the module core without waiting for reading of the entire N input image data strings. Further, according to the partial and parallel reading described above, the capacity of the read buffer can be reduced.

  According to the fourth to eighth aspects, it is possible to operate the image supply source memory more efficiently than when the read target region crosses the address alignment boundary of the image supply source memory. Thereby, it contributes to improvement of data transfer efficiency and power saving.

  According to the fifth to eighth aspects, data that is significant for the input image data can be left-justified in the received bit string, particularly when the read target area includes the start of the input image data string. In other words, adjustment of the start address of the read target area includes unnecessary data in the received bit string, but such unnecessary data can be intentionally arranged in front of the received bit string. Therefore, unnecessary data can be prevented from interrupting the input image data read to the buffer. This facilitates management and removal of the unnecessary data. Specifically, when data is supplied to the module core, the head data corresponding to the read start address adjustment amount in the output data of the buffer may be ignored.

  According to the sixth to eighth aspects, the maximum data amount that can be transferred can be secured by one read request. For this reason, the data transfer can be performed efficiently by suppressing the increase in the number of read requests. In addition, the frequency of read requests is reduced as data transfer becomes more efficient.

  According to the sixth to eighth aspects, when the unread portion in the input image data sequence exceeds the maximum transfer amount of burst transfer, and the excess amount is under the read size condition. If the difference is less than or equal to the difference between the start address set in step 1 and the start address of the input image data sequence, the end address of the read target area is set as the end address of the input image data sequence. As a result, the number of read requests for each input image data string is uniform. For this reason, also from this point, it is possible to suppress the frequency of read requests.

  According to the seventh to eighth aspects, an unnecessary transfer operation can be suppressed for reading of the terminal side portion of the input image data sequence. Therefore, the bus bandwidth can be used efficiently.

  According to the eighth aspect, the capacity of the read buffer can be reduced. Thereby, the chip area can be reduced, the apparatus can be reduced in size, and the power can be saved.

  According to the ninth to twelfth aspects, a plurality of output blocks are accumulated in the buffer, and they are collectively transferred to the image storage destination memory. Therefore, the frequency of write requests can be suppressed as compared with the configuration in which each time an output block is output from the module core, the output block is transferred to the image storage destination memory. Thereby, the bus bandwidth can be used efficiently.

  According to the tenth to twelfth aspects, the maximum amount of data can be written with a single write request according to the write size condition. For this reason, data transfer can be performed efficiently. In addition, the frequency of write requests is reduced as data transfer becomes more efficient. Further, the image storage destination memory can be operated more efficiently than the case where the write destination region crosses the address alignment boundary of the image storage destination memory depending on the write alignment condition. Thereby, it contributes to improvement of data transfer efficiency and power saving.

  According to the eleventh to twelfth aspects, it is possible to suppress unnecessary transfer operations for writing at the line end side portion. Therefore, the bus bandwidth can be used efficiently.

  According to the twelfth aspect, the capacity of the write buffer can be reduced. Thereby, the chip area can be reduced, the apparatus can be reduced in size, and the power can be saved.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is a block diagram which illustrates an image processing device. It is a figure explaining a pixel and a pixel line. It is a figure explaining a macroblock and a block line. It is a figure explaining a macroblock and a pixel line in a block. 3 is a block diagram illustrating a read I / F circuit. FIG. It is a figure which illustrates the buffer of a read I / F circuit. It is a figure which illustrates the writing and reading in a double buffer structure. It is a figure which illustrates reading of the data from an image supply source memory. It is a figure which illustrates reading of the data from an image supply source memory. It is a figure which illustrates reading of the data from an image supply source memory. It is a figure explaining the problem in case a read object area | region is not a multiple of a bus width. It is a figure explaining the solution in case a read object area | region is not a multiple of a bus width. It is a figure which illustrates reading of the data from an image supply source memory. 3 is a block diagram illustrating a read I / F circuit. FIG. It is a figure which illustrates the data input to a write buffer. It is a figure which illustrates the data extraction from a write buffer.

<Overall configuration>
FIG. 1 illustrates a block diagram of an image processing apparatus 1 according to the embodiment. 1, the image processing apparatus 1 includes a plurality of image processing module units 2, a module arbiter unit 3, a DMAC (Direct Memory Access Controller) unit 4, a bus 10, a memory 11, and a CPU 12. Is included. In addition, although the three image processing module parts 2 are illustrated here, it is not limited to this example. Further, when distinguishing the three processing module units 2, reference numerals 2a, 2b, and 2c are used. Such notation may also be used for other elements.

  The image processing module unit 2a includes a module core 5a, a read interface (I / F) circuit 6Ra that is an image processing interface circuit for reading, and a write interface (I / F) circuit 6Wa that is an image processing interface circuit for writing. Including. Similarly, the image processing module units 2b and 2c include module cores 5b and 5c, read I / F circuits 6Rb and 6Rc, and write I / F circuits 6Wb and 6Wc, respectively. The module arbiter unit 3 includes a read arbiter 3R and a write arbiter 3W. The DMAC unit 4 includes a read DMAC 4R and a write DMAC 4W.

  As shown in FIG. 1, the module core 5a is connected to the read I / F circuit 6Ra, and similarly, the module cores 5b and 5c are connected to the read I / F circuits 6Rb and 6Rc, respectively. All of the three read I / F circuits 6Ra, 6Rb, 6Rc are connected to the read arbiter 3R. The read arbiter 3R is connected to the read DMAC 4R, and the read DMAC 4R is connected to the bus 10.

  The module core 5a is connected to the write I / F circuit 6Wa. Similarly, the module cores 5b and 5c are connected to the write I / F circuits 6Wb and 6Wc, respectively. The three write I / F circuits 6Wa, 6Wb, and 6Wc are all connected to the write arbiter 3W. The write arbiter 3W is connected to the write DMAC 4W, and the write DMAC 4W is connected to the bus 10.

  That is, three image processing module units 2 a, 2 b and 2 c are connected to the module arbiter unit 3, the module arbiter unit 3 is connected to the DMAC unit 4, and the DMAC unit 4 is connected to the bus 10. In this case, the DMAC unit 4 is connected between the module arbiter unit 3 and the bus 10.

  The module core 5 performs predetermined image processing (for example, compression, expansion, affine transformation, various corrections, etc.) on the input image data, and outputs the processed data as output image data. In other words, the module core 5 generates output image data from the input image data by predetermined image processing.

  The module core 5 receives input image data in units of input blocks of a predetermined size, executes image processing on the received input blocks, and outputs processed data as core output data. The core output data is also referred to as an output block corresponding to the input block. Note that the input block may be configured by one data string or may be configured as an aggregate of a plurality of data strings. The same applies to the output block.

  The image processing contents of the module cores 5a, 5b, and 5c may be different from each other, or two or more of the module cores 5a, 5b, and 5c may be cores that perform image processing of the same type or the same contents. Good. As the module core 5, an existing module core, for example, a module core provided as a so-called IP (Intellectual Property) core can be used.

  The read I / F circuit 6R reads input image data to be processed by the module core 5 from the memory 11, and performs read processing for supplying the input image data to the module core 5 in units of input blocks. The write I / F circuit 6W receives output blocks from the module core 5 and performs a write process for writing these output blocks to the memory 11 as output image data.

  The module arbiter unit 3 arbitrates access to the memory 11 by the image processing module units 2a, 2b, and 2c.

  Specifically, the read arbiter 3R receives read requests for the memory 11 from the three read I / F circuits 6R, arbitrates them according to a predetermined arbitration method, and passes the read request selected by the arbitration to the read DMAC 4R. . The read request is accompanied by information for specifying the read target area on the memory 11.

  The write arbiter 3W receives write requests for the memory 11 from the three write I / F circuits 6W, arbitrates them according to a predetermined arbitration method, and delivers the write request selected by the arbitration to the write DMAC 4W. The write request is accompanied by data to be written and information for specifying a write destination area on the memory 11.

  In the following, a case where the read target area is specified by the start address and the end address is illustrated, and the write destination area is similarly illustrated. However, it is not limited to this example. For example, the read target area and the write destination area can be specified by the start address and the area length.

  Here, as an arbitration method using the arbiters 3R and 3W, a round robin method is exemplified. In the round robin method, multiple types of prioritization are prepared in advance between memory access requests (denoted as RQa, RQb, and RQc) of the image processing module units 2a, 2b, and 2c. If arbitration is performed based on any one of the prioritizations, the prioritization to be used is switched.

  More specifically, for example, three types of prioritization are prepared in advance: (i) RQa> RQb> RQc, (ii) RQb> RQc> RQa, and (iii) RQc> RQa> RQb. For example, RQa> RQb indicates that RQa has a higher priority than RQb. Assume that RQa and RQc compete in a state where the prioritization in (i) is valid. In this case, RQa having a higher priority is selected according to (i) above. Then, the prioritization in which the selected RQa is defined at the bottom, that is, the above (ii) is made effective in the next arbitration.

  Other arbitration methods may be adopted for the arbiters 3R and 3W. However, the round robin method is an example of a simple algorithm, and therefore the arbiters 3R and 3W can be configured on a small scale.

  The DMAC unit 4 executes memory access related to the arbitration result by the module arbiter unit 3.

  Specifically, the read DMAC 4R has a bus interface (I / F) conforming to a predetermined bus specification (in other words, a bus protocol). The read DMAC 4R controls the bus I / F according to a read request delivered from the read arbiter 3R. As a result, data is read from the read target area of the memory 11 specified by the read request. The read DMAC 4R transfers the read data to the read I / F circuit 6R that issued the read request.

  Similarly, the write DMAC 4W has a bus I / F, and the write DMAC 4W controls the bus I / F according to the write request delivered from the write arbiter 3W. More specifically, the write DMAC 4W controls the bus I / F so that write target data related to the write request is stored in the write destination area specified by the write request.

  Here, for the sake of explanation, a case where the bus I / F of the DMAC 4R, 4W conforms to AXI (Advanced eXtensible Interface) is illustrated. However, it is not limited to this example. According to AXI, burst transfer is possible. The AXI transfer control information includes a burst length, a burst size, and the like. Specifically, the burst length is the number of data transfers performed in one burst transfer, and can basically be set to any one of 1 to 16 times in terms of specifications. The burst size is the maximum transfer amount in each data transfer during one burst transfer, and can be set to any one of 1, 2, 4, 8, 16, 32, 64, and 128 bytes in the specification.

  The bus 10 includes, for example, a data bus, an address bus, a control bus, and the like. Here, the case where the data bus is 128 bits wide is illustrated. In this case, the maximum burst size that can be set is 16 bytes (128 bits). In AXI, the bus may be referred to as a channel.

  The memory 11 stores image data input to the image processing module unit 2, image data output from the image processing module unit 2, and the like. Therefore, the memory 11 functions as an image supply source memory that supplies input image data, and also functions as an image storage destination memory that stores output image data. Note that the image supply source memory and the image storage destination memory may be configured by separate components.

  Here, a case where the memory 11 is a DRAM (Dynamic Random Access Memory) is illustrated, and the memory 11 is also referred to as a DRAM 11 below. Further, the case where the DRAM 11 is aligned with 32 bytes, in other words, the case where the DRAM 11 has a 32-byte boundary is illustrated. However, it is not limited to these examples.

  The CPU 12 performs overall control of the image processing apparatus 1. For example, the CPU 12 provides the image processing module unit 2 with an instruction to execute image processing and information necessary for the execution.

  Note that another module, for example, a module that provides an interface for external connection (for an external storage medium, a display device, etc.) may be connected to the bus 10.

  The image processing apparatus 1 can be provided as an image integrated circuit integrated on one chip, but is not limited to this example. The image processing apparatus 1 can be variously modified. For example, the CPU 12 can be modified so that the CPU 12 is omitted from the image processing apparatus 1 and an external CPU is connected to the image processing apparatus 1. Further, instead of the CPU 12 or together with the CPU 12, one or both of the memory 11 and the bus 10 may be omitted from the image processing apparatus 1.

  According to the image processing apparatus 1, the three image processing module units 2a, 2b, and 2c share the DMAC unit 4. Therefore, the number of DMAC units 4 is reduced as compared with the configuration in which the DMAC unit 4 is provided for each of the image processing module units 2a, 2b and 2c. Thereby, the chip area can be reduced. As a result, it is possible to reduce the size and power consumption of the device.

<Description of images etc.>
Before illustrating the image processing apparatus 1 more specifically, images and the like will be described. FIG. 2 illustrates a quadrangular image G, and in order to make the explanation easy to understand, two orthogonal sides of the quadrilateral are horizontal (in other words, horizontal) H and vertical (in other words, vertical) V. It corresponds to each. Unlike the example of FIG. 2, the image G may be vertically long. It is assumed that the horizontal direction H of the image G corresponds to the ROW line direction of the DRAM 11.

  As shown in FIG. 2, the image G is grasped as an aggregate of the pixels PX. In FIG. 2, the pixels PX are aligned in both the horizontal direction H and the vertical direction V. That is, the pixels PX are arranged in a matrix.

  Here, a group of pixels PX arranged in the horizontal direction H is referred to as a pixel line PL. In this case, in the image G, each pixel line PL extends in the horizontal direction H, and a plurality of pixel lines PL are arranged in the vertical direction V. Further, in the image G, the pixel lines PL have the same length (that is, the number of pixels is the same), the positions of the start ends (here, left ends) of the pixel lines PL are aligned, and the end (here, The right end) is also aligned.

  As shown in FIGS. 3 and 4, a macroblock MB that is a group of pixels PX is set for the image G. Here, in the example of FIG. 4, the macroblock MB is composed of 8 pixels continuous in the horizontal direction H × 8 pixels continuous in the vertical direction V. However, the size of the macroblock MB is not limited to this example. For example, H.C. In H.264, the macroblock size can be selected from 16 × 16, 16 × 8, 8 × 16, 8 × 4, 4 × 8, and 4 × 4.

  As shown in FIG. 3, the macro blocks MB are set to be adjacent to each other with the upper left corner of the image G as a starting point (in other words, the origin). As a result, the macroblock MB is set in a matrix for the image G.

  Here, a group of pixels PX arranged in the horizontal direction H in the macroblock MB, in other words, a portion existing in the macroblock MB in the pixel line PL is referred to as an intra-block pixel line ML (see FIG. 4). I will decide. A group of macroblocks MB arranged in the horizontal direction H is referred to as a block line BL (see FIG. 3).

  In order to simplify the description, the case where the width (size along the horizontal direction H) and the height (size along the vertical direction V) of the image G are multiples of those of the macroblock MB is exemplified. That is, in the illustration that the macroblock MB has a size of 8 pixels wide × 8 pixels high, it is assumed that the number of pixels in the horizontal direction H and the vertical direction V of the image G is a multiple of 8.

  When the number of pixels of the image G is not a multiple of 8 in one or both of the horizontal direction H and the vertical direction V, when the image G is divided in units of the macroblock MB, a small image less than the size of the macroblock MB is generated. For example, such a small image is enlarged to the size of the macroblock MB by padding dummy data and used for image processing.

  When the image G is grasped as an aggregate of the pixels PX as described above, the data of the image G can be managed as an aggregate of image data (that is, pixel data) for each pixel PX.

  On the other hand, pixel data may be converted into data of another predetermined format, and image data may be constituted by such converted data. For example, image data that has been subjected to compression processing can be used.

  The compression processing is performed in units of macroblocks MB set for pixels (in other words, for pixel data), and stream data (in other words, sequential data) is generated for each macroblock MB. For this reason, the compressed image data is grasped as an aggregate of such stream data, for example, as a configuration in which each macroblock MB is regarded as stream data in FIG.

  Here, when the image data is composed of pixel data, a data string composed of pixel data arranged in the horizontal direction H corresponds to one pixel line PL. In addition, when the image data is composed of predetermined stream data, a data string composed of stream data arranged in the horizontal direction H is a predetermined number (the number included in the macroblock MB) of pixel lines PL, that is, pixels. Corresponds to the group of lines PL.

<Multi-line mode and 1-line mode>
Here, when the input block of the module core 5 is the macro block MB, that is, the input block is set for the plurality of pixel lines PL, thereby including a plurality of data strings (each corresponding to the pixel line PL). This case is referred to as a multiple line mode.

  On the other hand, the case where the input block of the module core 5 is predetermined stream data, that is, the case where the input block is composed of one data string is referred to as a one-line mode.

  Similarly, for the output block of the module core 5, a multi-line mode and a one-line mode are defined.

  Specific examples of the read I / F circuit 6R and the write I / F circuit 6W will be described below, but a case where both the input and output of the module core 5 are in the multi-line mode is mainly given as an example. For example, processing such as pixel value correction and image resizing corresponds to this. The case where the input is a multi-line mode and the output is a single-line mode (for example, compression processing) and the case where the input is a single-line mode and the output is a multi-line mode (for example, decompression processing) are sufficient from the following description. To be understood.

<Read I / F circuit 6R>
FIG. 5 illustrates a block diagram of the read I / F circuit 6R. According to the example of FIG. 5, the read I / F circuit 6 </ b> R includes a core side input / output unit 100, a read buffer 110, a read management unit 130, and a core input management unit 150.

<Core side input unit 100>
The core side input / output unit 100 is provided in accordance with an example in which the operation clock of the read I / F circuit 6R is synchronized with that of the read arbiter 3R, but is not synchronized with the operation clock of the module core 5. Yes. For this reason, when the operation clock of the read I / F circuit 6R is synchronized with that of the module core 5, the core-side input / output unit 100 can be omitted. According to the example of FIG. 3, the core-side input / output unit 100 includes an asynchronous FIFO (First In First Out) unit 101 for input and an asynchronous FIFO unit 102 for output.

<Read buffer 110>
The read buffer 110 is used to temporarily store data read from the DRAM 11. In the example of FIG. 6, the read buffer 110 has eight read line FIFO units 111. The eight readout line FIFO units 111 are respectively assigned to the eight pixel lines PL in which the macro block MB (that is, the input block) is set. Specifically, assuming that i = 0 to 7, the data of the i-th pixel line PL counted from the top in the macroblock MB is stored in the i-th readout line FIFO unit 111.

  Here, the number of line FIFO units 111 is equal to or more than the number of pixel lines PL in which the macroblock MB is set. For example, if 16 line FIFO units 111 are provided, a maximum of 16 pixel lines PL can be supported, and a predetermined 8 line FIFO units 111 are used, for example, a macro for 8 pixel lines PL. The block MB can be supported. The same applies to the 1-line mode.

  Each line FIFO unit 111 has 32 storage areas 112. The number of storage areas 112 per line FIFO unit 111 is selected to be Z times the maximum number of data transfers (16 times in AXI) that can be set in one burst transfer. Here, Z = 2, but is not limited to this (described later).

  The capacity of one storage area 112 is basically selected to be 16 bytes (128 bits), which is the same as the data bus width (in other words, the maximum burst size that can be set in terms of hardware design). . In this case, one line FIFO unit 111 can store data for two burst transfers at maximum. In the example described later, the capacity of one storage area 112 is expanded to 132 bits (= 128 bits + 4 bits).

  Here, in the case of 8-bit YUV422, the amount of image data for 8 pixels, that is, the amount of image data for one pixel line in the block ML is 16 bytes. Therefore, data for one pixel line ML in the block can be stored in one storage area 112, and one storage area 112 (one storage in each of the 0th to 7th line FIFO units 111). The data for one macroblock MB can be stored in the area 112). That is, 32 macroblock MB data can be stored in the entire read buffer 110.

  Here, a case where the read buffer 110 is configured with two SRAMs (Static Random Access Memory) 113 and 114, that is, a case where a double buffer configuration is adopted is illustrated. However, the read buffer 110 can be configured by one SRAM or three or more SRAMs, or a memory other than the SRAM can be used.

  One storage area 112 is allocated to one address of the SRAMs 113 and 114, so that 16 bytes of data can be stored in one address. Data for one address is read and written at a time. In this case, the word length of the SRAMs 113 and 114 is 16 bytes.

  Each line FIFO unit 111 includes 16 storage areas 112 in the SRAM 113 (these addresses are continuous) and 16 storage areas 112 in the SRAM 114 (the 16 storage areas 112 in the SRAM 113). And the same address are prepared). Writing to the 16 storage areas 112 in the SRAM 113 is performed cyclically in order from the smallest address, and reading is the same. Thereby, FIFO is realized. The same applies to the 16 storage areas 112 in the SRAM 114.

  Access to the SRAM 113 and access to the SRAM 114 can be executed independently. Therefore, for example, it is possible to read data from one SRAM among the SRAMs 113 and 114 while reading data from the other SRAM. Note that when accesses collide with the same SRAM, for example, writing may be prioritized and reading may be waited for one cycle.

  FIG. 7 shows an example in which data is written while the SRAMs 113 and 114 are alternately switched. That is, the 0th data D0 is written to the SRAM 113, the first data D1 is written to the SRAM 114, the second data D2 is written to the SRAM 113, and the third data D3 is written to the SRAM 114. According to this, for example, it is possible to read the data D0 from the SRAM 113 while writing the data D1 to the SRAM 114.

  Of course, it is also possible to write continuously to the 16 storage areas 112 of the SRAM 113 and then switch the write destination to the SRAM 114.

<Read manager 130>
The read management unit 130 manages data transfer from the DRAM 11 memory to the read buffer 110. According to the example of FIG. 5, the read management unit 130 includes an address conversion unit 131, synchronous FIFO units 132 and 133, and an end determination unit 134.

  The address conversion unit 131 acquires information necessary for reading input image data (hereinafter, referred to as read basic information) from the module core 5 via the asynchronous FIFO unit 101. The basic read information includes, for example, the start address and end address of the area where the input image data is stored in the DRAM 11, the size of the macro block MB (that is, the input block of the module core 5), and the number of macro blocks MB in the image horizontal direction H. , Etc.

  The address conversion unit 131 determines a read target area (more specifically, a start address and an end address of the area) on the DRAM 11 based on the acquired basic read information. At this time, the read target area is determined according to a predetermined read condition so that the input image data is burst transferred to the read buffer 110. The determination method will be described in detail later.

  The address conversion unit 131 inputs the start address and end address of the read target area together with the read request to the read arbiter 3R. Thereafter, based on the start address and end address of the read target area acquired by the read DMAC 4R via the read arbiter 3R, the data in the read target area is burst transferred from the DRAM 11 to the read buffer 110 via the read arbiter 3R. To do.

  Further, the address conversion unit 131 issues write control for the read buffer 110 for each read request. Such write control is input to the synchronous FIFO unit 132 and used when data related to a corresponding read request is stored in the read buffer 110. Thereby, for example, the data of the i-th pixel line PL in the macro block MB can be stored in the corresponding i-th line FIFO unit 111.

  Further, the address conversion unit 131 inputs the data size of the read target area to the synchronous FIFO unit 133 for each read request. The data size is used by the end determination unit 134 to detect the end of reading related to each read request. Specifically, the end determination unit 134 counts the number of bytes of data input from the DRAM 11 to the read buffer 110 via the read arbiter 3R, and the count value is the data size input to the synchronous FIFO unit 133. Therefore, it is determined that the reading of the desired reading target area has been completed, and the notification is input to the reading arbiter 3R.

  When the address conversion unit 131 determines that the determined end address of the read target area has reached the end address of the input image data, the determination result is input to the synchronous FIFO unit 133. The end determination unit 134 knows that reading of the entire input image data is completed by obtaining the determination result from the synchronous FIFO unit 133, and inputs the notification to the read arbiter 3R.

<Core input management unit 150>
The core input management unit 150 supplies the data stored in the read buffer 110 to the module core 5 in units of input blocks (here, in units of macro blocks). According to the example of FIG. 5, the core input management unit 150 includes an address calculation unit 151 and a format conversion unit 152.

  The address calculation unit 151 acquires the read basic information from the module core 5 and controls data reading from the read buffer 110 based on the basic information. Specifically, while the 0th to 7th line FIFO units 111 are cyclically selected, the data of the number of bytes corresponding to one pixel line ML in the block is read from the selected line FIFO unit 111. The address in the read buffer 110 is designated.

  In each storage area 112 of the line FIFO unit 111, basically, if a read operation is performed once, the stored data can be discarded or overwritten. However, in some cases, desired data may straddle the two storage areas 112, and it is necessary to prepare for such a case. Specifically, there is a possibility that the storage area 112 that stores the rear portion of the desired data also holds a part of the data that has not been read yet. For this reason, for example, only the read portion of the data in the storage area 112 may be deleted.

  The format conversion unit 152 converts the data read from the read buffer 110 into a predetermined format suitable for the input of the module core 5. For example, a process of dividing 128-bit data output from the read buffer 110 into a predetermined bit width is performed. Output data from the format conversion unit 152 is supplied to the module core 5 via the asynchronous FIFO unit 102.

<Effects of Read I / F Circuit 6R>
According to the read I / F circuit 6R, input blocks for a plurality of times are read to the read buffer 110 in advance, and these input blocks are sequentially supplied to the module core 5. In addition, the read target area of the DRAM 11 is determined so that burst transfer is used for reading the input block. Therefore, the frequency of read requests by the image processing module units 2 can be suppressed as compared with the configuration in which the input block is read each time it is required by the module core 5. Thereby, the bus bandwidth can be used efficiently.

  Further, as the frequency of read requests by each image processing module unit 2 is suppressed, the read arbiter 3R is caused to perform band adjustment performed by an existing so-called bus arbiter (arbiter connected to the bus and arbitrating the right to use the bus). Less need. Therefore, a simpler algorithm can be adopted for the read arbiter 3R than the bus arbiter, and as a result, the read arbiter 3R can be configured on a small scale.

<Reading Data by Read I / F Circuit 6R>
FIG. 8 schematically shows how the read I / F circuit 6 </ b> R reads data from the DRAM 11. As illustrated in FIGS. 8 and 9, the read I / F circuit 6 </ b> R performs reading on a block line BL that is a group of macroblocks MB.

  Specifically, burst transfer is repeated for each pixel line PL in the block line BL from the start end (here, the left end) toward the end (here, the right end). In particular, as shown in FIG. 9 corresponding to FIG. 8, burst transfer is performed from the beginning of the 0th pixel line PL counted from the top, and then burst transfer is performed from the beginning of the first pixel line PL. Thereafter, the second to seventh pixel lines PL are selected in order, and burst transfer is performed from the beginning of each pixel line PL. Then, returning to the 0th pixel line PL, burst transfer is performed from the head of the portion where reading has not been completed. Next, burst transfer is performed from the beginning of the portion of the first pixel line PL that has not been read out. In the same manner, reading is performed on the entire block line BL.

  Although FIG. 8 illustrates a case where reading of pixel data for one pixel line PL is completed by three burst transfers, the present invention is not limited to this example.

  At this time, one burst transfer is basically set to the maximum transfer amount that can be set. In the case of the image processing apparatus 1, data transfer of a maximum of 256 bytes is possible with a burst size of 16 bytes (128 bits) and a burst length of 16 times.

  The target of each burst transfer, that is, the read target area in the DRAM 11 is set by the read management unit 130 (more specifically, the address conversion unit 131) as described above. At this time, the read management unit 130 performs the read illustrated in FIGS. 8 and 9 by following the following read conditions.

  That is, a condition for cyclically selecting eight input image data strings corresponding to eight pixel lines PL in the block line BL (circular selection condition), and in order from the top of the input image data string Reading is performed in accordance with a condition for setting a reading target area (in-column order condition) and a setting for setting the reading target area for each input image data string once (selection condition). The management unit 130 sequentially determines the read target area.

  According to the readout method illustrated in FIGS. 8 and 9, eight input image data strings corresponding to the eight pixel lines PL are read out partially and in parallel, and eight such readouts are performed. The process proceeds in order from the beginning of the input image data sequence.

  For this reason, compared with the case where one pixel line PL is read from the head to the end and then reading of the other pixel lines PL is started, the data supply to the module core 5 is less likely to be delayed. That is, in the latter case, for example, the time required to supply the macro block MB set at the most leading side to the module core 5 is substantially equal to the time required to read the entire eight pixel lines PL, that is, the entire block line BL.

  On the other hand, according to the partial and parallel readout shown in FIGS. 8 and 9, the most macro block MB is transferred to the module core 5 without waiting for the readout of the entire eight pixel lines PL. You can finish supplying.

  Further, according to such partial and parallel reading, the capacity of the read buffer 110 can be reduced.

  Here, it is preferable to consider the address alignment of the DRAM 11 when setting the read target area. This is because the operation of the DRAM 11 can be made efficient. As a read condition relating to this point, a condition (read alignment condition) is adopted in which the end address of the read target area is aligned with the address alignment boundary (32-byte boundary here) of the DRAM 11.

According to the read alignment condition, when a certain starting address is given, the end address can be calculated by {(start address ^& ~ 0x1f) +255 bytes}.

  By adopting the read alignment condition, it is possible to operate the DRAM 11 more efficiently than when the read target region crosses the address alignment boundary of the DRAM 11. Thereby, it contributes to improvement of data transfer efficiency and power saving.

  By the way, if the end address of the read target area is adjusted according to the read alignment condition, the read target area may be shorter than 256 bytes in the first burst transfer and the last burst transfer of the pixel line PL as shown in FIG. . In such a case, for example, the setting of the burst length is adjusted by the read DMAC 4R.

  In addition, as a result of the shortening of the read target area, the read target area may not be a multiple of the bus width (here 128 bits). In view of the point that the read I / F circuit 6R receives data from the bus 10 in units of bus width, when the read target area is not a multiple of the bus width, as shown in FIG. Data will be picked up from the bus 10 together. In particular, since such unnecessary data is included in the end portion of the received bit string, if it is input to the read buffer 110 as it is, unnecessary data interrupts with the next read target area data as shown in FIG. It will be. The core input management unit 150 (more specifically, the address calculation unit 151) may be configured not to supply such unnecessary data to the module core 5, but in order to do so, it is necessary to manage the position and size of the unnecessary data. It is complicated.

  Therefore, when the readout target area includes the start end of the pixel line PL, the readout management unit 130 sets a condition that the start address of the readout target area is set so that the data amount of the readout target area is a multiple of the bus width (read out). Size size). According to this, as shown in FIG. 12, unnecessary data can be left-justified in the received bit string. In other words, data significant for input image data can be left-justified in the received bit string. That is, adjustment of the start address of the read target area includes unnecessary data in the received bit string, but such unnecessary data can be intentionally arranged in front of the received bit string.

Therefore, as shown in FIG. 12, it is possible to avoid unnecessary data from being interrupted in the data string corresponding to one pixel line PL. This facilitates management and removal of unnecessary data. Specifically, the core input management unit 150 may ignore head data corresponding to the adjustment amount of the read start address in the data string corresponding to each pixel line PL. The adjustment amount is given by the amount masked by ^~ 0x1f according to the read alignment condition, in other words, the lower 5 bits of the start address before the read alignment condition is applied.

  More specifically, the storage area 112 of the line FIFO unit 111 is provided with 4 bits for storing the read start address adjustment amount before 128 bits for storing the read data. In the core input management unit 150, the address calculation unit 151 or the format conversion unit 152 refers to the first 4 bits of each storage area 112, so that the presence / absence of unnecessary data and the size of unnecessary data (that is, of the following 128 bits) The amount of data not supplied to the module core 5) can be determined.

  As shown in FIG. 12, the read target area may not be a multiple of the bus width as a result of the shortened read target area even on the terminal side of the pixel line PL. However, regarding the end side of the pixel line PL, there is no particular problem even if unnecessary data exists at the end portion of the received bit string. This is because, for example, when the amount of data supplied to the module core 5 reaches one line of the pixel line PL, the subsequent bits output from the storage area 112 may be ignored. This is because it can be removed.

Next, conditions (end address conditions) related to setting the end address of the read target area will be described. The end address of the read target area is basically set to (start address + 255 bytes). However, as described above, under the read alignment condition, in consideration of the address alignment boundary of DRAM 11, the end address is given by {(the start address ^& ~ 0x1f) +255 bytes}.

  When the unread portion in the pixel line PL is equal to or less than the maximum transfer amount (256 bytes in this case) of burst transfer, the end address of the read target region is set as the end address of the pixel line PL. That is, FIG. 8 and FIG. 9 illustrate an example in which the last read target area of the pixel line PL also corresponds to the maximum transfer amount, but particularly when the last read target area is smaller than the maximum transfer amount. The end address may be set in accordance with the size of the read target area. According to this, an unnecessary transfer operation can be suppressed for reading of the terminal side portion of the pixel line PL. Therefore, the bus bandwidth can be used efficiently.

  In contrast, even if the unread portion of the pixel line PL is larger than the maximum transfer amount that can be set in one burst transfer, the end address of the read target region is set as the end address of the pixel line PL. May be preferred. Specifically, as shown in FIG. 10, when the last read target area of the pixel line PL is small, it is inefficient to issue a read request to read the small area. In particular, when there are many such small regions, the reduction in efficiency becomes large.

  Therefore, when the unread portion in the pixel line PL exceeds the maximum transfer amount that can be set by one burst transfer, the excess amount is set to the start address and the pixel set under the read size condition. If the difference from the head address of the line PL is larger than the basic end address condition, the end address of the read target area is set in accordance with the maximum transfer amount. The difference corresponds to the adjustment amount of the start address under the read alignment condition.

  According to this, it is possible to secure the maximum amount of data that can be transferred with a single read request. For this reason, the data transfer can be performed efficiently by suppressing the increase in the number of read requests. In addition, since the frequency of read requests is suppressed as data transfer becomes more efficient, the processing load on the read arbiter can be reduced.

  On the other hand, when the excess amount is equal to or less than the difference, the end address of the read target area is set as the end address of the pixel line PL. According to this, as shown in FIG. 13, it is possible to avoid the occurrence of such a small region. In this case, in addition to the maximum amount of data that can be burst transferred, the data in the small area can be secured by a single read request. In addition, as shown in FIG. 13, the number of read requests is equalized for each pixel line PL. As a result, an increase in the number of read requests is suppressed, so that data transfer can be performed efficiently. In addition, since the frequency of read requests is suppressed as data transfer becomes more efficient, the processing load on the read arbiter can be reduced.

  According to the end address condition when the excess amount is equal to or less than the difference, a read request is made exceeding the data amount that can be set by one burst transfer. Even in such a case, it is divided into two or more burst transfers by the read DMAC 4R. On the other hand, in order to store the read data, the line FIFO unit 111 needs to be able to accept 17 or more storage areas 112. For this reason, the end address condition may be used together with confirmation of the availability of the line FIFO unit 111.

<Write I / F circuit 6W>
FIG. 14 illustrates a block diagram of the write I / F circuit 6W. According to the example of FIG. 14, the write I / F circuit 6 </ b> W includes a core-side input / output unit 200, a write buffer 210, a write management unit 230, and a core output management unit 250.

<Core-side input unit 200>
The core side input / output unit 200 is provided for the same purpose as the core side input / output unit 100 (see FIG. 5) of the read I / F circuit 6R. According to the example of FIG. 14, the core side input / output unit 200 includes asynchronous FIFO units 201 and 202 and an asynchronous pulse unit 203 for input.

<Write buffer 210>
The write buffer 210 is used to temporarily store core output data (in other words, an output block) output from the module core 5. Here, as an example, the write buffer 210 is configured with eight write line FIFO units composed of two SRAMs, like the read buffer 110 of the read I / F circuit 6R. In this case, similarly to the read buffer 110, the eight write line FIFO units are respectively assigned to the eight pixel lines PL included in the output block.

  In this example, the number of pixel lines PL included in the output block is the same as the number of pixel lines PL in which the input block is set. For example, the module core 5 performs resizing so that the image is reduced in the vertical direction V. When processing is performed, the number of pixel lines PL corresponding to the output block is smaller than the number of pixel lines PL corresponding to the input block. On the contrary, in the resizing process for enlarging the image in the vertical direction V, the number of pixel lines PL corresponding to the output block is larger than the number of pixel lines PL corresponding to the input block.

<Core output management unit 250>
The core output management unit 250 manages input of core output data to the write buffer 210. According to the example of FIG. 14, the core output management unit 250 includes an address calculation unit 251 and a format conversion unit 252.

  The core output data is input from the module core 5 to the format conversion unit 252 via the asynchronous FIFO unit 202. The format conversion unit 252 converts the core output data configured in a predetermined format into a format suitable for input to the write buffer 210. For example, the bit string of the core output data is converted into one word (128 bits) unit of the write buffer 210.

  The address calculation unit 251 controls in which address of the write buffer 210 the output data of the format conversion unit 252 is stored. Specifically, the address calculation unit 251 acquires information necessary for writing output image data to the DRAM 11 (hereinafter referred to as write basic information) from the module core 5 via the asynchronous FIFO unit 201. The basic write information includes, for example, the start address and end address of the output image data storage destination area in the DRAM 11, the size of the output block of the module core 5 (in other words, the macroblock MB on the output side), and the output block in the image horizontal direction H Number of the like, etc.

  The information on the number of output blocks in the image horizontal direction H serves as an index of the end position of the pixel line PL. For example, when the module core 5 outputs data at the end of the pixel line PL, the notification is sent as an asynchronous pulse. The data may be output to the address calculation unit 251 via the unit 203.

<Write manager 230>
The write management unit 230 manages the transfer of data stored in the write buffer 210 to the DRAM 11. According to the example of FIG. 14, the write management unit 230 includes an address conversion unit 231, synchronous FIFO units 232 and 233, and an end determination unit 234.

  The address conversion unit 231 acquires the write basic information from the module core 5. As described above, instead of information on the number of output blocks in the image horizontal direction H, for example, a notification issued when the module core 5 outputs data at the end of the pixel line PL is acquired via the asynchronous pulse unit 203. May be.

  Then, the address conversion unit 231 controls reading of data from the write buffer 210 based on the acquired basic information. Specifically, the address conversion unit 231 collects the output block data stored in the write line FIFO unit as shown in FIG. 15 for burst transfer as shown in FIG. Further, the address conversion unit 231 sets a start address and an end address of a write destination area on the DRAM 11 which is a storage destination of the write target data collected in this way.

  The write target data and the write destination area are input to the write arbiter 3W together with the write request. Thereafter, the write DMAC 4W performs burst transfer of the write target data to the write destination area acquired via the write arbiter 3W.

  The write management unit 231 determines write target data and a write destination area for each write line FIFO unit, and the determination is performed according to a predetermined write condition. Write conditions will be described later.

  Further, the address conversion unit 231 issues a read control to the write buffer 210 for each write request. Such read control is input to the synchronous FIFO unit 232 and used when taking out write target data from the write buffer 210.

  In addition, the address conversion unit 231 inputs the data size of the write destination area to the synchronous FIFO unit 233 for each write request. The data size is used by the end determination unit 234 to detect the end of writing related to each write request. Specifically, the end determination unit 234 counts the number of bytes of data transferred from the write buffer 210 to the DRAM 11 via the write arbiter 3W, and the count value is input to the synchronous FIFO unit 233. Therefore, it is determined that the writing of the desired write target data has been completed, and the notification is input to the write arbiter 3W.

  If the address conversion unit 231 determines that a write request has been issued for all the output image data, the determination result is input to the synchronous FIFO unit 233. The end determination unit 234 knows that writing has been completed for the entire output image data by acquiring the determination result from the synchronous FIFO unit 233, and inputs the notification to the write arbiter 3W.

<Effects of write I / F circuit 6W>
According to the write I / F circuit 6W, a plurality of output blocks are accumulated in the write buffer 210, and are collectively transferred to the DRAM 11 in a burst manner. Therefore, the frequency of write requests by each image processing module unit 2 can be suppressed as compared with the configuration in which the output block is transferred to the DRAM 11 each time an output block is output from the module core 5. Thereby, the bus bandwidth can be used efficiently.

  Further, as the frequency of write requests by each image processing module unit 2 is suppressed, it is less necessary for the write arbiter 3W to perform band adjustment performed by an existing so-called bus arbiter. Therefore, a simpler algorithm can be employed for the write arbiter 3W than the bus arbiter, and as a result, the write arbiter 3W can be configured on a small scale.

<Data writing by write I / F circuit 6W>
The write I / F circuit 6W monitors whether or not the accumulated amount of unwritten data (data not yet written to the DRAM 11) exceeds a predetermined threshold for each write line FIFO unit, and the accumulated amount of unwritten data is When the predetermined threshold value is exceeded, the unwritten data is selected as write target data and a write request is issued.

  The predetermined threshold is basically the maximum transfer amount that can be set by one burst transfer. That is, a condition (write size condition) for setting the write target data to the maximum transfer amount is applied. According to the write size condition, data transfer can be performed efficiently. In addition, since the frequency of write requests is suppressed as data transfer becomes more efficient, the processing load on the write arbiter 3W can be reduced.

  However, when unwritten data reaches the end of the pixel line in the output image output from the module core 5, the data to be written is divided within the range up to the core output data corresponding to the end, It is preferable to set a write destination area in accordance with the range (in other words, the size of the write target data) (line termination condition). According to this, an unnecessary transfer operation can be suppressed for writing at the line end side portion. Therefore, the bus bandwidth can be used efficiently.

  Further, like the read I / F circuit 6R, it is preferable to consider the address alignment of the DRAM 11. Specifically, a condition (write alignment condition) that the write destination area in the DRAM 11 is aligned with the address alignment boundary of the DRAM 11 is employed. According to the write alignment condition, it is possible to operate the DRAM 11 more efficiently than when the write destination region crosses the address alignment boundary of the DRAM 11. Thereby, it contributes to improvement of data transfer efficiency and power saving.

<Modification 1>
In the above, the case where the number of the storage areas 112 in each line FIFO unit 111 is twice the maximum number of data transfers that can be set by one burst transfer (16 times in AXI). However, it is not limited to this example.

  Specifically, the number of storage areas 112 of each line FIFO unit 111 is more than one time and less than twice the maximum number of data transfers that can be set in one burst transfer (16 times in AXI). May be. In this case, the capacity of each line FIFO unit 111 is larger than one time and smaller than twice the maximum transfer amount that can be set by one burst transfer.

  Even in such a design, in each line FIFO unit 111, data supplied to the module core 5 is read from the DRAM 11 in place of the supplied data because the data transferred to the module core 5 exceeds the maximum transfer amount of burst transfer. New data may be stored in the line FIFO unit 111. According to this example, the capacity of the read buffer 110 can be reduced. As a result, it is possible to reduce the chip area, downsize the device, save power, and the like.

  Such a modification can also be applied to the write buffer 210.

<Modification 2>
In the above, the case where the macroblock MB is set for the eight pixel lines PL, the read buffer 110 is configured by the eight line FIFO units 111, and the burst length is 16 times is illustrated. On the other hand, for example, when the macro block MB corresponds to 16 pixel lines PL, it is possible to prepare 16 line FIFO units 111 by dividing each line FIFO unit 111 into two. . However, in this case, the burst length is limited to a maximum of 8 times. According to such a method, it is possible to flexibly cope with macroblocks MB of various sizes without increasing the capacity of the read buffer 110.

  Such a modification can also be applied to the write buffer 210.

<Modification 3>
In the above, the case where one image data is a processing target is illustrated. On the other hand, it is also possible to process in parallel while switching a plurality of image data. For example, there is an example in which common macroblocks MB set at the same position on the image are processed in parallel while switching the image data for each of the Y, U, and V components.

<Modification 4>
Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  The image processing apparatus according to the present invention can be mounted on, for example, a digital camera. However, it is not limited to this example.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2,2a-2c Image processing module part 3 Module arbiter part 3R Read arbiter 3W Write arbiter 4 DMAC part 4R Read DMAC
4W write DMAC
5, 5a to 5c Module core 6R, 6Ra to 6Rc Read I / F circuit (image processing interface circuit)
6W, 6Wa ~ 6Wb Write I / F circuit (image processing interface circuit)
10 buses 11 memory (image supply source memory, image storage destination memory)
DESCRIPTION OF SYMBOLS 110 Read buffer 130 Read management part 150 Core input management part 210 Write buffer 230 Write management part 250 Core output management part PX Pixel PL Pixel line MB Macroblock BL Block line

Claims (12)

An image processing interface circuit connected to a module core that executes predetermined image processing,
A read buffer for storing data read from the image supply source memory connected to the bus;
A read manager that manages data transfer from the image source memory to the read buffer;
A core input management unit that supplies storage data in the read buffer to the module core in units of input blocks of a predetermined size;
The read management unit manages reading of input image data to be processed by the module core so that a plurality of input blocks are stored in the read buffer, and the image so that the input image data is burst transferred. Determining a read target area on the source memory according to a predetermined read condition;
Image processing interface circuit. The image processing interface circuit according to claim 1,
The input image data includes a plurality of input image data strings each corresponding to a pixel line or a pixel line group,
The input block is set for N input image data strings (N is an integer of 2 or more) among the plurality of input image data strings,
The read buffer includes N read line FIFO units to which the N input image data strings in which the input blocks are set are respectively input.
The predetermined read condition is:
A cyclic selection condition for cyclically selecting the N input image data strings;
An in-column order condition for setting the read target region in order from the top of the input image data sequence;
The image processing interface circuit, wherein the setting of the read target area for each input image data string includes a number condition that the read target area is set to be once for each selection. The image processing interface circuit according to claim 1,
The input image data includes a plurality of input image data strings each corresponding to a pixel line or a pixel line group,
The input block is set for one input image data sequence of the plurality of input image data sequences,
The read buffer includes one read line FIFO unit to which the one input image data string in which the input block is set is input,
The predetermined read condition is:
An image processing interface circuit including an in-column ordering condition for setting the read target area in order from the head of the input image data sequence. An image processing interface circuit according to any one of claims 1 to 3,
The image processing interface circuit, wherein the predetermined read condition includes a read alignment condition for matching an end address of the read target area with an address alignment boundary of the image supply source memory. The image processing interface circuit according to claim 4,
When the read target area includes the start end of the input image data sequence, the predetermined read condition is that the start address of the read target area is set such that the data amount of the read target area is a multiple of the bus width of the bus. An image processing interface circuit including a read size condition for setting. The image processing interface circuit according to claim 5,
The predetermined read condition is:
When the unread portion in the input image data sequence exceeds the maximum transfer amount that can be set by one burst transfer, and the excess amount is the start address set under the read size condition A first end address condition that sets an end address of the read target area in accordance with the maximum transfer amount of the burst transfer when greater than a difference from a start address of the input image data sequence;
And a second end address condition for setting the end address of the read target area to the end address of the input image data sequence when the excess amount is equal to or less than the difference. An image processing interface circuit according to any one of claims 1 to 6,
When the unread portion in the input image data sequence is less than or equal to the maximum transfer amount of the burst transfer, the predetermined read condition sets the end address of the read target area as the end address of the input image data sequence An image processing interface circuit including a third end address condition to that effect. An image processing interface circuit according to any one of claims 1 to 7,
The read buffer includes at least one read line FIFO unit having a capacity that is greater than 1 and less than 2 times the maximum transfer amount of the burst transfer,
The read management unit reads the new data read from the image supply source memory in place of the supplied data when the supplied data for the module core exceeds the maximum transfer amount in the read line FIFO unit. Store in the line FIFO section,
Image processing interface circuit. An image processing interface circuit connected to a module core that executes predetermined image processing,
A write buffer for storing core output data output from the module core;
A core output management unit that manages input of the core output data to the write buffer;
A write management unit that manages the transfer of data stored in the write buffer to an image storage destination memory connected to the bus;
The write buffer includes at least one write line FIFO (First In First Out) portion having a capacity larger than a maximum transfer amount that can be set in one burst transfer,
The write management unit determines, for each write line FIFO unit, write target data to be subjected to burst transfer among data in the write line FIFO unit and a write destination area in the image storage destination memory. Determine according to the writing conditions of
Image processing interface circuit. An image processing interface circuit according to claim 9,
The predetermined write condition is:
Write size condition for setting the write target data to the maximum transfer amount of the burst transfer,
An image processing interface circuit including at least one of a write alignment condition for aligning the write destination area with an address alignment boundary of the image storage destination memory. The image processing interface circuit according to claim 9 or 10, wherein:
The predetermined write condition divides the write target data in a range up to the core output data corresponding to the end of the pixel line or pixel line group of the output image output from the module core, and An image processing interface circuit including a line termination condition for setting the writing destination area corresponding to a range. An image processing interface circuit according to any one of claims 9 to 11,
The write line FIFO unit has a capacity that is greater than 1 and less than 2 times the maximum transfer amount of the burst transfer,
When the transferred data for the image storage destination memory exceeds the maximum transfer amount in the write line FIFO unit, the write management unit sends new core output data to the write line FIFO unit instead of the transferred data. Store,
Image processing interface circuit.

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