JP2014033278A - Channelizer and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure that when an input signal is output at a different sampling rate than the sampling rate of the input signal, the respective transition areas are not duplicated, so their pass bands do not overlap.SOLUTION: A channelizer comprises: first and second circuit demultiplexing means for demultiplexing an input signal at a sampling rate Fs into N subchannels and outputting the demultiplexed signals at a sampling rate Fs/N; first and second circuit switching means for selecting for output a desired subchannel from the subchannels output by each of the multiplexing means or outputting data 0; multiple sets of first and second circuit multiplexing means for multiplexing M subchannels out of the subchannels output by each of the switching means in such a way that the multiplexed signal has alternately arranged frequency characteristics so that the respective transition areas of subchannels are not duplicated and the their pass bands do not overlap and outputting the multiplexed signal at a sampling rate M×Fs/N; and a plurality of composing means for adding up the multiplexed signals output by each of the multiplexing means to combine them into a whole.

Description

  The present invention relates to a technology for processing frequency-multiplexed signals used in the communication field.

  A technique for filtering a signal from a frequency-multiplexed input signal with a bandwidth as required is disclosed in Patent Document 1 or Patent Document 2.

  In the filtering circuit disclosed in Patent Document 1, an input signal in which multi-channel signals are frequency-multiplexed is divided into N sub-channel signals by a shift register and a sampling circuit, and is filtered by a sub-filter to be subjected to FFT (Fast A Fourier transform is performed by a Fourier Transform (Fourier Transform) circuit, and adjacent channels are selected from the output of the FFT circuit by a switch circuit and added to be combined.

  On the other hand, in the filtering circuit disclosed in Patent Document 2, two maximum thinning digital filter banks having frequency characteristics are arranged in parallel so that the transition bands of a plurality of subchannels overlap and the passbands do not overlap. The output is arranged and combined with the output filtered by each digital filter bank. Then, by filtering the signal of the bandwidth of the input signal in which multi-channel signals are frequency-multiplexed, and controlling the passage and blocking of the signals in the subchannels in each digital filter bank, the combination can be made variable. The channels of the input signal in which multi-channel signals are frequency-multiplexed are rearranged on the frequency axis.

  FIG. 27 is a configuration example of the filtering circuit disclosed in Patent Document 1. An input signal from a QAD (Quadrature Amplitude Demodulator) (not shown) is converted into Fs (Fs: input) by N shift channels 27 and sampling circuits 26-1 to 26-N (N is a positive integer). Signal sampling rate), the sub-filters 25-1 to 25-N perform filtering at the sampling rate Fs, and the FFT circuit 24 performs high-speed complex Fourier transform at the sampling rate Fs.

  The k-th output (k is a positive integer less than or equal to N) of the FFT circuit 24 indicates the bandpass filter characteristic of the center frequency ωk. Under the control of the control unit 19, adjacent channels in the FFT circuit 24 are added at the sampling rate Fs by the switch circuit 22, thereby extracting a signal of a specific channel with the bandwidth Fs. In FIG. 27, 13 is a sampling timing generation circuit, 14 is a complex local oscillation circuit, 16 and 18 are adders, 17 is a switch element, 20 is a D / A converter, and 21 is a complex multiplier.

  FIG. 28 shows the amplitude characteristics of the specific channel signal extracted with the bandwidth Fs.

  In the filtering circuit disclosed in Patent Document 1, since a signal of a specific channel is extracted with the bandwidth Fs, the reception channelizer has a problem that the modulated signal of the extracted channel cannot be demodulated as it is. On the other hand, in the case of a transmission channelizer, when the channel of the input signal is distributed to a plurality of beams and transmitted, the frequency band of all the transmission beams must be the same frequency band Fs as the channel of the input signal. There is a problem that usage efficiency is poor.

  FIG. 29 is a configuration example of the filtering circuit disclosed in Patent Document 2. The filtering circuit includes a branch circuit 3 for branching an input into two of a first input and a second input, a first digital filter bank 1 for filtering the first input, and a first filter for filtering the second input. 2 digital filter banks 2, and a synthesis circuit 4 that synthesizes the outputs of the first digital filter bank 1 and the second digital filter bank 2.

  The first digital filter bank 1 includes a first input / N output first demultiplexing circuit 5 that demultiplexes an input into an N-sequence (N is a positive integer) signal, and a first demultiplexing circuit 5 N series outputs are input as inputs, and the N switch-N output first switch circuit 6 for controlling the passage / blocking of each series of signals and the outputs of the first switch circuits 6 are connected to one output. The first combining circuit 7 has N inputs and one output for wave generation. Similarly to the first digital filter bank 1, the second digital filter bank 2 includes a second branching circuit 8, a second switch circuit 9, and a second multiplexing circuit 10.

  The frequency characteristics of the first digital filter bank 1 and the second digital filter bank 2 are as shown in FIGS. 30B and 30C, respectively. It has the characteristic of being alternately arranged so as not to overlap.

  The first digital filter bank 1 and the second digital filter bank 2 having such frequency characteristics are arranged in parallel, and the output obtained by filtering the input signal shown in FIG. To obtain a synthesized signal shown in FIG.

  By controlling the operations of the first switch circuit 6 of the first digital filter bank 1 and the second switch circuit 9 of the second digital filter bank 2 to make the combination variable, a multi-channel The channels of the input signal on which the signal is frequency-multiplexed are rearranged on the frequency axis.

  In the filtering circuit disclosed in Patent Document 2, both the first multiplexing circuit 7 and the second multiplexing circuit 10 are used for filtering the first demultiplexing circuit 5 and the second demultiplexing circuit 8. Since multiplexing is performed at the same sampling rate as the sampling rate, the bandwidth of the combined output signal is the same as the bandwidth of the input signals of the first branching circuit 5 and the second branching circuit 8. For this reason, in the case of a reception channelizer, there is a problem that a signal of a specific channel cannot be extracted from an input signal in which multi-channel signals are accommodated by frequency division. On the other hand, in the case of a transmission channelizer, there is a problem that when a channel of an input signal is distributed and transmitted to a plurality of beams, only a necessary channel cannot be extracted and assigned to each transmission beam.

Japanese Patent Laid-Open No. 9-284242 JP 2001-51975 A

  The above problem will be described from another viewpoint. In recent years, in a system that shares the frequency band used for communications via ground facilities and communications via satellites, in the normal state, most of the frequency bands used are allocated to communications via ground facilities, and via satellites. It is desired to put into practical use a system that uses only a certain frequency band at sea and in mountainous areas, etc., and maintains the service by increasing the ratio of the band used for communication via satellite when an abnormal situation such as a disaster occurs. Yes. In such a system, it is necessary for the satellite channelizer to always extract the effective frequency (channel) in response to changes in the frequency usage status of each beam of the user link to effectively use the frequency of the feeder link. For this reason, it is required to ensure the flexibility of frequency arrangement and to improve the frequency utilization efficiency.

  Therefore, a satellite-mounted channelizer used in such a system can demultiplex an input signal in which multi-channel signals are frequency-multiplexed into various subchannels among various channelizer processing methods to obtain a desired subchannel. Select a channel and frequency-shift the sub-channels for the required bandwidth so that they have frequency characteristics that are alternately arranged so that the transition bands of each sub-channel overlap and the pass bands do not overlap, A method of combining and generating a channel signal with a desired bandwidth (such as a band combining polyphase FFT method) is suitable in terms of “small amount of calculation”, “flexibility”, and “frequency utilization efficiency”.

  However, this type of channelizer only presents means for outputting at the same sampling rate as the sampling rate (frequency bandwidth) of the input signal. For this reason, this type of channelizer can rearrange the channels of the input signal on which the multi-channel signal is frequency-multiplexed on the frequency axis and output it with the same bandwidth as the input signal. In addition, a signal of a specific channel such as a desired channel cannot be extracted with the bandwidth of the channel. This type of channelizer also cannot output at a sampling rate different from the sampling rate of the input signal.

  Also, in the above channelizer, when the sub-channels that are alternately arranged so that the transition bands do not overlap and the pass bands do not overlap are combined, the signals must be matched to the phase characteristics of both sub-channels. Since quality deteriorates, it is necessary to match the phase characteristics of both subchannels. However, when outputting at a sampling rate different from the sampling rate of the input signal, the value of the impulse response length in the actual device configuration is substituted into the impulse response length term of the filter coefficient calculation formula when calculating the filter coefficient. If the filter coefficient obtained by the normal calculation method is used, the phase characteristics of both subchannels do not match.

  In view of the problems as described above, the present invention intends to provide a method for outputting at a sampling rate different from the sampling rate of an input signal in the above-described channelizer.

  The present invention also provides that when output is performed at a sampling rate different from the sampling rate of the input signal, both sub-channels are synthesized at the time of synthesizing sub-channels that are alternately arranged so that the transition bands overlap and the pass bands do not overlap. It is an object of the present invention to provide a filter coefficient calculation method capable of matching channel phase characteristics and a channelizer to which the filter coefficient calculation method is applied.

  The present invention relates to a frequency-multiplexed signal processing technique used in the communication field.

  According to the first aspect of the present invention, there is provided a channelizer that extracts a channel signal having a desired bandwidth from an input signal in which multi-channel signals are frequency-multiplexed, and includes N input signals defined by a sampling rate Fs. To the first and second systems of demultiplexing means parallel to the input signal and to be output at the sampling rate of Fs / N, and to the first and second systems of demultiplexing means. The first and second systems are provided correspondingly and selectively output a desired subchannel from the subchannels output by the first and second branching means or output 0 (null) data. M subchannels out of the subchannels provided by the switch means and the first and second system switch means and outputted by the first and second system switch means, respectively. Are combined so as to have frequency characteristics that are alternately arranged so that the transition bands of the subchannels overlap and the passbands do not overlap, and output at a sampling rate M × Fs / N different from the sampling rate Fs, A plurality of combinations for adding and combining a plurality of sets of first and second systems of combining means and a combination signal output from each of the first and second systems of combining means corresponding to each other. Means for extracting a signal of a specific channel from the input signal with a bandwidth of the channel.

  According to the second aspect of the present invention, an input signal in which a multi-channel signal is frequency-multiplexed is demultiplexed into N subchannels, a desired subchannel is selected, and a bandwidth corresponding to a necessary bandwidth is selected. A signal that is frequency-shifted so as to have frequency characteristics that are alternately arranged so that passbands do not overlap with each other because the transition areas of the respective subchannels overlap, and a signal that generates a channel signal with a desired bandwidth A processing method is provided.

  In the present signal processing method, the input signals defined by the sampling rate Fs are demultiplexed into N subchannels and output at a sampling rate of Fs / N, and first and second demultiplexing processes; Corresponding to the demultiplexing processes of the first and second systems, a desired subchannel is selectively output from the subchannels output in the demultiplexing processes of the first and second systems, or 0 (null) data M sub-channels corresponding to the first and second system switch processes and the first and second system switch processes and output in each of the first and second system switch processes. The sub-channels of the sub-channels are combined so as to have frequency characteristics that are alternately arranged so that the transition bands of the respective sub-channels overlap and the pass bands do not overlap, and sampling is different from the sampling rate Fs. A combination of a plurality of first and second systems combined with each other and a plurality of mutually combined combining processes of the first and second systems. A plurality of combining processes for adding and combining wave signals, and extracting a signal of a specific channel from the input signal with a bandwidth of the channel.

  According to the present invention, it is possible to extract a signal of a specific channel with the bandwidth of the channel without degrading the signal quality from an input signal in which multi-channel signals are frequency-multiplexed. Can demodulate the modulated signal of the extracted channel as it is. On the other hand, in the case of the transmission channelizer, when the channel of the input signal is distributed to a plurality of beams and transmitted, only the necessary channels are extracted and assigned to each transmission beam, thereby improving the frequency utilization efficiency.

It is the figure which showed the structure of the channelizer by the Example of this invention. FIG. 3 is a block diagram showing a configuration of the first system branching circuit 111 shown in FIG. 1 when the tap number K is an odd number. It is a block diagram which shows the structure in case the tap number K is an even number of the 1st system branching circuit 111 shown by FIG. It is the figure which showed the frequency band of each subchannel which the 1st system branching circuit 111 shown by FIG. 1 extracts from all the bands of an input signal. It is the figure which showed the frequency characteristic of each subchannel which the 1st system branch circuit 111 shown by FIG. 1 outputs. FIG. 2 is a block diagram illustrating a configuration of a second system branching circuit 121 illustrated in FIG. 1. It is the figure which showed the frequency band of each subchannel which the 2nd system branch circuit 121 shown by FIG. 1 extracts from all the bands of an input signal. It is the figure which showed the frequency characteristic of each subchannel which the 2nd system branch circuit 121 shown by FIG. 1 outputs. It is a block diagram which shows a structure in case the tap number K of the 1st system integrated wave circuit 113_L shown by FIG. 1 is an odd number. It is a block diagram which shows a structure in case the tap number K of the 1st system integrated wave circuit 113_L shown by FIG. 1 is an even number. FIGS. (A), (b), and (c) are diagrams showing the frequency characteristics of the combined signals output from the first system integrated wave circuits 113_1, 113_2, and 113_L shown in FIG. 1, respectively. FIG. 2 is a block diagram showing a configuration of a second system integrated wave circuit 123_L shown in FIG. 1. FIGS. 9A, 9B, and 9C are diagrams showing the frequency characteristics of the combined signals output from the second system integrated wave circuits 123_1, 123_2, and 123_L shown in FIG. 1, respectively. It is the characteristic figure which calculated | required the frequency characteristic (amplitude characteristic and phase characteristic) of filter 1 output and filter 2 output by simulation. It is the characteristic figure which calculated | required the frequency characteristic (amplitude characteristic and phase characteristic) of the filter 1 output and the filter 2 output by the simulation at the time of using the filter coefficient calculated | required with the calculation method of this invention. 6 is a characteristic diagram obtained by simulation of the phase characteristics of the filter 1 output when the initial phase = 0 in the number of taps (K) = 1, 2, 3, 4,. 6 is a characteristic diagram obtained by simulation of the phase characteristics of the output of the filter 1 when the initial phase = π in the number of taps (K) = 1, 2, 3, 4,. 6 is a special drawing in which the phase characteristics of the output of the filter 2 when the initial phase is π in the number of taps (K) = 1, 2, 3, 4,. It is the figure which showed the frequency characteristic of the channel signal 1 which the synthetic | combination circuit 14_1 outputs in the number M of multiplexed subchannel signals = 2. It is the figure which showed the frequency characteristic of the channel signal 2 which the synthetic | combination circuit 14_2 outputs in the number M of multiplexing subchannel signals = 4. It is the figure which showed the frequency characteristic of the channel signal L which the synthetic | combination circuit 14_L outputs in the number M of multiplexing subchannel signals. FIG. 4 is a diagram illustrating characteristics of filter coefficients used in the multiplier circuits 22_1_21 to 22_1_2K illustrated in FIG. 2 and the multiplier circuits 32_1_21 to 32_1_2K illustrated in FIG. FIG. 11 is a diagram illustrating characteristics of filter coefficients used in the multiplication circuits 93_1_21 to 93_N_2K illustrated in FIG. 9 and the multiplication circuits 10_3_1_21 to 10_3_N_2K illustrated in FIG. It is the figure which displayed the filter coefficient by the graph which uses a tap as a horizontal axis. It is the figure which displayed the filter coefficient by the graph which uses a tap as a horizontal axis. It is the figure which displayed the filter coefficient by the graph which uses a tap as a horizontal axis. It is the figure which showed the structure of the filtering circuit shown by patent document 1. FIG. FIG. 28 is a diagram showing amplitude characteristics of a specific channel signal extracted with a bandwidth Fs in the filtering circuit shown in FIG. 27. It is the figure which showed the structure of the filtering circuit shown by patent document 2. FIG. FIG. 30 is a diagram illustrating an input signal, frequency characteristics of first and second digital filter banks, and a synthesized signal that is an output signal in the filtering circuit illustrated in FIG. 29.

[Example]
(Constitution)
FIG. 1 is a diagram showing a channelizer as an embodiment of the present invention.

In FIG. 1, reference numeral 111 indicates that an input signal defined by the sampling rate Fs is demultiplexed into N (N is a positive integer) subchannels of X _{10 to} X _{1 (N-1)} , and Fs / N sampling is performed. first system branching circuit for outputting a rate (branching means in the first line), _{112, X 10 ~X 1 (N-} 1) X 110 any subchannel from the N sub-channel signals to X The first system switch circuit (the first system switch means) 113_1 to 113_L that selectively outputs from a desired terminal of _{1L (M-1)} (L and M are positive integers) 113_1 to 113_L have the required bandwidth. 1st system integrated wave circuit which combines M subchannels selected and output by 1 system switch circuit 112 and outputs at a sampling rate (M × Fs / N) different from the sampling rate (Fs) of the input signal (First system multiplexing means). For example, 113_1 is the first system 2-multiplex circuit, 113_2 is the first system 4-multiplex circuit,..., 113_L is the first system M-multiplex circuit.

Reference numeral 121 denotes a second system demultiplexing circuit (second system demultiplexing means ₎ that demultiplexes the input signal into N subchannels X _{20 to} X _{2 (N-1)} and outputs the demultiplexed signal at an Fs / N sampling rate. ), 122, X ₂₀ to X _{2 (desired} terminal with selecting outputs from the desired terminal of the _N-1) of N X ₂₁₀ any subchannels from subchannel signal ~X _{2L (M-1)} The second system switch circuit (second system switch means) 123_1 to 123_L that outputs 0 (null data) from 1 to 123 is selected by the second system switch circuit 122 so as to have the necessary bandwidth. A second system integrated wave circuit (second system combining means) that combines channels and outputs at a sampling rate (M × Fs / N) different from the sampling rate (Fs) of the input signal. For example, 123_1 is a second multiplexing circuit, 123_2 is a second four multiplexing circuit, and 123_L is a second M multiplexing circuit.

  14_1 to 14_L respectively synthesize the first system integrated wave signal and the second system integrated wave signal combined into the necessary bandwidths to obtain a desired channel signal (combined output channel 1 (band: 2 × Fs / N) to This is a synthesis circuit (synthesizing means) that generates a synthesis output channel L (band: M × Fs / N)).

FIG. 2 is a block diagram showing in detail the configuration when the tap number K of the first system branching circuit 111 is an odd number. In FIG. 2, 21_1 to 21_ (N-1) are (N-1) delay circuits for delaying by one clock at the sampling frequency (Fs) of the input signal. Reference numerals 22_1 to 22_N denote sub-filters H _{0,1 to} H _{N-1,1 corresponding} to the number of sub-channels. The signals delayed by the delay circuits 21_ (N-1) to 21_1 are sequentially input to the sub-filters 22_ (N-1) (not shown) to 22_1. In the sub-filters H _0,1 22_1, 22_1_1 to 22_1_1 (K-1) are delay circuits that delay by one clock at a frequency of (Fs / N), and 22_1_21 to 22_1_2K are signals and filter coefficients for each tap. Multiplication circuits for multiplying (h _{0 to} h _{(K−1) N} ), and 22_1_32 to 22_1_3K are addition circuits for adding the outputs of the respective taps.

Similarly, in the sub-filters H _{N-1, 1} 22_N, 22_N — 11 to 22_N — 1 (K−1) are delay circuits that delay by one clock at the frequency (Fs / N), and 22_N — 21 to 22_N — 2K are signals for each tap. And 22_N_32 to 22_N_3K are adder circuits for adding the outputs of the taps, respectively, and a multiplication circuit for multiplying the filter coefficients (h _{N-1 to} h _KN-1 ).

  The filter coefficients used in the multiplication circuits 22_1_21 to 22_N_2K are calculated by calculating the impulse response length as NK + 1 instead of the actual impulse response length NK, and then calculating NK + 1 of h (0) to h (NK) calculated. Among the values, NK pieces of h (0) to h (NK-1) are used, and the sign is inverted at the even-numbered taps.

Specifically, the filter coefficients used in the multiplication circuits 22_1_21 to 22_1_2K are as follows.
22_1_21: h ₀
22_1_22: -h _N
22_1_23: h _2N
22_1_24: -h _3N
22_1_25: h _4N
:
22_1_2K: h _{(K-1) N}

Similarly, the filter coefficients used in the multiplication circuits 22_N_21 to 22_N_2K are as follows.
22_N_21: h _N-1
22_N_22: -h _2N-1
22_N_23: h _3N-1
22_N_24: -h _4N-1
22_N_25: h _5N-1
:
22_N_2K: h _KN-1

In FIG. 2, 23_1 to 23_N are multiplication circuits that multiply the outputs of the sub-filters 22_1 to 22_N by coefficients W- ⁰ to W- ^{(N-1) / 2} , and 24 is a Fourier transform of the outputs of the multiplication circuits 23_1 to 23_N. , An FFT circuit that outputs signals X _{10 to} X _{1 (N-1)} of each subchannel of the first system.

FIG. 3 is a block diagram showing in detail the configuration when the number of taps K of the first system branching circuit 111 is an even number. In FIG. 3, 31_1 to 31_ (N-1) are (N-1) delay circuits for delaying by one clock at the sampling frequency (Fs) of the input signal. Reference numerals 32_1 to 32_N denote sub-filters H _{0,1 to} H _N-1,1, which are equivalent to the number of sub-channels. The signals delayed by the delay circuits 31_ (N-1) to 31_1 are sequentially input to the sub-filters 32_ (N-1) (not shown) to 32_1. In the sub-filters H _0,1 32_1, 32_1_11 to 32_1_1 (K-1) are delay circuits that delay by one clock at the frequency of Fs / N, and 32_1_21 to 32_1_2K are signals and filter coefficients (-h ₀ for each tap). ˜h _{(K−1) N} ) are multiplication circuits, and 32_1_32 to 32_1_3K are addition circuits for adding the outputs of the respective taps.

Similarly, in the sub-filters H _{N-1 and 1} 32_N, 32_N_11 to 32_N_1 (K-1) is a delay circuit that delays by one clock at the frequency of Fs / N, and 32_N_21 to 32_N_2K is a signal and a filter for each tap. Multiplication circuits for multiplying coefficients (-h _{N-1 to} h _KN-1 ) and 32_N_32 to 32_N_3K are addition circuits for adding the outputs of the respective taps.

  The filter coefficients used in the multipliers 32_1_21 to 32_N_2K are calculated as NK + 1 instead of the actual impulse response length NK instead of the actual impulse response length NK, and NK + 1 of the calculated h (0) to h (NK). Among the values, NK pieces of h (0) to h (NK-1) are used, and the sign is inverted at an odd-numbered tap.

Specifically, the filter coefficients used in the multiplication circuits 32_1_21 to 32_1_2K are as follows.
32_1_21: -h ₀
32_1_22: h _N
32_1_23: -h _2N
32_1_24: h _3N
32_1_25: -h _4N
:
32_1_2K: h _{(K-1) N}

Similarly, filter coefficients used in the multiplier circuits 32_N — 21 to 32 — N — 2K are as follows.
32_N_21: -h _N-1
32_N_22: h _2N-1
32_N_23: -h _3N-1
32_N_24: h _4N-1
32_N_25: -h _5N-1
:
32_N_2K: h _KN-1

In FIG. 3, 33_1 to 33_N are multiplication circuits for multiplying the outputs of the sub-filters 32_1 to 32_N by coefficients W- ⁰ to W- ^{(N-1) / 2} , and 34 is a Fourier transform of the outputs of the multiplication circuits 33_1 to 33_N. , An FFT circuit that outputs signals X _{10 to} X _{1 (N-1)} of each subchannel of the first system.

FIG. 6 is a block diagram showing in detail the configuration of the second system branching circuit 121 shown in FIG. In FIG. 6, reference numerals 61_1 to 61_N denote (N-1) delay circuits that delay the input signal sampling frequency (Fs) by one clock at a time. Reference numerals 62_1 to 62_N denote sub-filters H _{0,2 to} H _{N-1,2 corresponding} to the number of sub-channels. The signals delayed by the delay circuits 61_ (N-1) to 61_1 are sequentially input to the sub-filters 62_ (N-1) (not shown) to 62_1. In the sub-filter H _0,2 62_1, 62_1_1 to 62_1_1 (K-1) is a delay circuit that delays by one clock at the frequency of Fs / N, and 62_1_21 to 62_1_2K are signals and filter coefficients (h _{0 to} h _{( K-1)} Multiplication circuits for multiplying _N ), and 62_1_32 to 62_1_3K are addition circuits for adding the outputs of the taps.

Similarly, in the sub-filter H _N-1,2 62_N, 62_N — 11 to 62_N — 1 (K−1) is a delay circuit that delays by one clock at the frequency of Fs / N, and 62_N — 21 to 62_N — 2K is a signal and filter coefficient (for each tap) h _{N-1 to} h _KN-1 ) are multiplying circuits, and 62_N_32 to 62_N_3K are adding circuits for adding the outputs of the taps.

  Note that the filter coefficients used in the multiplication circuits 62_1_21 to 62_N_2K are calculated by calculating the impulse response length as NK + 1 instead of the actual impulse response length NK, and then calculating NK + 1 of h (0) to h (NK) calculated. Among the values, NK pieces of h (0) to h (NK-1) are used.

Specifically, the filter coefficients used in the multiplication circuits 62_1_21 to 62_1_2K are as follows.
62_1_21: h ₀
62_1_22: h _N
62_1_23: h _2N
62_1_24: h _3N
62_1_25: h _4N
:
62_1_2K: h _{(K-1) N}

Similarly, filter coefficients used in the multiplication circuits 62_N — 21 to 62_N — 2K are as follows.
62_N_21: h _N-1
62_N_22: h _2N-1
62_N_23: h _3N-1
62_N_24: h _4N-1
62_N_25: h _5N-1
:
62_N_2K: h _KN-1

In FIG. 6, reference numeral 63 denotes an FFT circuit that Fourier-transforms the outputs of the sub-filters 62_1 to 62_N and outputs the second sub-channels X _{20 to} X _{2 (N-1)} .

  FIG. 9 is a block diagram showing in detail the configuration when the number of taps K of the first system integrated wave circuit 113_L shown in FIG. 1 is an odd number. The first system integrated wave circuits 113_1 and 113_2 correspond to cases where the number M of subchannels to be combined in FIG.

In FIG. 9, subchannel signals X _{1L0 to} X _{1L (M−1) corresponding} to a desired band of the first system are input. M is the number of subchannels to be combined.

In FIG. 9, 91 is an IFFT (Inverse Fast Fourier Transform) circuit for performing inverse Fourier transform on inputs of desired subchannel signals _{X1L0 to X1L (M-1)} of the first system, 92_1 to 92_M Is a multiplication circuit that multiplies the coefficients W ^{0 to} W ^{(M−1) / 2} for each subchannel output of the IFFT circuit 91. Reference numerals 93_1 to 93_M denote sub-filters G _{0,1 to} G _M-1,1, which are as many as the number of sub-channels to be combined. In the sub-filters G _0,1 93_1, 93_1_11 to 93_1_1 (K-1) are delay circuits for delaying one clock at a frequency of M × (Fs / N), and 93_1_21 to 93_1_2K are signals and filter coefficients (g _{M-1 to} g _MK-1 ) are multiplying circuits, and 93_1_32 to 93_1_3K are adding circuits for adding the outputs of the taps.

Similarly, in the sub-filters G _{M- 1 and 1} 93_M, 93_M_11 to 93_M_1 (K-1) are delay circuits that delay one clock at a frequency of M × (Fs / N), and 93_M_21 to 93_M_2K are signals for each tap. a filter coefficient _{(g 0 ~g (K-1} ) M) for multiplying the multiplication circuit, 93_M_32～93_M_3K is adder circuit for adding the outputs of the taps.

  Note that the filter coefficients used in the multipliers 93_1_21 to 93_M_2K are calculated by calculating the impulse response length as MK-1 instead of the actual impulse response length MK, and the calculated MK of g (0) to g (MK-2). In addition to −1 value, g (MK−1) = 0 is set to MK coefficients from g (0) to g (MK−1), and the sign is inverted at even-numbered taps.

Specifically, the filter coefficients used in the multiplication circuits 93_1_21 to 93_1_2K are as follows.
93_1_21: g _M-1
93_1_22: -g _2M-1
93_1_23: g _3M-1
93_1_24: -g _4M-1
93_1_25: g _5M-1
:
93_1_2 (K-1): -g _{(K-1) M-1}
93_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 93_M_21 to 93_M_2K are as follows.
93_M_21: g ₀
93_M_22: -g _M
93_M_23: g _2M
93_M_24: -g _3M
93_M_25: g _4M
:
93_M_2 (K-1): -g _{(K-2) M}
93_M_2K: 0

In FIG. 9, 94_1 to 94_ (M−1) are (M−1) delay circuits for delaying by one clock at the sampling frequency (M × Fs / N) of the output signal. Accordingly, the first system integrated wave circuit 113_L outputs an output signal Y _1L obtained by combining the outputs of the sub-filters 93_1 to 93_M.

  FIG. 10 is a block diagram showing in detail the configuration when the number of taps K of the first system integrated wave circuit 113_L shown in FIG. 1 is an even number. The first system integrated wave circuits 113_1 and 113_2 correspond to the case where the number M of subchannels to be combined in FIG.

In FIG. 10, subchannel signals X _{1L0 to} X _{1L (M−1)} for a desired band of the first system are input. M is the number of subchannels to be combined. In FIG. 10, 10_1 is an IFFT circuit that performs inverse Fourier transform on inputs of signals _{X1L0 to X1L (M-1)} of a desired first subchannel of the first system, and 10_2_1 to 10_2_M is a coefficient for each subchannel output of the IFFT circuit 10_1. This is a multiplication circuit for multiplying W ^{0 to} W ^{(M−1) / 2} . 10_3_1 to 10_3_M are sub-filters G _{0,1 to} G _M−1,1 , and there are as many as the number of sub-channels to be combined. In the sub-filters G _0,1 10_3_1, 10_3_1_11 to 10_3_1_1 (K-1) is a delay circuit that delays one clock at a frequency of M × Fs / N, 10_3_1_21 to 10_3_1_2K is a signal and a filter coefficient (−g _{M -1 to} g _MK-1 ) are multiplication circuits, 10_3_1_32 to 10_3_1_3K are addition circuits for adding the outputs of the taps.

Similarly, in the sub-filter G _M-1,1 10_3_M, 10_3_M_11 to 10_3_M_1 (K-1) is a delay circuit that delays one clock at a frequency of M × Fs / N, and 10_3_M_21 to 10_3_M_2K is a signal and a filter for each tap. coefficient _{(-g 0 ~g (K-1} ) M) multiplier circuits for multiplying, 10_3_M_32～10_3_M_3K is adder circuit for adding the outputs of the taps.

  The filter coefficients used in the multiplication circuits 10_3_1_21 to 10_3_M_2K are calculated by calculating the impulse response length as MK-1 instead of the actual impulse response length MK, and calculating MK of g (0) to g (MK-2). In addition to −1 value, g (MK−1) = 0 is set to MK coefficients from g (0) to g (MK−1), and the sign is inverted at odd-numbered taps.

Specifically, the filter coefficients used in the multiplication circuits 10_3_1_21 to 10_3_1_2K are as follows.
10_3_1_21: -g _M-1
10_3_1_22: g _2M-1
10_3_1_23: -g _3M-1
10_3_1_24: g _4M-1
10_3_1_25: -g _5M-1
:
10_3_1_2 (K-1): -g _{(K-1) M-1}
10_3_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 10_3_M_21 to 10_3_M_2K are as follows.
10_3_M_21: -g ₀
10_3_M_22: g _M
10_3_M_23: -g _2M
10_3_M_24: g _3M
10_3_M_25: -g _4M
:
10_3_M_2 (K-1): -g _{(K-2) M}
10_3_M_2K: 0

In FIG. 10, 10_4_1 to 10_4_ (M-1) are (M-1) delay circuits which are delayed by one clock at the sampling frequency (M × Fs / N) of the output signal. Accordingly, the first system integrated wave circuit 113_L outputs an output signal Y _1L obtained by combining the outputs of the sub-filters 10_3_1 to 10_3_M.

  FIG. 12 is a block diagram showing in detail the configuration of the second system integrated wave circuit 123_L shown in FIG. The second system integrated wave circuits 123_1 and 123_2 correspond to cases where the number M of subchannels to be combined in FIG.

In FIG. 12, sub-channel signals X _{2L0 to} X _{2L (M-1)} for a desired band of the second system are input. M is the number of subchannels to be combined. In FIG. 12, reference _{numeral 12_1 denotes} an IFFT circuit that performs inverse Fourier transform on inputs of signals X _{2L0 to} X _{2L (M-1)} of desired subchannels of the second system. Reference numerals 12_2_1 to 12_2_M are sub-filters G _{0,2 to} G _M-1,2 and have the same number as sub-channels to be combined. In the sub-filter G _0,1 12_2_1, 12_2_1_1 to 12_2_1_1 (K-1) is a delay circuit that delays by one clock at a frequency of M × Fs / N, and 12_2_1_1 to 12_2_1_1K is a signal and a filter coefficient (g _{M− 1 to} g _MK-1 ), and 12_2_1_32 to 12_2_1_3K are adder circuits that add the outputs of the taps.

Similarly, in the sub-filter G _M-1,1 12_2_M, 12_2_M_11 to 12_2_M_1 (K-1) is a delay circuit that delays one clock at a frequency of M × Fs / N, and 12_2_M_21 to 12_2_M_2K is a signal and a filter for each tap. Multiplication circuits for multiplying coefficients (g _{0 to} g _{(K−1) M} ), and 12_2_M_32 to 12_2_M_3K are addition circuits for adding the outputs of the respective taps.

  Note that the filter coefficients used in the multipliers 12_2_1_21-12_2_M_2K are calculated as MK-1 instead of the actual impulse response length MK and the calculated MK of g (0) to g (MK-2). In addition to the -1 value, g (MK-1) = 0 and MK coefficients from g (0) to g (MK-1).

Specifically, the filter coefficients used in the multiplication circuits 12_2_1_21 to 12_2_1_2K are as follows.
12_2_1_21: g _M-1
12_2_1_22: g _2M-1
12_2_1_23: g _3M-1
12_2_1_24: g _4M-1
12_2_1_25: g _5M-1
:
12_2_1_2 (K-1): g _{(K-1) M-1}
12_2_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 12_2_M_21 to 12_2_M_2K are as follows.
12_2_M_21: g ₀
12_2_M_22: g _M
12_2_M_23: g _2M
12_2_M_24: g _3M
12_2_M_25: g _4M
:
12_2_M_2 (K-1): g _{(K-2) M}
12_2_M_2K: 0

In FIG. 12, 12_3_1 to 12_3_ (M-1) are (M-1) delay circuits that delay one clock at a time at the sampling frequency (M × Fs / N) of the output signal. Thus, the second system multiplexing circuit 123_L outputs an output signal _{Y 2L} which multiplexes the output of the sub-filter 12_2_1～12_2_M.

(Operation)
Next, the operation of the channelizer of FIG. 1 will be described. In Figure 1, the first line branching circuit 111 demultiplexes an input signal to the signal X ₁₀ to X ₁ of N subchannels _(N-1) sampling rate Fs, the output at a sampling rate of Fs / N To do.

  FIG. 4 is a diagram showing the frequency band of each subchannel extracted by the first system demultiplexing circuit 111 from the entire band of the input signal, and FIG. 5 shows each subchannel output by the first system demultiplexing circuit 111. It is the figure which showed the frequency characteristic.

The band of Cb ₁₀ to Cb _{1 (N-1)} in FIG. 4 is output from each subchannel output X _{10 to} X _{1 (N-1) of} the first system demultiplexing circuit 111 as a signal of the frequency characteristic of FIG. N baseband signals with a sampling frequency Fs / N are output.

  The first system branching circuit 111 will be described in detail.

  As described above, FIG. 2 is a block diagram showing in detail the configuration when the tap number K of the first system branching circuit 111 is an odd number.

In FIG. 2, the input signal is delayed by one clock at the sampling frequency (Fs) of the input signal by delay circuits 21_1 to 21_ (N-1), and sub-filters H _{0,1 to} H _N-1,1 22_1 to 22_N are repeatedly input in the order of H _N-1,1 , H _N-2,1 ,..., H _0,1 .

In the sub-filter H _0,1 22_1, the delay circuits 22_1_11 to 22_1_1 (K-1) are delayed by one clock at the frequency of Fs / N, and the multiplier circuits 22_1_21 to 22_1_2K have a signal and a filter coefficient (h ₀ to h _{(K-1) N} ) is multiplied, and the adder circuits 22_1_32 to 22_1_3K add the outputs of the respective taps.

Similarly, in the sub-filters H _N−1,1 22_N, the delay circuits 22_N — 11 to 22_N — 1 (K−1) are delayed by one clock at the frequency of Fs / N, and the multiplier circuits 22_N — 21 to 22_N — 2K The coefficients (h _{N-1 to} h _KN-1 ) are multiplied, and the adder circuits 22_N_32 to 22_N_3K add the outputs of the taps. The multiplication circuits 23_1 to 23_N multiply the coefficients W- ⁰ to W- ^{(N-1) / 2} for each output of the sub-filters 22_1 to 22_N. FFT circuit 24 the output of the multiplier circuit 23_1~23_N Fourier transform, and outputs a signal X ₁₀ to X ₁ of each sub-channel of the first system _(N-1). The operating frequency of the circuit after the sub-filter is Fs / N.

The processing of the first system demultiplexing circuit 111 is expressed by the following formula (1).

In Equation (1), N represents the number of demultiplexes (the number of subchannels), and H _{i, 1} (i = _{0 to N−1} ) represents the subfilters H _{0,1 to} H _N−1,1 22_1 to 22_N.

The FFT circuit 24 calculates the following formula (2) in the determinant (1).

The specifications of the filter coefficients used in the multiplier circuits 22_1-21 to 22_1_2K are as follows, and the characteristics are shown in FIG.
Normalized value: 1
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

  Further, the filter coefficients used in the multiplication circuits 22_1_21 to 22_N_2K are calculated by calculating the impulse response length as NK + 1 instead of the actual impulse response length NK, and then calculating NK + 1 of the calculated h (0) to h (NK). Among the values, NK pieces of h (0) to h (NK-1) are used, and the sign is inverted at the even-numbered taps.

Specifically, the filter coefficients used in the multiplication circuits 22_1_21 to 22_1_2K are as follows.
22_1_21: h ₀
22_1_22: -h _N
22_1_23: h _2N
22_1_24: -h _3N
22_1_25: h _4N
:
22_1_2K: h _{(K-1) N}

Similarly, filter coefficients used in the multiplication circuits 22_N — 21 to 22_N — 2K are as follows.
22_N_21: h _N-1
22_N_22: -h _2N-1
22_N_23: h _3N-1
22_N_24: -h _4N-1
22_N_25: h _5N-1
:
22_N_2K: h _KN-1

The sign of the filter coefficient in the sub-filters 22_1 to 22_N is inverted at the even-numbered taps, and the multiplication circuit 23_1 to 23_N multiplies the coefficients W ^{−0 to} W ^{− (N−1) / 2} by the first. As shown in FIG. 4, the system demultiplexing circuit 111 extracts a band of width Fs / N having a value shifted by Fs / 2N from Fs / N as a base frequency as a baseband signal as shown in FIG. .

  FIG. 3 is a block diagram showing in detail the configuration when the number of taps K of the first system branching circuit 111 is an even number.

In FIG. 3, an input signal is delayed by one clock at the sampling frequency (Fs) of the input signal by delay circuits 31_1 to 31_ (N-1), and sub-filters H _{0,1 to} H _N-1,1, 32_1 to 32_N are repeatedly input in the order of H _N-1,1 , H _N-2,1 ,..., H _0,1 .

Within the sub-filter H _0,1 32_1, the delay circuits 32_1_11 to 32_1_1 (K-1) are delayed by one clock at the frequency of Fs / N, and the multiplying circuits 32_1_21 to 32_1_2K have a signal and a filter coefficient (h ₀ to h _{(K-1) N} ) is multiplied, and the adder circuits 32_1_32 to 32_1_3K add the outputs of the respective taps.

Similarly, in the sub-filters H _N-1,1 32_N, the delay circuits 32_N_11-32_N_1 (K-1) are delayed by one clock at the frequency of Fs / N, and the multiplier circuits 32_N_21-32_N_2K are connected to the signal and filter for each tap. The coefficients (h _{N-1 to} h _KN-1 ) are multiplied, and the adder circuits 32_N_32 to 32_N_3K add the outputs of the taps.

The multipliers 33_1 to 33_N multiply the coefficients W- ⁰ to W- ^{(N-1) / 2} for each output of the sub-filters 32_1 to 32_N. FFT circuit 34 the output of the multiplier circuit 33_1~33_N Fourier transform, and outputs the signal X ₁₀ to X ₁ of each sub-channel of the first system the _(N-1). The operating frequency of the circuit after the sub-filter is Fs / N.

The processing of the first system demultiplexing circuit 111 is expressed by the following formula (3).

In Expression (3), N represents the number of demultiplexes (the number of subchannels), and H _{i, 1} (i = _{0 to N−1} ) represents the subfilters H _{0,1 to} H _N−1,1 32_1 to 32_N.

The FFT circuit 34 calculates the following formula (4) in the determinant (3).

The specifications of the filter coefficients used in the multiplication circuits 32_1_21 to 32_1_2K are as follows, and the characteristics are shown in FIG.
Normalized value: 1
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

  The filter coefficients used in the multipliers 32_1_21 to 32_N_2K are calculated as NK + 1 instead of the actual impulse response length NK instead of the actual impulse response length NK, and NK + 1 of the calculated h (0) to h (NK). Among the values, NK pieces of h (0) to h (NK-1) are used, and the sign is inverted at an odd-numbered tap.

Specifically, the filter coefficients used in the multiplier circuits 32_1_21 to 32_1_2K are as follows.
32_1_21: -h ₀
32_1_22: h _N
32_1_23: -h _2N
32_1_24: h _3N
32_1_25: -h _4N
:
32_1_2K: h _{(K-1) N}

Similarly, filter coefficients used in the multiplication circuits 32_N — 21 to 32 — N — 2K are as follows.
32_N_21: -h _N-1
32_N_22: h _2N-1
32_N_23: -h _3N-1
32_N_24: h _4N-1
32_N_25: -h _5N-1
:
32_N_2K: h _KN-1

The sign of the filter coefficient in the sub-filters 32_1 to 32_N is inverted at the odd-numbered taps, and the multiplication circuits 33_1 to 33_N multiply the coefficients W- ^{0 to} W- ^{(N-1) / 2} to obtain the first. As shown in FIG. 4, the system demultiplexing circuit 111 extracts a band of width Fs / N having a value shifted by Fs / 2N from Fs / N as a base frequency as a baseband signal as shown in FIG. .

The first system switch circuit 112 in FIG. 1 is a desired terminal of X _{110 to} X _{1L (M-1)} from _N subchannel signals X _{10 to} X _{1 (N-1).} Select output from.

The first system integrated wave circuits 113_1 to 113_L in FIG. 1 include subchannel signals _{X1L0 to X1L (M-1) corresponding to} a necessary band among the subchannel signals selected by the first system switch circuit 112. Are combined and output at a sampling frequency of M × Fs / N.

  FIGS. 11A, 11B, and 11C are diagrams illustrating frequency characteristics of the combined signals output from the first system integrated wave circuits 113_1, 113_2, and 113_L, respectively.

The subchannel signals having the frequency characteristics shown in FIG. 5 are input from X _{110 to} X _{1L (M−1) of} the first system integrated wave circuits 113_1, 113_2, and 113_L, and Y of the first system integrated wave circuits 113_1, 113_2, and 113_L. _{11 to} Y _1L are output as signals arranged on the frequency axis like C _{g10 to Cg1 (M-1)} in FIGS. 11 (a), 11 (b), and 11 (c).

  The operation of the first system integrated wave circuit 113_L will be described in detail.

  FIG. 9 is a block diagram showing in detail the configuration when the tap number K of the first system integrated wave circuit 113_L is an odd number.

  The first system integrated wave circuits 113_1 and 113_2 correspond to cases where the number M of subchannels to be combined in FIG.

In FIG. 9, subchannel signals X _{1L0 to} X _{1L (M−1) corresponding} to a desired band of the first system are input. M is the number of subchannels to be combined.

The IFFT circuit 91 performs inverse Fourier transform on the inputs of the desired subchannel signals X _{1L0 to} X _{1L (M−1)} of the first system. The multiplication circuits 92_1 to 92_M multiply the coefficients W ^{0 to} W ^{(M−1) / 2} for each subchannel output of the IFFT circuit 91.

Within the sub-filter G _0,1 93_1, the delay circuits 93_1_11 to 93_1_1 (K−1) are delayed by one clock at the frequency of M × Fs / N, and the multiplier circuits 93_1_21 to 93_1_2K _{M-1 to} g _MK-1 ), and the adder circuits 93_1_32 to 93_1_3K add the outputs of the respective taps.

Similarly, in the sub-filters G _{M-1, 1} 93_M, the delay circuits 93_M_11 to 93_M_1 (K−1) are delayed by one clock at the frequency of M × Fs / N, and the multiplication circuits 93_M_21 to 93_M_2K are signals for each tap. And the filter coefficient (g _{0 to} g _{(K−1) M} ), and the adder circuits 93_M_32 to 93_M_3K add the outputs of the taps.

The delay circuits 94_1 to 94_ (M−1) delay the output signal sampling frequency (M × Fs / N) by one clock at a time, and the combined output Y _1L is sub-filter G _{0,1 to} G _M−1,1. From 93_1 to 93_M, G _M-1,1 , G _M-2,1 ,..., G _0,1 are repeatedly output in this order.

The processing of the first system integrated wave circuit 113_L is expressed by the following formula (5).

In Expression (5), M represents the number of multiplexed signals (number of subchannels), and G _{i, 1} (i = 0 to M−1) represents the subfilters G _{0,1 to} G _M−1,1 93_1 to 93_M.

The IFFT circuit 91 performs arithmetic processing on the following formula (6) in the determinant (5).

The specifications of the filter coefficients used in the multiplier circuits 93_1_21 to 93_M_2K are as follows, and the characteristics are shown in FIG.
Normalized value: M
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

  In addition, the filter coefficients used in the multipliers 93_1_21 to 93_M_2K are calculated by calculating the impulse response length as MK-1 instead of the actual impulse response length MK, and the calculated MK of g (0) to g (MK-2) In addition to −1 value, g (MK−1) = 0 is set to MK coefficients from g (0) to g (MK−1), and the sign is inverted at even-numbered taps.

Specifically, the filter coefficients used in the multiplication circuits 93_1_21 to 93_1_2K are as follows.
93_1_21: g _M-1
93_1_22: -g _2M-1
93_1_23: g _3M-1
93_1_24: -g _4M-1
93_1_25: g _5M-1
:
93_1_2 (K-1): -g _{(K-1) M-1}
93_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 93_M_21 to 93_M_2K are as follows.
93_M_21: g ₀
93_M_22: -g _M
93_M_23: g _2M
93_M_24: -g _3M
93_M_25: g _4M
:
93_M_2 (K-1): -g _{(K-2) M}
93_M_2K: 0

The multiplication circuit 92_1 to 92_M multiplies the coefficients W ^{0 to} W ^{(M−1) / 2,} and the filter coefficients in the sub-filters 93_1 to 93_M are inverted at the even-numbered taps, thereby integrating the first system. The wave circuit 113_L has a band of width Fs / N in which each subchannel that is a baseband signal as shown in FIG. 5 has a center frequency as a value shifted by Fs / 2N from Fs / N as shown in FIG. Are arranged on the frequency axis.

  FIG. 10 is a block diagram showing in detail the configuration when the number of taps K of the first system integrated wave circuit 113_L is an even number. The first system integrated wave circuits 113_1 and 113_2 correspond to the case where the number M of subchannels to be combined in FIG.

In FIG. 10, subchannel signals X _{1L0 to} X _{1L (M−1)} for a desired band of the first system are input. M is the number of subchannels to be combined.

The IFFT circuit _{10_1 performs} inverse Fourier transform on the inputs of the desired subchannel signals _{X1L0 to X1L (M-1)} of the first system. Multiplication circuits 10_2_1 to 10_2_M multiply the coefficients W ^{0 to} W ^{(M−1) / 2} for each subchannel output of IFFT circuit 10_1. Within the sub-filter G _0,1 10_3_1, the delay circuits 10_3_1_11 to 10_3_1_1 (K-1) are delayed by one clock at a frequency of M × Fs / N, and the multipliers 10_3_1_21 to 10_3_1_2K are connected to the signal and filter coefficient (g _{M-1 to} g _MK-1 ), and the adder circuits 10_3_1_32 to 10_3_1_3K add the outputs of the respective taps.

Similarly, in the sub-filter G _M-1,1 10_3_M, the delay circuits 10_3_M_11 to 10_3_M_1 (K-1) are delayed by one clock at the frequency of M × Fs / N, and the multiplication circuits 10_3_M_21 to 10_3_M_2K are signals for each tap. And the filter coefficient (g _{0 to} g _{(K−1) M} ), and the adder circuits 10_3_M_32 to 10_3_M_3K add the outputs of the respective taps.

The delay circuits 10_4_1 to 10_4_ (M-1) delay the output signal sampling frequency (M × Fs / N) by one clock at a time, and the combined output Y _1L is sub-filter G _{0,1 to} G _M−1,1. From 10_3_1 to 10_3_M, G _M-1,1 , G _M-2,1 ,..., G _0,1 are repeatedly output in this order.

The processing of the first system integrated wave circuit 113_L is expressed by the following formula (7).

In Expression (7), M represents the number of multiplexed signals (number of subchannels), and G _{i, 1} (i = 0 to M−1) represents the subfilters G _{0,1 to} G _M−1,1 10_3_1 to 10_3_M.

The IFFT circuit 10_1 performs arithmetic processing on the following formula (8) in the determinant (7) described above.

The specifications of the filter coefficients used in the multiplier circuits 10_3_1_21 to 10_3_M_2K are as follows, and the characteristics are shown in FIG.
Normalized value: M
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

The filter coefficients used in the multipliers 10_3_1_10 to 10_3_1_2K are calculated by calculating the impulse response length as MK-1 instead of the actual impulse response length MK, and then calculating the MK of g (0) to g (MK-2) In addition to −1 value, g (MK−1) = 0 is set to MK coefficients from g (0) to g (MK−1), and the sign is inverted at odd-numbered taps. Specifically, the filter coefficients used in the multiplication circuits 10_3_1_21 to 10_3_1_2K are as follows.
10_3_1_21: -g _M-1
10_3_1_22: g _2M-1
10_3_1_23: -g _3M-1
10_3_1_24: g _4M-1
10_3_1_25: -g _5M-1
:
10_3_1_2 (K-1): -g _{(K-1) M-1}
10_3_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 10_3_M_21 to 10_3_M_2K are as follows.
10_3_M_21: -g ₀
10_3_M_22: g _M
10_3_M_23: -g _2M
10_3_M_24: g _3M
10_3_M_25: -g _4M
:
10_3_M_2 (K-1): -g _{(K-2) M}
10_3_M_2K: 0

The multipliers 10_2_1 to 10_2_M multiply the coefficients W ^{0 to} W ^{(M−1) / 2} , and invert the signs of the filter coefficients in the sub-filters 10_3_1 to 10_3_M at the odd-numbered taps. As a result, the first integrated wave circuit 113_L sets the value obtained by shifting each subchannel, which is a baseband signal as shown in FIG. 5, by Fs / 2N with respect to Fs / N as shown in FIG. Is arranged on the frequency axis as a band of width Fs / N.

1 splits the input signal into N subchannel signals X _{20 to} X _{2 (N−1)} , and outputs them at a sampling rate of Fs / N.

  FIG. 7 is a diagram showing the frequency band of each subchannel extracted by the second system branching circuit 121 from the entire band of the input signal, and FIG. 8 is the frequency of each subchannel output by the second system branching circuit 121. It is the figure which showed the characteristic.

The band of Cb ₂₀ to Cb _{2 (N-1)} in FIG. 7 is output from each subchannel output X _{20 to} X _{2 (N-1) of} the second system demultiplexing circuit 121 as a signal of the frequency characteristic of FIG. N baseband signals with a sampling frequency Fs / N are output.

  The second system branch circuit 121 will be described in detail.

FIG. 6 is a block diagram showing in detail the configuration of the second system branching circuit 121. In FIG. 6, an input signal is delayed by one clock at a sampling frequency (Fs) of the input signal by delay circuits 61_1 to 61_ (N-1), and sub-filters H _{0,2 to} H _{N-1,2 are provided.} H _N-1,2 , H _N-2,2 ,..., H _0,2 are repeatedly input to 62_1 to 62_N.

In the sub-filter H _0,2 62_1, the delay circuits 62_1_11 to 62_1_1 (K-1) are delayed by one clock at the frequency of Fs / N, and the multiplier circuits 62_1_21 to 62_1_2K each have a signal and a filter coefficient (h ₀ to h _{(K-1) N} ) is multiplied, and the adder circuits 62_1_32 to 62_1_3K add the outputs of the respective taps.

Similarly, in the sub-filter H _N−1,2 62_N, the delay circuits 62_N — 11 to 62_N_1 (K−1) are delayed by one clock at the frequency of Fs / N, and the multiplying circuits 62_N — 21 to 62_N — 2K The coefficients (h _{N-1 to} h _KN-1 ) are multiplied, and the adder circuits 62_N_32 to 62_N_3K add the outputs of the taps.

The FFT circuit 63 Fourier-transforms the outputs of the sub-filters 62_1 to 62_N, and outputs signals X _{20 to} X _{2 (N-1)} of each sub-channel of the second system. The operating frequency of the circuit after the sub-filter is Fs / N.

The processing of the second system branching circuit 121 is expressed by the following formula (9).

In Equation (9), N is the number of demultiplexes (number of subchannels) H _{i, 2} (i = _{0 to N−} 1) represents the sub filters H _{0,2 to} H _N−1,2 62_1 to 62_N.

The FFT circuit 63 calculates the following formula (10) in the determinant (9) described above.

The specifications of the filter coefficients used in the multiplication circuits 62_1_21 to 62_N_2K are as follows, and the characteristics are shown in FIG.
Normalized value: 1
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

Further, the filter coefficients used in the multiplication circuits 62_1_21 to 62_N_2K are calculated as NK + 1 instead of the actual impulse response length NK instead of the actual impulse response length NK, and then NK + 1 of the calculated h (0) to h (NK). Among the values, NK pieces of h (0) to h (NK-1) are used. Specifically, the filter coefficients used in the multiplication circuits 62_1_21 to 62_1_2K are as follows.
62_1_21: h ₀
62_1_22: h _N
62_1_23: h _2N
62_1_24: h _3N
62_1_25: h _4N
:
62_1_2K: h _{(K-1) N}

Similarly, filter coefficients used in the multiplication circuits 62_N — 21 to 62_N — 2K are as follows.
62_N_21: h _N-1
62_N_22: h _2N-1
62_N_23: h _3N-1
62_N_24: h _4N-1
62_N_25: h _5N-1
:
62_N_2K: h _KN-1

Unlike the first system demultiplexing circuit 111, the second system demultiplexing circuit 121 performs sign inversion of the filter coefficients in the sub-filters 62_1 to 62_N and multiplication of the coefficients W- ^{0 to} W- ^{(N-1) / 2} . Not performed. As a result, as shown in FIG. 7, a band having a width Fs / N having a center frequency of Fs / N is extracted as a baseband signal as shown in FIG.

The second system switch circuit 122 shown in FIG. 1 is a desired terminal of X _{210 to} X _{2L (M-1)} from _N subchannel signals X _{20 to} X _{2 (N-1).} From the terminals X ₂₁₁ , X ₂₂₂ ..., X _{2L (M / 2)} corresponding to the subchannel at the frequency position that is the boundary between the extracted channel and the adjacent channel, 0 (null data) Output.

The second system integrated wave circuits 123_1 to 123_L in FIG. 1 are subchannel signals X _{2L0 to} X _{2L (M-1) corresponding to} a necessary band among the subchannel signals selected by the second system switch circuit 122. Are combined and output at a sampling frequency of M × Fs / N.

  FIGS. 13A, 13B, and 13C are diagrams illustrating frequency characteristics of the combined signals output from the second system integrated wave circuits 123_1, 123_2, and 123_L, respectively.

8 are input from X _{210 to} X _{2L (M-1) of} the second system integrated wave circuits 123_1, 123_2, and 123_L, and the Y of the second system integrated wave circuits 123_1, 123_2, and 123_L. _{21 to} Y _2L are output as signals arranged on the frequency axis as C _{g20 to} C _{g2 (M-1)} in FIGS. 13A, 13B, and 13C. In addition, since 0 (null data) is input to the subchannel signals X ₂₁₁ , X ₂₂₂ ,..., X _{2L (M / 2)} at the frequency position that is the boundary between the extracted channel and the adjacent channel, Figure 13 C _g21 of _(a), C _g22 of FIG. 13 _(b), the frequency position of the C _{g2 (M / 2)} of FIG. 13 (c) the amplitude level 0.

  The second system integrated wave circuit 123_L will be described in detail.

  FIG. 12 is a block diagram showing in detail the configuration of the second system integrated wave circuit 123-L. The second system integrated wave circuits 123_1 and 123_2 correspond to the case where the number M of subchannels to be combined in FIG.

In FIG. 12, sub-channel signals X _{2L0 to} X _{2L (M-1)} for a desired band of the second system are input. M is the number of subchannels to be combined.

The IFFT circuit _{12_1 performs} inverse Fourier transform on the inputs of the desired subchannel signals _{X2L0 to X2L (M-1)} of the second system.

Within the sub-filter G _0,2 12_2_1, the delay circuits 12_2_1_1 to 12_2_1_1 (K−1) are delayed by one clock at a frequency of M × Fs / N, and the multiplying circuits 12_2_1_21 to 12_2_1_2K each have a signal and a filter coefficient (g _{M-1 to} g _MK-1 ), and the adder circuits 12_2_1_32 to 12_2_1_3K add the outputs of the respective taps.

Similarly, in the sub-filter G _M-1,2 12_2_M, the delay circuits 12_2_M_11 to 12_2_M_1 (K-1) are delayed by one clock at a frequency of M × Fs / N, and the multiplication circuits 12_2_M_21 to 12_2_M_2K are signals for each tap. And the filter coefficient (g _{0 to} g _{(K−1) M} ), and the adder circuits 12_2_M_32 to 12_2_M_3K add the outputs of the respective taps.

The delay circuits 12_3_1 to 12_3_ (M−1) delay the output signal sampling frequency (M × Fs / N) by one clock at a time, and the combined output Y _2L is sub-filter G _{0,2 to} G _M−1,2. From 12_2_1 to 12_2_M, G _M-1,2 , G _M-2,2 ,..., G _0,2 are repeatedly output in this order.

The processing of the second system integrated wave circuit 123_L is expressed by the following formula (11).

In Expression (11), M represents the number of multiplexed signals (number of subchannels), and G _{i, 1} (i = 0 to M−1) represents the subfilters G _{0,1 to} G _M−1,1 12_2_1 to 12_2_M.

The IFFT circuit 12_1 performs arithmetic processing on the following equation (12) in the determinant (11).

The specifications of the filter coefficients used in the multiplier circuits 12_2_1_21 to 12_2_M_2K are as follows, and their characteristics are shown in FIG.
Normalized value: M
Passband _{f pass: -Fs / 4N <f} pass <Fs / 4N
Gain: 1 / √2 (when frequency f = ± Fs / 4N)
Stop band f _stop : f _stop <−Fs / 4N, Fs / 4N <f _stop

The filter coefficients used in the multipliers 12_2_1_21 to 12_2_M_2K are calculated by calculating the impulse response length as MK-1 instead of the actual impulse response length MK, and then calculating the MK values of g (0) to g (MK-2). In addition to the -1 value, g (MK-1) = 0 and MK coefficients from g (0) to g (MK-1). Specifically, the filter coefficients used in the multiplication circuits 12_2_1_21 to 12_2_1_2K are as follows.
12_2_1_21: g _M-1
12_2_1_22: g _2M-1
12_2_1_23: g _3M-1
12_2_1_24: g _4M-1
12_2_1_25: g _5M-1
:
12_2_1_2 (K-1): g _{(K-1) M-1}
12_2_1_2K: 0

Similarly, filter coefficients used in the multiplication circuits 12_2_M_21 to 12_2_M_2K are as follows.
12_2_M_21: g ₀
12_2_M_22: g _M
12_2_M_23: g _2M
12_2_M_24: g _3M
12_2_M_25: g _4M
:
12_2_M_2 (K-1): g _{(K-2) M}
12_2_M_2K: 0

Unlike the first system integrated wave circuit 113_L, the second system integrated wave circuit 123_L does not perform multiplication of coefficients W ^{0 to} W ^{(M−1) / 2} and sign inversion of the filter coefficients in the sub-filters 12_2_1 to 12_2_M. As a result, the subchannels that are baseband signals as shown in FIG. 8 are arranged on the frequency axis as a band of width Fs / N with Fs / N as the center frequency as shown in FIG.

  The combining circuits 14_1 to 14_L in FIG. 1 add and synthesize the first system integrated wave signal and the second system integrated wave signal combined to each necessary bandwidth to generate a desired channel signal.

  At this time, if the phases of the first system integrated wave signal and the second system integrated wave signal do not match at the time of input of the combining circuits 14_1 to 14_L, the quality of the combined signal deteriorates.

  In order to match the phases of the first system integrated wave signal and the second system integrated wave signal, the input signal is changed from the first system branch circuit 111 to the first system switch circuit 112 to the first system integrated wave circuits 113_1 to 113_L. And the phase characteristic of the signal reaching the synthesis circuits 14_1 to 14_L and the phase of the signal reaching the synthesis circuits 14_1 to 14_L via the second system demultiplexing circuit 121 → second system switch circuit 122 → second system integrated wave circuits 123_1 to 123_L. It is necessary to match the characteristics, and the means is shown below.

Phase characteristic θ ₁ of a signal (hereinafter referred to as “filter 1 output”) from first system branch circuit 111 → first system switch circuit 112 → first system integrated wave circuits 113_1 to 113_L to synthesis circuits 14_1 to 14_L. f) is expressed by the following formulas (13) and (14).

  Expression (13) is obtained when the sign of the filter coefficient of the even-numbered taps of the sub-filters in the first system branching circuit 111 and the first system integrated wave circuits 113_1 to 113_L is inverted (hereinafter, initial phase = 0). Called).

  Expression (14) is obtained when the sign of the filter coefficient of the odd-numbered taps of the sub-filters in the first system demultiplexing circuit 111 and the first system integrated wave circuits 113_1 to 113_L is inverted (hereinafter, initial phase = π). Called).

In Expressions (13) and (14), f is the frequency, τ _bra is the delay amount of the demultiplexing unit (demultiplexing circuit), τ _syn is the delay amount of the multiplexing unit (multiplexing circuit), and Fs is the demultiplexing unit. The input signal sampling frequency, N is the demultiplexing number.

On the other hand, the phase characteristic θ of the signal (hereinafter referred to as “filter 2 output”) that reaches the synthesis circuits 14_1 to 14_L through the second system branch circuit 121 → second system switch circuit 122 → second system integrated wave circuits 123_1 to 123_L. ₂ (f) is expressed by the following formula (15) when expressed by a calculation formula.

Therefore, the matching conditions of the phase characteristics of the filter 1 output and the filter 2 output are expressed by the following equations (16) and (17).

  In formulas (16) and (17), n is an integer.

The first system demultiplexing circuit 111 and the second system demultiplexing circuit 121 perform Fourier transform by FFT (Fast Fourier Transform), and the first system integrated wave circuits 113_1 to 113_L and the second system integrated wave circuits 123_1 to 123_L Therefore, in order to perform inverse Fourier transform by IFFT (Inverse Fast Fourier Transform), it is necessary to have a demultiplexing number N = 2 ⁿ (n is a natural number) and a multiplexing number M = 2 ⁿ (n is a natural number).

  Therefore, assuming this, in the first system demultiplexing circuit 111 and the second system demultiplexing circuit 121, the number of sub-filter multipliers is NK, the first system integrated wave circuits 113_1 to 113_L, and the second system integrated wave circuit. In 123_1 to 123_L, the number of sub-filter multipliers needs to be MK (K is the number of taps).

Therefore, when considering this in terms of impulse response length, NK and MK are even numbers. Therefore, when the filter coefficients are displayed in a graph with taps on the horizontal axis, they are symmetric as shown in FIG. In this case, the delay amounts τ _bra and τ _syn are expressed by the following equations (18) and (19).

  In equations (18) and (19), Fs is the sampling frequency of the demultiplexed input signal, and fs is the sampling frequency of the M multiplexed output (= M × Fs / N).

Here, when the delay amounts τ _bra and τ _syn are substituted into the phase characteristic matching conditional expression and expanded, the following tap number conditions such as the following expressions (20) and (21) are derived.

  Since the number of taps must be an integer, this condition does not hold unless N = M, that is, the number of demultiplexes = the number of multiplexed signals (input sampling frequency = combined output sampling frequency).

  Actually, in the case of demultiplexing number (N) = 128, multiplexing number (M) = 2, tap length (K) = 13, the term of impulse response length (NK) in the calculation formula for filter coefficient is shown in the actual configuration. When the frequency characteristics (amplitude characteristics and phase characteristics) of the filter 1 output and the filter 2 output when the filter coefficient obtained by substituting the value of the impulse response length is used are obtained by simulation, the result shown in FIG. The phase characteristics of the output and filter 2 output do not match.

Therefore, in the present invention, in order to approximately match the delay amounts τ _bra and τ _syn , the first system demultiplexing circuit 111, the second system demultiplexing circuit 121, the first system integrated wave circuits 113_1 to 113_L, the second system The calculation method of the filter coefficient of the sub filter of the integrated wave circuits 123_1 to 123_L is as follows.

  The filter coefficients of the sub-filters of the first system branch circuit 111 and the second system branch circuit 121 are calculated as h (0) after calculating the impulse response length as NK + 1 instead of the actual impulse response length NK. Among NK + 1 values of ˜h (NK), NK pieces of h (0) to h (NK−1) are used. A graph with the tap as the horizontal axis, the filter coefficient calculated by substituting a value (NK + 1) that is one more than the impulse response length in the actual configuration into the impulse response length (NK) term of the filter coefficient calculation formula Is displayed as shown in FIG.

  The filter coefficients of the sub-filters of the first system integrated wave circuits 113_1 to 113_L and the second system integrated wave circuits 123_1 to 123_L were calculated after calculating the impulse response length as MK-1 instead of the actual impulse response length MK. In addition to the MK-1 values from g (0) to g (MK-2), g (MK-1) = 0 is set to MK coefficients from g (0) to g (MK-1). The filter coefficient calculated by substituting 1 (NK-1) less than the impulse response length in the actual configuration into the impulse response length (NK) section of the filter coefficient calculation formula is a graph with taps on the horizontal axis. When displayed, it is as shown in FIG.

By using the filter coefficient calculated by the above method, the delay amounts τ _bra and τ _syn can be approximated by the following equations (22) and (23).

Substituting the delay amounts τ _bra and τ _syn into the phase characteristic coincidence conditional expression and expanding it leads to the following tap number condition.
K = 2n + 1 Initial phase = 0
When K = 2n initial phase = π

  Filter 1 output when the filter coefficient obtained by the calculation method of the present embodiment is used in the case of demultiplexing number (N) = 128, multiplexing number (M) = 2, tap length (K) = 13. When the frequency characteristics (amplitude characteristics and phase characteristics) of the filter 2 output are obtained by simulation, the result shown in FIG. 15 is obtained, and the phase characteristics of the filter 1 output and the filter 2 output substantially coincide.

  Further, the number of taps (K) of each sub-filter of the first system branch circuit 111, the second system branch circuit 121, the first system integrated wave circuit 113_1 to 113_L, and the second system integrated wave circuit 123_1 to 123_L = 1, 2, 3, 4,..., The phase characteristics of the filter 1 output when the initial phase = 0, the phase characteristics of the filter 1 output when the initial phase = π, and the phase characteristics of the filter 2 output are obtained by simulation. The results are as shown in FIGS. 16, 17, and 18, respectively.

  When the initial phase = 0, the phase characteristics of the filter 1 output and the filter 2 output match when the number of taps is odd, and when the initial phase = π, the filter 1 output matches when the number of taps is even. It can be seen that the phase characteristics of the output of the filter 2 match.

  Therefore, the filter coefficient of each sub-filter uses the filter coefficient obtained by the calculation method of the present embodiment, and when the number of taps is odd, the sign is inverted at the even-numbered taps, and the number of taps is even. Sometimes, the phase characteristics of the filter 1 output and the filter 2 output coincide with each other by inverting the sign at the odd-numbered taps.

  FIG. 19 shows the frequency characteristics of the channel signal 1 output from the synthesis circuit 14_1 when the number of multiplexed subchannel signals M = 2.

  FIG. 20 shows frequency characteristics of the channel signal 2 output from the synthesis circuit 14_2 when the number of multiplexed subchannel signals M = 4.

  FIG. 21 shows the frequency characteristics of the channel signal L output from the combining circuit 14_L when the number of combined subchannel signals is M.

(Effect of Example)
The effect of the above embodiment is that a signal of a specific channel can be extracted with the bandwidth of the channel from an input signal obtained by frequency-multiplexing multi-channel signals without degrading the signal quality.

  Thereby, in the case of the reception channelizer, it becomes possible to demodulate the extracted modulation signal of the channel as it is. Further, in the case of the transmission channelizer, when the channel of the input signal is distributed to a plurality of beams and transmitted, only the necessary channels are extracted and assigned to each transmission beam, so that the utilization efficiency can be improved.

The reason is that an input signal in which a multi-channel signal is frequency-multiplexed is divided into N subchannels, a desired subchannel is selected, and subchannels corresponding to the bandwidth according to need are assigned to the respective subchannels. In a channelizer that frequency-shifts to have frequency characteristics that are alternately arranged so that the passbands do not overlap due to overlapping channel transition regions, and generates a channel signal with a desired bandwidth by combining them.
The first system demultiplexing circuit demultiplexes the input signal into N subchannels and outputs it at the sampling rate of Fs / N.
The first system switch circuit selects and outputs an arbitrary subchannel from a desired terminal from the N subchannel signals output from the first system branch circuit,
Combined M sub-channels in the required band of the first system integrated wave circuit and output at a sampling rate (M x Fs / N) different from the sampling rate (Fs) of the input signal,
The second system demultiplexing circuit demultiplexes the input signal into N subchannels and outputs it at the sampling rate of Fs / N.
The second system switch circuit selects and outputs an arbitrary subchannel from the desired terminal from the N subchannel signals output from the second system branch circuit, and outputs 0 (null data) from the desired terminal.
Combine the M subchannels in the required band of the second system integrated wave circuit and output at a sampling rate (M x Fs / N) different from the sampling rate (Fs) of the input signal,
By synthesizing the first system integrated wave signal and the second system integrated wave signal, which are combined in the required bandwidth, respectively, to generate a desired channel signal,
It is possible to synthesize as many sub-channels as necessary (M) by combining two systems of parallel multiplexed signals that are alternately arranged so that the transition bands of each sub-channel overlap and the pass bands do not overlap. And becoming
When calculating the filter coefficient of the sub-filter in the first and second branching circuits, the impulse response length is calculated as NK + 1 instead of the actual impulse response length NK (N: number of demultiplexed subchannels, K: number of taps) Above, among the calculated NK + 1 values of h (0) to h (NK), use NK values of h (0) to h (NK-1),
In calculating the filter coefficient of the sub-filter in the first and second system integrated wave circuits, the impulse response length is calculated as MK-1 instead of the actual impulse response length MK, and the calculated g (0) to g (MK− In addition to the MK-1 values in 2), by setting g (MK-1) = 0, the coefficients are MK coefficients from g (0) to g (MK-1).
At the time of synthesizing two combined signals that are alternately arranged so that the transition bands overlap and the passbands do not overlap, the phase characteristics of both combined outputs of the two systems are This is because they can be approximately matched.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims.

111 1st system branch circuit 112 1st system switch circuit 113_1-113_L 1st system integrated wave circuit 121 2nd system branch circuit 122 122 2nd system switch circuit 123_1-123_L 2nd system integrated wave circuit 14_1-14_L synthesis circuit

Claims (8)

In a channelizer that extracts a channel signal of a desired bandwidth from an input signal in which multi-channel signals are frequency-multiplexed,
Demultiplexing means for first and second systems parallel to the input signal, which demultiplexes the input signal defined by the sampling rate Fs into N subchannels and outputs the demultiplexed signal at a sampling rate of Fs / N; ,
A desired subchannel is selectively output from the subchannels provided corresponding to the first and second system demultiplexing means and output from the first and second system demultiplexing means, or 0 (null). ) First and second system switch means for outputting data;
M sub-channels of subchannels provided corresponding to the first and second system switch means and output by the first and second system switch means are each provided with a transition area of each subchannel. A plurality of sets of first and second sets that are combined so as to have frequency characteristics that are alternately arranged so that the passbands do not overlap and output at a sampling rate M × Fs / N different from the sampling rate Fs. A second system combining means;
A plurality of combining means for adding and combining the combined signals output by the respective combining means corresponding to each other in the plurality of sets of the first and second systems;
A channelizer that extracts a signal of a specific channel from the input signal with a bandwidth of the channel. Each of the first and second branching means includes N sub-filters in parallel to which the input signal and a signal obtained by delaying the input signal by one clock at a sampling rate Fs are sequentially input. In calculating the filter coefficients of these N sub-filters, the impulse response length is calculated as NK + 1 instead of the actual impulse response length NK (K is the number of taps), and among the calculated NK + 1 values Use NK pieces,
Each combination means of the first and second systems includes M sub-filters in parallel with each other, and when calculating the filter coefficients of these M sub-filters, the impulse response length is set to the actual impulse response length MK. Instead of calculating as MK-1, and adding 0 to the calculated MK-1 values to make MK coefficients,
2. The channelizer according to claim 1, wherein phase characteristics of outputs of a plurality of pairs of the first and second systems corresponding to each other are approximately matched at an input time point of the synthesizing unit. Each of the first and second branching means is respectively
(N-1) delay circuits connected in series for delaying the input signal by one clock at a sampling rate Fs;
The N sub-filters;
N multiplication means for multiplying different predetermined coefficients for each output of the N sub-filters;
The channelizer according to claim 2, further comprising: an FFT circuit that Fourier-transforms the outputs of the N multiplication means and outputs a signal of each subchannel of the first system. The multiplexing means of each set of the first and second systems are respectively
IFFT circuit that outputs M subchannels by performing inverse Fourier transform on the input subchannel signal;
M multiplication means for multiplying different predetermined coefficients for each output of the IFFT circuit,
The M sub-filters connected to the M multiplication means;
(M−1) delay circuits connected in series for delaying the outputs of the M sub-filters by one clock at a sampling rate of M × Fs / N in order. The channelizer according to claim 2 or 3, wherein an output signal obtained by combining the outputs of the sub-filters is output.   5. The filter coefficient of each of the sub-filters, when the number of taps is odd, inverts the sign at even-numbered taps, and when the number of taps is even, inverts the sign at odd-numbered taps. The channelizer according to any one of the above. An input signal that is frequency-multiplexed with multi-channel signals is demultiplexed into N sub-channels, a desired sub-channel is selected, and sub-channels corresponding to the required bandwidth are converted into the transition areas of the respective sub-channels Is a signal processing method for generating a channel signal having a desired bandwidth by performing frequency shift so as to have frequency characteristics that are alternately arranged so that the passbands do not overlap with each other.
Demultiplexing processing of the first and second systems, which demultiplexes the input signal defined by the sampling rate Fs into N subchannels and outputs it at a sampling rate of Fs / N;
Corresponding to the demultiplexing processes of the first and second systems, a desired subchannel is selectively output from the subchannels output in the demultiplexing processes of the first and second systems, or 0 (null) data Switch processing of the first and second systems,
Corresponding to the switch processing of the first and second systems, M subchannels of the subchannels output by the switch processing of the first and second systems overlap each other in the transition region of each subchannel. A plurality of first and second systems that combine with each other to have frequency characteristics that are alternately arranged so that the passbands do not overlap and output at a sampling rate M × Fs / N different from the sampling rate Fs. And combining processing of
A plurality of combining processes for adding and combining the combined signals output in the respective combining processes corresponding to each other of the first and second systems,
A signal processing method, wherein a signal of a specific channel is extracted from the input signal with a bandwidth of the channel. N sub-filters in parallel with each other, in which the input signal and a signal obtained by delaying the input signal by one clock at a sampling rate Fs are sequentially input for the first and second system demultiplexing processes, respectively. When calculating the filter coefficients of these N sub-filters, the impulse response length is calculated as NK + 1 instead of the actual impulse response length NK (K is the number of taps). Use NK values,
In order to combine the first and second systems, M sub-filters are provided in parallel with each other. When calculating the filter coefficients of these M sub-filters, the impulse response length is set to the actual impulse response. By calculating as MK-1 instead of response length MK, and adding 1 to the calculated MK-1 values to make MK coefficients,
7. The phase characteristics of outputs output in a plurality of mutually corresponding multiplexing processes of the first and second systems are approximately matched at an input time point of the synthesis process. Signal processing method.   The filter coefficient of each of the sub-filters is characterized in that the sign is inverted at an even-numbered tap when the number of taps is odd, and the sign is inverted at an odd-numbered tap when the number of taps is even. Signal processing method.

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