JP2001111639A - Digital signal branching filter, digital signal multiplexer, digital signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal branching filter and a digital signal multiplexer that are not affected by interference due to a loopback signal and by distortion due to a joint between filters. SOLUTION: Let a sampling speed of an input signal to a 2-branch filter bank be fs and four kinds of filters whose pass band includes the fs be A, B, C, D in the order of lower frequencies, then the 2-branch filter bank is a 1st 2-branch filter bank including either of the filters A, B or a 2nd 2-branch filter bank including either of the filters C, D. The 2-branch filter bank is connected so that a next stage of a signal passing through the filter A is the 1st 2-branch filter bank, a next stage of a signal passing through the filter B is the 2nd 2-branch filter bank, a next stage of a signal passing through the filter C is the 1st 2-branch filter bank, and a next stage of a signal passing through the filter D is the 2nd 2-branch filter bank.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital signal demultiplexing device used for high-speed wireless communication and the like, and a digital signal demultiplexing device. The present invention also relates to a digital signal transmission device used for wireless communication and the like, and more particularly to a digital signal transmission device capable of easily changing a transmission speed.

[0002]

2. Description of the Related Art First, conventional digital signal demultiplexers and digital signal multiplexers will be described. A device for multiplexing or demultiplexing a plurality of frequency-multiplexed channels requires, as an analog circuit, the same number of local oscillators and band-limiting filters as the number of channels.
It is inevitable that the device scale and power consumption will increase. On the other hand, with the spread of digital signal processing technology, a demultiplexing or multiplexing device based on digital signal processing has been realized, and it has become possible to reduce the size and power consumption of the device.

[0003] In particular, digital signal demultiplexing and multiplexing devices based on the theory of multi-rate signal processing use channel spacing,
This is an effective configuration method having a high degree of freedom in setting the bandwidth.

FIG. 20 shows an example of the configuration of a quadrant digital signal demultiplexer for demultiplexing a frequency-multiplexed input signal as shown in FIG. This configuration is described in the document "Hirohito Yamano," Fast frequency search and demodulation using complex multi-rate filter bank ", Technical Report of the Institute of Television Engineers of Japan, ROFT 96-4.
6 ".

In FIG. 1, reference numeral 201 denotes a quadrature detector;
Reference numerals 2 and 203 denote A / D converters, 204, 205, and 206 denote biquadratic filter banks, and 2041, 2051, and 2061.
Is a high-pass filter, 2042, 2052, and 2062 are low-pass filters, 2043, 2044, 2053, and 2
054, 2063 and 2064 are down samplers, 207
1, 2072, 2073 and 2074 are waveform shaping filters.

High-pass filters 2041, 2051, 2
The frequency characteristic of 061 is the same if normalized by the sampling frequency, and can be expressed by (a) in FIG. In the drawing, fs represents the sampling rate of the signal when the two-wave filter is input. Similarly, low-pass filters 2042, 2
The frequency characteristics of 052 and 2062 can be represented by (b) of FIG.

[0007] The received signal is input to a quadrature detector 201 and converted into an in-phase component and a quadrature component. Quadrature detector 2
01 is output to the AD converter 202, 2
03, the in-phase component and the quadrature component are digitally converted, respectively, and then input to the half-wave filter bank 204. In the two-wave filter bank 204, the signal is branched into two systems, each of which is input to a high-pass filter 2041 and a low-pass filter 2042 and band-limited.

The band-limited signals are input to downsamplers 2043 and 2044 connected to the respective signals,
At the timing shown in FIG. 6, downsampling is performed to reduce the sampling rate to 1/2. The signals output from the downsampler are cascaded into two branching filter banks 205 and 20.
6 is input. Half-wave filter banks 205 and 206
In the signal, the signal is branched into two systems, and the high-pass filter 20
51, 2061 and low-pass filters 2052, 2062
Respectively.

The band-limited signals are transmitted to the downsamplers 2053, 2054, 2063, 2,
064, and at the timing shown in FIG.
Down sampling is performed, and
72, 2073, 2074, and after waveform shaping, FIG.
2 as four independent signals.

[0010] 2041, 2043, 20 in FIG.
Each point A, B, C, D, which passed through 51 and 2053,
The spectrum of the signal at E is as shown in FIGS. 23 (a) to (c) and FIGS. 24 (d) and (e), respectively. In these figures, indications such as "-" in the figures indicate the distinction between the original signals, and this is the same in the same kind of figures described below.

Next, FIG. 21 shows an example of the configuration of a four-multiplex digital signal multiplexer for inputting four different transmission signals, multiplexing the signals, and outputting the multiplexed signals. The vector of each transmission signal is shown in FIG.
As shown in FIG. In the figure, 212, 21
2, 213 are two multiplexing filter banks, 2111, 211
2, 2121, 2122, 2131, 2132 are upsamplers, 2113, 2123, 2133 are high-pass filters, 2114, 2124, 2134 are low-pass filters, 2115, 2125, 2135 are adders, 21
4, 215 are D / A converters, 216 is a quadrature modulator, 21
71, 2172, 2173, 2174 are waveform shaping filters.

The four different baseband signals are combined into two sets of filters 2171, 2172, and 217.
3, 2174. The outputs of the waveform shaping filters are two synthesis filter banks 211 and 21.
2 and input to the upsamplers 2111, 2112, and 2
Due to 121 and 1222, up-sampling is performed to the double sampling rate at the timing shown in FIG.

The signals that have passed through the upsamplers 2111, 2112 are input to a high-pass filter 2113 and a low-pass filter 2114, respectively, and added by an adder 2115. Similarly, upsamplers 2121, 212
2 are input to a high-pass filter 2123 and a low-pass filter 2124, respectively.
It is added at 25. 2 multiplexing filter bank 211,
The signal output from 212 is a 2-multiplex filter bank 2
13 is input.

The input signal is supplied to an upsampler 2131, 2 which performs interpolation processing twice at the timing shown in FIG.
132. Upsampler 2131, 213
2 are input to a high-pass filter 2133 and a low-pass filter 2134, respectively.
It is added at 35. The output from the two-combination filter bank 213 is input to D / A converters 214 and 215, and then converted to a desired radio frequency by an orthogonal converter 216.

2111, 2113, 21 in FIG.
The spectra of the signals at points A, B, C, D, E, F, and G passing through 15, 2131, 2133, and 2135 are shown in FIGS. 26 (a) to (c) and FIG. 27 (d), respectively. To (f) and (g) of FIG.

Next, a conventional digital signal transmission device will be described. FIG. 40 is a diagram showing an example of the configuration of a conventional digital signal transmitting apparatus, and shows a transmitting side apparatus for performing communication of signals of different transmission speeds in a wireless system using FDMA (Frequency Division Multiple Access). ing.

In FIG. 40, reference numeral 7001 denotes a serial-parallel conversion circuit, 7002 to 7009 denote modulation circuits, 7010 to 7017 denote low-pass filters, 7018 to 7025 denote local oscillation circuits, and 7
026 is a transmission circuit, 7027 is a control circuit, and 7028 to 7028
Reference numeral 035 denotes a frequency conversion circuit. In the configuration shown in the figure, the maximum number of carrier frequencies to be used is eight. FIG.
At 0, the input digital signal is input to a serial / parallel conversion circuit 7001 and converted into a maximum of eight systems of parallel data specified by the control circuit 7027 according to the transmission speed.

The speeds of these parallel data are all equal, each being Fb. The output of the serial-parallel conversion circuit 7001 is
Of the eight modulation circuits 7002 to 7009 arranged in parallel, up to eight systems are input and modulated, and output as complex modulation signals of up to eight systems.

The complex modulation signals of up to eight systems output from the modulation circuits 7002 to 7009 are
After the signals are input to and subjected to band limitation, local oscillators 7018 to 7025 are output from frequency conversion circuits 7028 to 7035.
, Are frequency-converted at different frequencies, these are combined by a combiner 7036, input to a transmission circuit 7026, and transmitted from an antenna.

FIG. 41 is a diagram showing an example of the configuration of a conventional digital signal receiving apparatus. In a wireless system using FDMA (Frequency Division Multiple Access), a receiving side of a communication system for transmitting signals of different transmission rates is used. The device is shown. In FIG. 40, reference numeral 7101 denotes a receiving circuit,
Reference numerals 7102 to 7109 denote local oscillation circuits;
7 is a low-pass filter, 7118 to 7125 are demodulation circuits, 7126 is a parallel-serial conversion circuit, 7127 is a control circuit,
Reference numerals 7128 to 7135 represent frequency conversion circuits.

The signals received by the antennas are frequency-converted into baseband signals by frequency conversion circuits 7128 to 7135 using different frequencies generated by local oscillation circuits 7102 to 7109. The signal converted to the baseband signal is a low-pass filter 710-711.
At 7 the band is limited and output.

The band-limited signal is supplied to a demodulation circuit 7118.
, And are demodulated. The demodulated signal is input to a parallel-to-serial conversion circuit 7126, which converts the parallel data of up to eight systems into serial data under the control of the control circuit and outputs the data. With such a configuration, the transmission speed can be varied from Fb to 8Fb.

[0023]

By the way, in the above-mentioned digital signal demultiplexing apparatus and multiplexing apparatus, FIGS.
As can be seen from FIG.
If the high-pass filter and low-pass filter used in the multiplexing filter bank are general half-band filters, the output signal will be a signal generated by interference due to the mixing of aliasing components or a signal generated at a joint between filters. Under the influence of distortion due to component attenuation, it becomes difficult to split or combine signals.

On the other hand, if an ideal rectangular filter as shown in FIG. 29 is used, it is possible to perform demultiplexing or multiplexing without being affected by interference or distortion. However, an impulse response having the frequency characteristics of an ideal rectangular filter cannot be realized in a finite time domain.

In the conventional variable transmission rate modulation / demodulation apparatus as described above, when an input signal or an output signal is multiplexed or demultiplexed in terms of frequency, an analog circuit is used. A local oscillator and a low-pass filter for the number of data are required, and the circuit scale and the power consumption increase.

Therefore, an object of the present invention is to provide a digital signal demultiplexer and a digital signal combiner having a high-quality characteristic which are not affected by interference by a folded signal and distortion by a seam between filters with a simple device configuration. To provide a wave device. It is another object of the present invention to provide a digital signal transmitting device, a receiving device, and a transmitting device that can make the transmission speed variable with a simple device configuration. Further, at that time, it is another object of the present invention to prevent a decrease in frequency use efficiency.

[0027]

In order to achieve the above object, the present invention provides a means for dividing an input signal into two signals by two kinds of filters having different pass bands, and a method for sampling the two divided signals. In a digital signal demultiplexing apparatus including a band demultiplexing filter bank configured by cascade-connecting two demultiplexing filter banks each including a downsampling unit for thinning out a frequency to half, the two demultiplexing filter banks are arranged such that Is a filter A in which the frequency at the lower end of the pass band is equal to or higher than -fs / 4 (fs is the sampling frequency at the input of the bi-divided filter bank) and the frequency at the upper end of the pass band is equal to or lower than fs / 2. Is a filter B in which the frequency at the lower end of the pass band is 0 or more and the frequency at the upper end of the pass band is 3 fs / 4 or less,
Or, if one of the filters has
The filter C has a frequency of 3 fs / 4 or more and a frequency of an upper end of the pass band is 0 or less, and the other filter has a frequency of a lower end of the pass band of -fs / 2 or more and a frequency of an upper end of the pass band of fs /
Or a filter D that is less than or equal to four, and the next-stage two-segment filter bank that has passed through the filter A is the filter A and the filter B, or any one of them. And the next-stage two-half filter bank that has passed through the filter B is
The filter C and the filter D, or any one of them, and the following two-stage filter bank that has passed through the filter C is the filter A and the filter B or any one of them. And the next-stage two-segment filter bank that has passed through the filter D provides a digital signal demultiplexer constituted by the filter C and the filter D or any one of them. .

Here, the "pass band" refers to a frequency band in which a signal to be filtered passes through a certain threshold in the filter characteristics of the band pass filter as shown in FIG. The upper end (maximum frequency) of this pass band is called “pass band upper end”, and the lower end (minimum frequency) is called “pass band lower end”. The digital signal demultiplexing device having this configuration can cascade-connect four types of filters having different passbands according to the above-described procedure, so that signals are not affected by interference due to aliasing components and distortion due to joints between filters. Is different from the conventional one.

According to the present invention, in the digital signal demultiplexer, the first stage of the band division filter bank includes any one or more of filters A, B, C and D. . The digital signal demultiplexing apparatus having this configuration is different from the conventional digital signal demultiplexing apparatus in that a signal can be demultiplexed in the entire sampled band without being affected by interference due to a folded component or distortion due to a joint between filters.

Further, the present invention provides an up-sampling means for up-sampling the sampling frequency of the input signals of the two systems twice for each signal, and two kinds of pass bands having different pass bands for filtering the output signals of the up-sampling means. A filter, means for combining output signals of the two types of filters,
In the digital signal multiplexing apparatus provided with a band combining filter bank formed by cascade-connecting two multiplexing filter banks, the one of the two multiplexing filter banks is such that the frequency at the lower end of the passband is −fs. / 4 (fs is the sampling frequency at the input of the two-half filter bank), and the filter E is such that the frequency at the upper end of the pass band is not higher than fs / 2. Either the filter F is such that the frequency at the upper end of the band is 3 fs / 4 or less, or one of the filters has a frequency at the lower end of the pass band of -3 fs / 4 or more and a frequency of the upper end of the pass band is 0 or less. Or the other is a filter H having a frequency at the lower end of the pass band equal to or higher than -fs / 2 and a frequency at the upper end of the pass band equal to or lower than fs / 4. And the output signal of the two-combination filter bank constituted by the filter E and the filter F or any one of them is supplied to the filter E or the filter E via the up-sampling means. The output signal of the two-multiplex filter bank, which is input to the filter G and is configured by the filter G and the filter H, or any one of them, is supplied to the filter F, Alternatively, a digital signal multiplexing device input to the filter H is provided. The digital signal multiplexing device according to this configuration cascade-connects four types of filters having different passbands in the order described above, so that the signal is not affected by interference due to aliasing components and distortion due to joints between filters. Is different from the conventional one.

According to the present invention, in the digital signal multiplexer, the final stage of the band synthesis filter bank includes any one or more of filters E, F, G and H. I do. The digital signal multiplexing apparatus having this configuration is different in that signals can be multiplexed within the entire sampled band without being affected by interference due to a folded component or distortion due to a joint between filters.

Further, according to the present invention, in the digital signal demultiplexing apparatus and the digital signal multiplexing apparatus, the impulse responses A (n), B () of the filters A, B, C, D, E, F, G, H are provided. n), C (n), D (n), E (n),
F (n), G (n), and H (n) (1 ≦ n ≦ N, where n is an integer) are expressed by the following equation (5), where I (n) is the impulse response of the original filter having the tap length N. , "Equation 6".

(Equation 5)

(Equation 6) In a digital signal demultiplexing device and a digital signal multiplexing device, since the amount of calculation is increased if a complex filter is used, frequency conversion is performed using Expression 5 as an original filter.

As a result, the filter of each filter is a real number or an imaginary number only, excluding the center tap, or the coefficient becomes zero, which is different from the others in that it can be realized with a calculation amount almost equal to that of the conventional real number filter. As an example, when the original filter has seven taps, the tap coefficients shown in Table 2 are obtained when the tap coefficients of the original filter as shown in Table 1 are subjected to frequency conversion using “Equation 5” for k = 1. Can be

[Table 1]

[Table 2]

According to another aspect of the present invention, there is provided a digital signal transmission device including at least one of a transmission device and a reception device, wherein the transmission device converts an input signal into a plurality of low-speed signals. Serial-parallel conversion means for serial-to-parallel conversion, a plurality of modulation means for modulating each parallelized signal, channel multiplexing means for frequency-multiplexing and multiplexing the modulated signals, and a transmission circuit. The channel multiplexing means includes an up-sampling means for up-sampling the sampling frequency of the input signal of the two systems twice for each signal, and two kinds of different pass bands for filtering the output signal of the up-sampling means. , And one or more two-combination filter banks comprising means for synthesizing the output signals of the two types of filters. If there are two or more two-complex filter banks, A plurality of wave filter banks are connected in cascade in a multistage manner. The plurality of modulating means are divided into two, and two outputs of each of the two modulating means are input to one two-multiplexing filter bank. , The two multiplexing filter banks are divided into two, the outputs of the two two multiplexing filter banks are input to the next two multiplexing filter banks, and the output of the two multiplexing filter banks is further In order to input to the two multiplexing filter banks at the last stage, the outputs of the two multiplexing filter banks at the preceding stage are sequentially connected to the input of one two multiplexing filter bank at the end. The output of the final two-stage multiplexing filter bank is configured to be input to the transmission circuit, and the reception device is configured to separate the reception circuit and the frequency-multiplexed signal into two signals. Channel demultiplexing means, and the channel A plurality of demodulation circuits for demodulating the output of the demultiplexing means; and a parallel-serial conversion means for inputting each output of the demodulation circuit. The channel demultiplexing means is provided by two types of filters having different passbands. One or more bi-segment filter banks comprising means for demultiplexing a signal into two signals, and down-sampling means for thinning out the sampling frequency of the two demultiplexed signals to そ れ each, are provided. When there are two or more wave filter banks, the configuration is such that the two-segment filter banks are cascaded in multiple stages, and the output of the receiving circuit is input to the two-segment filter banks, Are input to the different two-stage splitter filter banks at the next stage, respectively.
The two outputs of the next-stage two-half-wave filter banks are connected so as to be further input to different next-stage two-half-wave filter banks. Provided is a digital signal transmission device which is configured to be inputted to respective demodulation circuits, to input the outputs of the respective demodulation circuits to parallel / serial conversion means, and to use the output of the parallel / serial conversion means as a receiver output. The digital signal transmission device having this configuration is different from the conventional one in that the entire device can be formed as a digital circuit, and the device scale can be easily reduced.

Further, the present invention is a digital signal transmission device provided with at least one of a transmission device and a reception device, wherein the transmission device serial-parallel conversion means for converting an input signal into a plurality of low-speed signals. A plurality of modulating means for modulating each parallelized signal, a channel multiplexing means for frequency-multiplexing and multiplexing the modulated signal, and a transmission circuit, the channel multiplexing means, Up-sampling means for up-sampling the sampling frequency of the two input signals for each signal, two types of filters having different pass bands for filtering output signals of the up-sampling means, and the two types of filters And a means for synthesizing the output signals of
When the number of multiplexing filter banks is two or more, the two multiplexing filter banks are cascaded in multiple stages, and the outputs of two modulating means in the transmitting device are connected to the two multiplexing filter banks. Is multiplexed by frequency multiplexing with one of
The output of the multiplexing filter bank and the output of another modulating means connected to the serial-parallel conversion means or the output of a different two-multiplexing filter bank having the same sampling rate are output by the next-stage two-multiplexing filter bank. Multiplex, and
The output of the two multiplexing filter bank and the output of another modulating means connected to the serial / parallel conversion means, or the output of a different two multiplexing filter bank having the same sampling rate are output to the next two multiplexing filter. The receiver is sequentially connected so as to be multiplexed by a bank, and the output of one final two-multiplexing filter bank is input to the transmitting circuit. The receiving device is frequency-multiplexed with the receiving circuit. Channel demultiplexing means for demultiplexing the received signal, a plurality of demodulation circuits for demodulating the received signal, and parallel / serial conversion means for inputting each output of the demodulation circuit. It consists of means for splitting the input signal into two signals by two types of filters having different bands, and down-sampling means for thinning out the sampling frequency of the two split signals by half. Comprising one or more 2 minutes wave filter bank, if the half wave filter bank is two or more, the 2
It is a configuration in which the demultiplexing filter banks are cascaded in multiple stages,
The output of the receiving circuit is split by a two-segment filter bank, and one of the two outputs of the two-segment filter bank is connected to
The other is input to a demultiplexing filter bank or a demodulation circuit, and the other is sequentially connected so as to be input to a different two-division filter bank or a different demodulation circuit of the next stage, and the output of each demodulation circuit is connected in parallel to A digital signal transmission device configured to input to a conversion means is provided.
According to the present invention, the transmission rate can be made variable by selecting an appropriate modulation circuit according to the input transmission rate.

Also, the present invention is a digital signal transmission device provided with at least one of a transmission device and a reception device, wherein the transmission device modulates an input signal in a time-division manner, Up-sampling means having channel multiplexing means for multiplexing and multiplexing, and a transmission circuit, wherein the channel multiplexing means up-samples the sampling frequency of the input signals of the two systems twice for each signal;
One or more two-combination filter banks comprising two types of filters having different passbands for filtering the output signals of the up-sampling means and means for combining the output signals of the two types of filters are provided. When there are two or more wave filter banks, the two multiplexing filter banks are connected in cascade in multiple stages, and two of the outputs of the time-division processing modulating means are connected to the two multiplexing filter banks. Input to one of the banks, the output of the two-multiplexing filter bank is input to the next-stage two-multiplexing filter bank, and the output of the modulation means for performing the time-division processing is applied to the two-multiplexing filter bank. Are sequentially connected so as to be directly input, and the output of the final two-stage multiplexing filter bank is input to the transmitting circuit. The receiving apparatus further comprises: a receiving circuit; Split the signal A that a channel dividing means, and a demodulation circuit for processing a time division output of said channel demultiplexing means,
Means for splitting the input signal into two signals by two types of filters having different passbands,
One or more two-segment filter banks are provided as down-sampling means for thinning out the sampling frequency of each of the two split signals to １ ／. If the number of the two-segment filter banks is two or more, A demodulator in which the output of the receiving circuit is input to the two-segment filter bank, and one of the two outputs of the two-segment filter bank is processed in the time division manner. Circuit, the other is input to a different two-half filter bank at the next stage, and one of the two outputs of the two-half filter bank is input to a different two-half filter bank at the next stage, and the other is Input to the demodulation circuit for processing in the time division,
Thus, the present invention provides a digital signal transmission apparatus that is sequentially connected and configured to obtain an output from a demodulation circuit that performs time division processing. In the present invention, according to the input transmission speed,
By selecting an appropriate modulation circuit, the transmission speed can be made variable.

According to the present invention, in the above digital signal transmission apparatus, one of the filters of the two multiplexing filter banks of the channel multiplexing means has a frequency at the lower end of the passband of -fs.
/ 4 (fs is the sampling frequency at the input of the two-half filter bank) and the frequency at the upper end of the passband is fs /
The filter A is such that the frequency at the lower end of the pass band is 0 or more and the frequency at the upper end of the pass band is 3 fs /
Either the filter B is equal to or less than 4 or one filter is the filter C whose frequency at the lower end of the pass band is equal to or higher than -3fs / 4 and the frequency at the upper end of the pass band is equal to or lower than 0, and However, the frequency at the lower end of the passband is -fs /
A filter D whose frequency is 2 or more and an upper end of a pass band is fs / 4 or less, and is configured by the filter A and the filter B or any one of them. The output signal of the two-multiplex filter bank is passed through the up-sampling means,
An output signal of a two-combination filter bank, which is input to the filter A or the filter C and is configured by the filter C and the filter D, or any one of them, is transmitted through the up-sampling unit. , B, or D. The digital signal transmission device having this configuration can combine the channels without being affected by the interference or the amplitude distortion due to aliasing when frequency-multiplexing each channel.

According to the present invention, in the above digital signal transmission apparatus, one of the filters of the two-segment filter bank of the channel demultiplexer has a frequency at the lower end of the pass band of -fs.
/ 4 (fs is the sampling frequency at the input of the two-half filter bank) and the frequency at the upper end of the passband is fs /
The filter A is such that the frequency at the lower end of the pass band is 0 or more and the frequency at the upper end of the pass band is 3 fs /
Either the filter B is equal to or less than 4 or one filter is the filter C whose frequency at the lower end of the pass band is equal to or higher than -3fs / 4 and the frequency at the upper end of the pass band is equal to or lower than 0, and However, the frequency at the lower end of the passband is -fs /
Or a filter D whose frequency at the upper end of the pass band is equal to or less than fs / 4, and the next-stage bifurcated filter bank that has passed the filter A is the filter A and The next-stage bi-partition filter bank, which is constituted by the filter B or any one of them, and has passed the filter B, is the filter C
And the filter D or any one of them, and the next-stage two-half filter bank passing through the filter C is provided by the filter A and the filter B or any one of them. The second-stage splitter filter bank that has been configured and passed the filter D is configured by the filter C and the filter D or any one of them. In the digital signal transmission device having this configuration, when the frequency-multiplexed signal is demultiplexed into each channel,
The signal can be split without being affected by the interference or the amplitude distortion due to the aliasing.

Further, the present invention is configured to cope with a case where low-speed signals of different speeds are mixed in the specific digital signal transmission apparatus. The digital signal transmission device having this configuration differs from the conventional one in that it has modulation / demodulation circuits having different modulation speeds. As a result, the number of modulation / demodulation units can be reduced as compared with the case where the constant-speed modulation / demodulation units are used.

Further, the present invention is adapted to cope with the case where the speeds of the low-speed signals are all different in the above-mentioned specific digital signal transmission apparatus. The digital signal transmission device having this configuration can minimize the number of modulation / demodulation means for obtaining the same transmission speed.

According to the present invention, in the above digital signal transmission apparatus, at least a part of the modulating means, the demodulating means, the multiplexing means, and the demultiplexing means operate in a time division manner. is there. The digital signal transmission apparatus having this configuration utilizes the fact that the sampling speeds of the modulating means, the two multiplexing filter bank, the splitter filter bank, and the demodulating means are different, and that the lower the sampling speed, the greater the number of systems. Slow processing,
By executing the processing in a time-division manner by one system of higher-speed processing means, the size of the apparatus can be reduced.

According to the present invention, in the above digital signal transmission apparatus, a means for varying the speed of input / output digital signals is provided. The digital signal transmission device having this configuration is different from the conventional one in that signals having different transmission speeds can be transmitted with a simple device configuration.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, in the embodiments 1-1 to 1-4, a digital signal demultiplexing device and a digital signal multiplexing device will be described. Also, the second
In the first to second to fourth embodiments, a digital signal transmitting device, a digital signal receiving device, and a digital signal transmitting device including these transmitting / receiving devices will be described.

(1-1 Embodiment) The first embodiment of the present invention.
One embodiment is shown in FIG. In the figure, 100 is a detector, 101 is an A / D converter, 102, 103, 10
Reference numerals 4, 105, 106, 107, and 108 denote two-branch filter banks, 1021, 1031, 1051, and 1071 denote first filters, 1022, 1032, 1052, and 1072.
Is a second filter.

Reference numerals 1041, 1061, and 108 denote third filters, and reference numerals 1042, 1062, and 1082 denote fourth filters, 1023, 1024, 1033, 1034, and 104.
3, 1044, 1053, 1054, 1063, 106
4, 1073, 1074, 1083, 1084 are downsamplers, 2091, 2092, 2093, 209
4, 2095, 2096, 2097 and 2098 are waveform shaping filters.

In the figure, the first filter, the second filter, the third filter, and the fourth filter have the frequency characteristics shown in FIG. 5 and the original filter has seven taps. And it is as showing in Table 3, Table 4, and Table 5. FIG. 5 shows that the sampling frequency of the filter included in the filter bank is fs, and -fs / 2
5 shows the frequency characteristics of each filter when the frequency range is defined in the range of fs / 2 to fs / 2. Here, if the passband is redefined to be included in fs, and each filter is shown from the lower frequency side,
The order is the first filter, the second filter, the third filter, and the fourth filter.

[Table 3]

[Table 4]

[Table 5]

The received signal input to the digital signal demultiplexer is input to the detector 100, and then the A / D converter 1
01 is input. The signal input to the A / D converter 101 is converted to a digital signal, and then input to the bi-wave filter bank 102. The signal is branched into two systems in the two-wave filter bank 102, and is input to the first filter 1021 and the second filter 1022 having different passbands, respectively, and band-limited.

The band-limited signals are input to downsamplers 1023 and 1024 connected to the respective signals.
At the timing shown in FIG. 6, downsampling is performed to reduce the sampling rate to 1/2. The signal output from the downsampler 1023 is connected to the cascade-connected demultiplexing filter bank 103.
The signal output from the downsampler 1024 is input to the cascade-connected half-wave filter 104.

The two-wave filter bank 103 is composed of a first filter, a second filter, and two downsamplers.
As described above, the biquadratic filter bank 104 includes a third filter, a fourth filter, and two downsamplers. 2
In the demultiplexing filter banks 103 and 104, the signal is branched into two systems, and the half-band filters 1031 and 103
2, 1041, and 1042, respectively. The band-limited signals are input to downsamplers 1033, 1034, 1043, and 1044 connected to the respective signals.

Then, at the timing shown in FIG.
Down sampling is performed. The signal output from the down sampler 1033 is applied to the cascade-connected two-segment filter bank 105, and the signal output from the down sampler 1034 is applied to the cascade-connected two-shunt filter 10.
6 and output from the downsampler 1043 are cascaded into two-divided filter banks 107.
The signal output from the downsampler 1044 is input to the cascade-connected two-wave filter 108.

The two-wave filter bank 105 is composed of a first filter, a second filter, and two downsamplers.
Similarly, the splitter filter bank 106 includes a third filter,
The fourth filter and two down-samplers are also provided. Similarly, the two-segment filter bank 107 is constituted by the first filter and the second filter and the two down-samplers. It consists of a filter, a fourth filter and two downsamplers.

The two-wave filter banks 105, 106, 1
07, 108, the signal is split into two systems, and the half-band filters 1051, 1052, 1061, 106
2, 1071, 1072, 1081, and 1082.

The band-limited signals are sent to the downsamplers 1053, 1054, 1063, 1
064, 1073, 1074, 1083, and 1084, down-sampling to 1/2 is performed at the timing shown in FIG.
1, 2092, 2093, 2094, 2095, 209
6, 2097, and 2098, and output as eight independent signals.

In FIG. 1, 1021, 1023, and 103
The spectrums of the signals at points A, B, C, D, E, F, G and H passing through 1, 1033, 1051 and 1053 are shown in FIGS. 7 (a) to 7 (c) and FIG. 8 (d). ~
(F) and as shown in (g) and (h) of FIG.

(Embodiment 1-2) Embodiment 1 of the present invention
FIG. 2 shows a second embodiment. In the figure, 200 is a quadrature detector, 2011 and 2012 are A / D converters, 20
2 is a quadrant filter bank, 203, 204, 205,
Reference numeral 206 denotes a binary filter bank, 2021, 2031,
2051 is a first filter, 2022, 2032, 205
Reference numeral 2 denotes a second filter, and reference numerals 2023, 2041, and 2061 denote third filters.

Reference numerals 2024, 2042, and 2062 denote fourth filters, which are 2025, 2026, 2027, and 2
028, 2033, 2034, 2043, 2044, 2
053, 2054, 2063, 2064 are down samplers, 2071, 2072, 2073, 2074, 20
75, 2076, 2077, 2078 are waveform shaping filters.

Further, in the figure, the first filter, the second filter, the third filter, and the fourth filter have the frequency characteristics shown in FIG. 5 and the original filter has seven taps. As shown in FIG. The received signal input to the digital signal demultiplexer is input to the quadrature detector 200, where it is converted into an in-phase component and a quadrature component.
The outputs of the quadrature detector 200 are A / D converters 2011 and 2
012, and the in-phase component and the quadrature component
It is converted to a digital signal by a / D converter.

The outputs of the A / D converters 2011 and 2012 are input to the quadrant filter bank 202. The signal is branched into four systems in the quadrant filter bank 202, and the first filter 2021, the second filter 2022, the third filter 2023, and the fourth filter 2 each having different passbands.
024 and the band is limited. The band-limited signal is connected to the downsampler 2025,
The signals are input to 2026, 2027, and 2028, and downsampling is performed at the timing shown in FIG.

The signal output from the downsampler 2025 is supplied to a cascade-connected two-segment filter bank 203.
The signal output from the downsampler 2026 is input to the cascade-connected half-wave filter 204, and the signal output from the downsampler 2027 is input to the cascade-connected half-wave filter bank 205 and the downsampler 2028. The output signal is cascade-connected to two-branch filter 20.
6 is input.

The two-branch filter banks 203 and 205 are
It is composed of a first filter, a second filter, and two downsamplers.
Is composed of a third filter, a fourth filter, and two downsamplers. Within the two-wave filter bank 203,
The signal is split into two systems and input to the first filter 2031 and the second filter 2032, respectively.

The band-limited signals are input to the downsamplers 2033 and 2034 connected to the respective signals.
At the timing shown in FIG. 6, downsampling is performed to reduce the sampling rate to 1/2. Similarly, the splitter filter bank 20
4, the signal is split into two systems and the third filter 204
1 and the fourth filter 2042.

The band-limited signals are input to downsamplers 2043 and 2044 connected to the respective signals.
At the timing shown in FIG. 6, downsampling is performed to reduce the sampling rate to 1/2. Similarly, the splitter filter bank 20
5, the signal is split into two systems and the first filter 205
1 and the second filter 2052.

The band-limited signals are input to downsamplers 2053 and 2054 connected to the respective signals.
At the timing shown in FIG. 6, downsampling is performed to reduce the sampling rate to 1/2. Similarly, the splitter filter bank 20
6, the signal is split into two systems, and the third filter 206
1 and the fourth filter 2062.

The band-limited signals are input to the downsamplers 2063 and 2064 respectively connected thereto, and
At the timing shown in FIG. 6, down-sampling to reduce the sampling rate to 1/2 is performed, and the waveform shaping filters 2071 and 207 are performed.
2, 2073, 2074, 2075, 2076, 207
7, 2078 and output as independent eight-system signals.

In FIG. 2, 2021, 2025, 203
Each point A, B, C, D, which passed 1, 1033
E, the spectrum of the signal is shown in FIG.
(C) and (d) to (f) of FIG.

(Embodiment 1-3) Embodiment 1 of the present invention
FIG. 3 shows a third embodiment. In the figure, the first filter, the second filter, the third filter, the fourth filter,
It has the frequency characteristics shown in FIG. 5, and the original filter has seven taps, and the tap coefficients are as shown in Tables 2, 3, 4, and 5.

In the figure, 301, 302, 303, 3
04, 305, 306, and 307 are two multiplexing filter banks, 3011, 3012, 3021, 3022, and 303.
1, 3032, 3041, 3042, 3051, 305
2, 3061, 3062, 3071, and 3072 are upsamplers, and 3013, 3033, 3053, and 3073 are first filters.

Also, 3014, 3034, 3054, 3
074 is a second filter bank, 3023, 3043, 3
063 is a third filter, 3024, 3044, 3064
Is the fourth filter, 3015, 3025, 3035, 30
45, 3055, 3065, 3075 are adders, 308
Is a D / A converter, 309 is a modulator, 3101, 310
2, 3103, 3104, 3105, 3106, 310
7 and 3108 are waveform shaping filters.

The transmission signals of the eight different systems input to the digital signal multiplexing device are divided into waveform shaping filters 3101, 3
102, 3103, 3104, 3105, 3106, 3
107 and 3108 are input. The output of each waveform shaping filter is combined by two systems and input to two multiplexing filter banks 301, 302, 303 and 304, respectively.

The signals are input to the connected upsamplers 3011 and 3012 in the two-combination filter bank 301, and are upsampled twice at the timing shown in FIG. Outputs of the upsamplers 3011 and 3012 are input to the connected first filter 3013 and second filter 3014 and band-limited.

The first filter 3013 and the second filter 30
The output of 14 is input to the complex adder 3015 and added. Similarly, the signal is input to the connected upsamplers 3021 and 3022 in the two-multiplex filter bank 302, and the upsampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 3021 and 3022 are connected to the third filter 3023 and the fourth filter 3
024 and the band is limited. Third filter 302
The outputs of the third and fourth filters 3024 are complex adders 3025
Is added to the input. Similarly, the signal is connected to the connected upsampler 30 in the two-multiplex filter bank 303.
31 and 3032, and up-sampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 3031 and 3032 are connected to the first filter 3033 and the second filter 3
034 and the band is limited. First filter 303
3 and the output of the second filter 3034 are complex adders 3035
Is added to the input. Similarly, the signal is connected to the connected upsampler 30 in the two-multiplexing filter bank 304.
41 and 3042, and up-sampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 3041 and 3042 are connected to the connected third filter 3043 and fourth filter 3
044 and the band is limited. Third filter 304
The output of the third and fourth filters 3044 is a complex adder 3045
Is added to the input. 2 multiplexing filter bank 3
The outputs of 01 and 302 are input to a two-multiplex filter bank 305.

In the two-combination filter bank 305, the signals are input to the upsamplers 3051 and 3052 respectively connected thereto, and are upsampled twice at the timing shown in FIG. Outputs of the upsamplers 3051 and 3052 are input to the connected first filter 3053 and second filter 3054 and band-limited.

The first filter 3053 and the second filter 30
The output of 54 is input to the complex adder 3055 and added.

Similarly, the two multiplexing filter banks 303, 3
04 is input to the two-multiplex filter bank 306. In the two-multiplexing filter bank 306, the signals are input to the upsamplers 3061 and 3062 respectively connected thereto, and upsampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 3061 and 3062 are connected to the connected third filter 3063 and fourth filter 3
064 and band-limited. Third filter 306
The outputs of the third and fourth filters 3064 are complex adders 3065
Is added to the input. 2 multiplexing filter bank 3
The outputs of 05 and 306 are input to the two-multiplex filter bank 307.

In the two-combination filter bank 307, the signals are input to the up-samplers 3071 and 3072, respectively, and are up-sampled twice at the timing shown in FIG. The outputs of the upsamplers 3071 and 3072 are input to the connected first filter 3073 and second filter 3074 and band-limited.

The first filter 3073 and the second filter 30
The output of 74 is input to the complex adder 3075 and added. The output of the two-multiplex filter bank 307 is D / A
After being input to the converter 308 and converted to analog, it is input to the modulator 309 and transmitted.

In FIG. 3, 3011, 3013, 301
5, 3051, 3053, 3055, 3071, 307
Each point A, B, C, D, which passed 3,3075,
The spectrum of the signal at E, F, G, H, I, J is
This is as shown in FIGS. 13 (a) to 13 (c), FIGS. 14 (d) to (f), FIG. 15 (g) to (i), and FIG. 16 (j).

(Embodiment 1-4) Embodiment 1 of the present invention
FIG. 4 shows a fourth embodiment. In the figure, the first filter, the second filter, the third filter, the fourth filter,
It has the frequency characteristics shown in FIG. 5, the original filter has seven taps, and the tap coefficients are as shown in Tables 2 to 5.

In the figure, 401, 402, 403,
404 is a 4-multiplex filter bank, 4011, 4012,
4021, 4022, 4031, 4032, 4041,
Reference numerals 4042, 4051, 4052, 4053, and 4054 denote upsamplers, and reference numerals 4013, 4033, and 4055 denote first filters.

Reference numerals 4014, 4034, and 4056 denote second filters, reference numerals 4023, 4043, and 4057 denote third filters, reference numerals 4024, 4044, and 4058 denote fourth filters.
4015, 4025, 4035, 4045 and 4059 are adders, 406 and 407 are D / A converters, and 408
Is a quadrature modulator, 3091, 3092, 3093, 309
4, 3095, 3096, 3097, 3098 are waveform shaping filters.

The transmission signals of the eight different systems input to the digital signal multiplexer are divided into waveform shaping filters 3091,
092, 3093, 3094, 3095, 3096, 3
097 and 3098. The output of each waveform shaping filter is combined by two systems and input to two multiplexing filter banks 401, 402, 403, and 404, respectively.

The signal is input to the connected upsamplers 4011 and 4012 in the two-multiplexing filter bank 401, and the upsampling is performed twice at the timing shown in FIG. Outputs of the upsamplers 4011 and 4012 are input to the connected first filter 4013 and second filter 4014 and band-limited.

The first filter 4013 and the second filter 40
The output of 14 is input to a complex adder 4015 and added. Similarly, a signal is input to the connected upsamplers 4021 and 4022 in the two-multiplex filter bank 402, and upsampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 4021 and 4022 are connected to the third filter 4023 and the fourth filter 4
024 and the band is limited. Third filter 402
The output of the third and fourth filters 4024 is a complex adder 4025
Is added to the input. Similarly, the signal is connected to the connected upsampler 40 in the two-multiplex filter bank 403.
31 and 4032, and up-sampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 4031 and 4032 are connected to the first filter 4033 and the second
034 and the band is limited. First filter 403
3 and the output of the second filter 4034 are complex adders 4035
Is added to the input. Similarly, within the two-multiplex filter bank 404, the signal is
The signals are input to 41 and 4042, and up-sampling is performed twice at the timing shown in FIG.

The outputs of the upsamplers 4041 and 4042 are connected to the connected third filter 4043 and fourth filter 4
044 and the band is limited. Third filter 404
The output of the third and fourth filters 4044 is a complex adder 4045
Is added to the input. 2 multiplexing filter bank 4
Outputs of 01, 402, 403, and 404 are input to a 4-multiplex filter bank 405.

In the four-combination filter bank 405, the connected upsamplers 4051, 4052, 40
53 and 4054, and up-sampling is performed twice at the timing shown in FIG. The outputs of the upsamplers 4051 and 4052, 4053, and 4054 are connected to the connected first filter 4055 and second filter 405.
6, input to the third filter 4057 and the fourth filter 4058 and band-limited.

First filter 4055, second filter 40
The outputs of 56, the third filter 4057, and the fourth filter 4058 are input to the complex adder 4059 and are added. The output of the four-combination filter bank 405 is input to D / A converters 406 and 407 and is converted to analog.
The signal is input to the quadrature modulator 408 and transmitted.

In FIG. 4, 4011, 4013, 401
The spectra of the signals at points A, B, C, D, E, F and G passing through 5, 4051, 4055 and 5059 are shown in FIGS. 17 (a) to 17 (c) and FIGS. 18 (d) to 18 (d).
(F), as shown in FIG.

The above-described embodiments 1-1 to 1-4 are examples in which the number of carriers to be demultiplexed and multiplexed is eight. However, the number of stages of the cascaded two-demultiplex filter banks may be changed. Can be used for any number of carriers.

In the first to the first to fourth embodiments, examples are shown in which each of the two-half filter bank and the two-multiplex filter bank includes two filters. A configuration in which all or a part includes only one filter is also possible. Here, the case where each of the two-branch filter banks or two-combination filter banks includes only one filter does not use some carriers and does not include filters and samplers corresponding to the carriers.
Therefore, when focusing only on the filter, the two-branch filter bank in the digital signal demultiplexing device is as follows: a two-branch filter bank including both the first filter and the second filter; and a two-branch filter including only the first filter. Bank ・ Biplex filter bank including only the second filter ・ Biquad filter bank including both the third and fourth filters ・ Biquad filter bank including only the third filter ・ Only the fourth filter Includes one of the two splitter filter banks. As can be inferred from FIGS. 1 and 2 and the like, the connection of each of the two-half filter banks is made up of at least the first and second filters of the next stage of the signal that has passed through the first filter. It becomes a two-wave filter bank including one. Similarly, the second-half filter bank at the next stage of the signal passed through the second filter is a two-half filter bank including at least one of the third filter and the fourth filter. Further, the second-half filter bank at the next stage of the signal that has passed through the third filter is a two-half filter bank including at least one of the first filter and the second filter. In addition, the second stage of the signal that has passed through the fourth filter
The branching filter bank is a two-branching filter bank including at least one of the third filter and the fourth filter.

Similarly, the two-multiplexing filter bank in the digital signal multiplexing device, when focusing only on the filter, includes: a two-multiplexing filter bank including both the first filter and the second filter; and including only the first filter. 2 multiplexing filter bank 2 multiplexing filter bank including only the second filter 2 multiplexing filter bank including both the 3rd and 4th filters 2 multiplexing filter bank including only the 3rd filter 4th This is one of the two multiplexing filter banks that include only the filter. As can be inferred from FIGS. 3 and 4 and the like, the connection of each of the two multiplexing filter banks is based on the output signal of the two multiplexing filter bank including at least one of the first filter and the second filter. It is connected so as to be input to a two-combination filter bank having a third filter. The output signal of the two-multiplex filter bank including at least one of the third filter and the fourth filter is:
It is connected so as to be input to a two-combination filter bank constituted by the second filter or the fourth filter.

In the digital signal multiplexers 1-3 to 1-4, even when signals (data) having different speeds are multiplexed to output a frequency multiplexed signal, two multiplexing is performed. This can be handled by devising the cascade connection of the filter banks. For example, when two signals having a signal rate α are combined with one signal having a signal rate 2α and four signals having a signal rate 4α are combined, the connection of the two combining filter banks is connected as shown in FIG. You can respond by doing. In addition, five signals at the signal speed α and one signal at the signal speed 2α
When two signals are multiplexed, it is possible to cope with the connection of the two-half filter bank as shown in FIG. In FIG. 55, the two-wave filter bank 9000 is used.
May include only one filter and one downsampler. Similarly, according to the signal speed and the number of signals to be multiplexed, for example, by configuring as shown in FIGS. 66 and 57, it is possible to multiplex signals having different signal speeds.

In the digital signal demultiplexing apparatuses 1-1 to 1-2, even if a signal of a different speed is frequency-multiplexed with a reception signal to be demultiplexed, the speed of the included signal is This can be dealt with by devising the cascade connection of the two-half filter bank according to the band in which the signal is multiplexed. For example, when demultiplexing a signal output from a digital signal multiplexer having a cascade connection of two multiplexer filters shown in FIG. 54, the connection of the two-demultiplexer filter bank of the digital signal demultiplexer is illustrated. This can be handled by connecting as shown in FIG. Similarly, FIGS.
When splitting a signal output from a digital signal multiplexer having a cascade connection of two multiplexer filters shown in FIG. It can be handled by connecting as shown by 62.

In the digital signal demultiplexer shown in 1-2, an example is shown in which the first-stage filter bank includes all of the first to fourth filters. The present invention is not limited to this, and the first-stage filter bank may include any one or more of the first to fourth filters according to the number of signals to be demultiplexed and the band used in frequency multiplexing. Good. Similarly, in the digital signal multiplexer shown in 1-4, an example is shown in which the last-stage filter bank includes all of the first to fourth filters. The present invention is not limited to this, and the final-stage filter bank includes any one or more of the first to fourth filters according to the number of signals to be combined and the band used in frequency multiplexing. Is also good.

(2-1 Embodiment) The second embodiment of the present invention.
One embodiment is shown in FIGS. FIG.
FIG. 32 is a block diagram illustrating an example of a configuration of a transmission device of the digital signal transmission device. FIG. 32 is a block diagram illustrating an example of a configuration of a reception device of the digital signal transmission device.

The digital signal transmission device of the present invention comprises at least one transmission device and one reception device. FIG.
The digital signal transmission apparatus shown in FIG. 1 and FIG. 32 shows a configuration example in the case where the number of systems of the used carrier is eight. FIG.
In FIG. 1, reference numeral 6101 denotes a serial-parallel conversion circuit,
Reference numerals 02 to 6109 denote modulation circuits, reference numerals 6110 to 6116 denote two-multiplex filter banks, reference numeral 6117 denotes a control circuit, and reference numeral 6118 denotes a transmission circuit.

Here, the control circuit 6117 controls the serial-parallel conversion circuit 6101 to convert the input signal (data) into eight low-speed signals (data) and output which low-speed signal to which modulation circuit. And controls the output timing. In addition, the control circuit 6117 controls each modulation circuit 6.
The operation / stop of 102 to 6215 is controlled. Note that "
The "low-speed signal" is a signal output from a serial-parallel conversion circuit or a time-division modulation circuit in the case of a digital signal transmission device, and is input to a parallel-serial conversion circuit or a time-division demodulation circuit in the case of a digital signal reception device. Signal.

FIG. 38 shows the configuration of a two-multiplex filter bank. In the figure, reference numerals 6801 and 6802 denote digital filters, and 6803 and 6804 denote upsamplers. Each of the digital filters 6801 and 6802 is composed of a filter having a different pass band. The frequency characteristics of each filter are as shown in FIG. 47.
In the fourth embodiment, see the document "Kazuhiro Tanabe," Proposal of Seamless Multirate Filter Bank ", IEICE Technical Report SAT
99-14 ".

FIG. 47 shows a case where the sampling frequency of the filter included in the filter bank is fs and 0 to f
This is the frequency characteristic of each filter when specified in the range of s. As can be seen from FIG. 47, when each filter is shown from the lower frequency side, the order is the first filter, the second filter, the third filter, and the fourth filter.

The input time-series data is input to a serial / parallel conversion circuit 6101 and is converted into parallel data of up to eight systems. The speeds of these parallel data are all equal, each being Fb. Up to eight parallel data output by the serial-parallel conversion circuit are output from the modulation circuits 6102 to 6109 operated by the control signal from the control circuit 6117.
Are input and modulated.

The outputs from the modulation circuits 6102 and 6103 are input to a two-multiplex filter bank 6110, and are up-sampled for each input signal, band-limited by filters having different passbands, and then synthesized by a synthesizer. Outputs from the modulation circuits 6104 and 6105 are input to the two-multiplex filter bank 6111, and are up-sampled for each input signal, band-limited by filters having different passbands, and then synthesized by a synthesizer.

The outputs from the modulation circuits 6106 and 6107 are input to the two-combination filter bank 6112, are up-sampled for each input signal, are band-limited by filters having different passbands, and are then synthesized by the synthesizer. The outputs from the modulation circuits 6108 and 6109 are input to the two-multiplexing filter bank 6113, up-sampled for each input signal, band-limited by filters having different passbands, and then synthesized by a synthesizer.

Two multiplexing filter banks 6110, 6111
Is input to a two-multiplexing filter bank 6114, and is up-sampled for each signal, band-limited by filters having different passbands, and then synthesized by a synthesizer.
The outputs from the two-multiplexing filter banks 6112 and 6113 are input to the two-multiplexing filter bank 6115, and are up-sampled for each signal, band-limited by filters having different passbands, and then synthesized by a synthesizer.

Two multiplexing filter banks 6114, 6115
Are input to a two-combination filter bank 6116, up-sampled for each signal, band-limited by filters having different passbands, and then synthesized by a synthesizer.
An output signal from the two-multiplex filter bank 6116 is input to the transmission circuit 6118 and transmitted from the antenna.

Next, the receiving apparatus will be described with reference to FIG. Numerals 6201 to 6207 in FIG. 9 denote a two-segment filter bank, 6208 to 6215 a demodulation circuit, and 62
16 is a parallel-to-serial conversion circuit, 6217 is a control circuit, 6218
Represents a receiving circuit. FIG. 39 shows an example of the configuration of the half-wave filter bank. In FIG.
1, 6902 are digital filters, 6903, 690
Reference numeral 4 denotes a downsampler.

Digital filters 6901 and 6902
Are filters having different passbands, and are described in the above-mentioned embodiments 1-1 to 1-4, or in the above-mentioned document "Kazuhiro Tanabe," Proposal of Seamless Multirate Filter Bank ", IEICE Technical Report SAT99. -14 ".

In FIG. 32, a signal received by an antenna is input to a receiving circuit 6218. Receiver circuit 6218
Is input to the bi-wave filter bank 6201.

The signal input to the binary filter bank 6201 is branched into two, band-limited by filters having different pass bands, down-sampled, and output. One of the outputs from the halving filter bank 6201 is input to the halving filter bank 6202. The signal input to the splitter filter bank 6202 is split into two, band-limited by filters having different passbands, and after downsampling, output.

The other of the outputs from the binary filter bank 6201 is input to the binary filter bank 6203. The signal input to the halving filter bank 6203 is split into two, band-limited by filters having different passbands, down-sampled, and output. One of the outputs from the splitter filter bank 6202 is input to the splitter filter bank 6204.

The signal input to the binary filter bank 6204 is split into two, band-limited by filters having different passbands, down-sampled, and output. The other of the outputs from the halving filter bank 6202 is input to the halving filter bank 6205. The signal input to the splitter filter bank 6205 is split into two, band-limited by filters having different passbands, downsampled, and output.

One of the outputs from the binary filter bank 6203 is input to the binary filter bank 6206. The signal input to the splitter filter bank 6206 is split into two, band-limited by filters having different passbands, downsampled, and output. The other of the outputs from the two-half filter bank 6203 is input to the two-half filter bank 6207.

The signal input to the splitter filter bank 6207 is split into two, band-limited by filters having different passbands, down-sampled, and output. One of the outputs from the splitter filter bank 6204 is input to the demodulation circuit 6208 and demodulated, and the other is input to the demodulation circuit 6209 and demodulated. One of the outputs from the halving filter bank 6205 is a demodulation circuit 6210
And demodulated, and the other is input to the demodulation circuit 6211 and demodulated.

One of the outputs from the binary filter bank 6206 is input to the demodulation circuit 6212 and demodulated, and the other is input to the demodulation circuit 6213 and demodulated. One of the outputs from the halving filter bank 6207 is
214 and demodulated, and the other is demodulated by a demodulation circuit 6215
And demodulated. Out of the demodulation circuits 6208 to 6215 operated by the control signal from the control circuit 6217, outputs from up to eight systems are input to the parallel / serial conversion circuit 6216. The parallel data of up to eight systems input to the parallel-serial conversion circuit 6216 is converted into one system of time-series data and output.

The control circuit 6217 controls the operation / stop of each of the demodulation circuits 6208 to 6215. Further, the control circuit 6217 controls the parallel / serial conversion circuit 6216
The conversion control is performed when the eight low-speed signals (data) input from the demodulation circuits 6208 to 6215 are converted into one system of serial (time series) signals.

FIGS. 42A and 42B show examples of output frequency spectra of the present embodiment when signals having transmission rates of 7 Fb and 5 Fb are input. FIG.
Ch1 shown in (a) and (b) indicates that the modulation circuit 6102
h2 denotes a modulation circuit 6103, and Ch3 denotes a modulation circuit 6104.
Ch4 is a modulation circuit 6105, and Ch5 is a modulation circuit 6105.
106, Ch6 is a signal passing through the modulation circuit 6107, Ch7 is a signal passing through the modulation circuit 6108, and Ch8 is a signal passing through the modulation circuit 6109.

As shown in FIGS. 42A and 42B, in this embodiment, the transmission rate is made variable by using a number of low-speed modulation signals proportional to the transmission rate. Further, by selecting the frequency-dividing filter bank and the frequency characteristics and connection relation of the frequency-dividing filter bank as shown in FIG. 47, mutual interference does not occur between a plurality of low-speed signals.

This is described in the above-mentioned document “Kazuhiro Tanabe,“ Proposal of Seamless Multirate Filter Bank ””, IEICE Technical Report S
AT99-14 ". Therefore, unused low-speed signals such as Ch6 to Ch8 in FIG.
Since it can be used for transmission from other transmitting stations, the frequency utilization efficiency can be increased.

(2-2nd Embodiment) The 2nd embodiment of the present invention.
FIGS. 33 and 34 show the second embodiment. FIG. 33 is a block diagram illustrating an example of a configuration of a transmission device of the digital signal transmission device, and FIG. 34 is a block diagram illustrating an example of a configuration of a reception device of the digital signal transmission device. The digital signal transmission device according to the present invention includes at least one transmitting device and one receiving device. The digital signal transmission apparatus shown in FIGS. 33 and 34 shows a configuration example in the case where the number of carrier waves used is a maximum of four.

In FIG. 33, numeral 6301 is a serial-parallel conversion circuit, 6302 to 6305 are modulation circuits, and 6306
Reference numerals 6308 to 6308 denote two-multiplex filter banks, 6309 denotes a control circuit, and 6310 denotes a transmission circuit. The two-multiplex filter bank is the same as that used in the first example of the embodiment described above. The input data is transmitted to the control circuit 6
The parallel / parallel conversion circuit 6301 controlled by the control signal from the 309 controls the parallel data S1, S2, S3,
Converted to S4.

The parallel data S1 is 4Fb, S2 is 2Fb,
S3 and S4 are Fb. Parallelized data S
1, S2, S3 and S4 are controlled by a control signal from a control circuit 6309. S1 is a modulation circuit 6302, S2 is a modulation circuit 6303, S3 is a modulation circuit 6304, and S4 is input to a modulation circuit 6305 and becomes a modulation signal. . However, the modulation circuit 6302 operates at four times the speed of the modulation circuits 6304 and 6305 by the control signal of the control circuit 6309, and the modulation circuit 6303 operates at the modulation circuits 6304 and 63
It operates at twice the speed of 05.

Here, the control circuit 6309 sends an input signal to the serial / parallel conversion circuit 6301 to the data S1
To S4 to control the modulation circuit to output each data, and the output timing. The control circuit 6309 controls the operation / stop of each of the modulation circuits 6302 to 6305.

Modulating circuit 6304 and modulating circuit 630
The output of 5 is input to the two-multiplex filter bank 6306. The input data is up-sampled by a factor of two and then band-limited by filters having different pass bands before being output. The outputs of the modulation circuit 6303 and the two-multiplex filter bank 6306 are
307, each of which is up-sampled by a factor of two and band-limited by filters having different pass bands, then synthesized by a synthesizer and output.

The outputs of the modulation circuit 6302 and the two multiplexing filter bank 6307 are
Is input to The input data is upsampled by a factor of two and band-limited by filters having different passbands, and then synthesized by a synthesizer and output. 2
The output from the multiplexing filter bank 6308 is
After input to 310, it is transmitted from the antenna.

Next, the receiving apparatus shown in FIG. 34 will be described. In FIG. 34, reference numerals 6401 to 6403 denote two-half-wave filter banks, 6404 to 6407 denote demodulation circuits, and 6408.
Is a parallel-to-serial conversion circuit, 6409 is a control circuit, and 6410 is a receiving circuit. The demodulation circuits 6404 to 6407 and the parallel / serial conversion circuit 6408 are controlled by a control circuit 6409. The two-half filter bank is the second-half filter bank described above.
This is the same as that used in the first embodiment. The signal received from the antenna is input to the reception circuit 6410.

The output from the receiving circuit 6410 is input to the halving filter bank 6401. The signal input to the two-segment filter bank 6401 is split into two signals, band-limited by filters having different pass bands, down-sampled, and output. One of the outputs from the half-wave filter bank 6401 is a half-wave filter bank 6
It is input to 402.

[0131] The signal input to the binary filter bank 6402 is split into two signals, each of which is band-limited by a filter having a different pass band, down-sampled and output. The other of the outputs from the halving filter bank 6401 is input to the demodulation circuit 6404. Demodulation circuit 64
The signal input to 04 is demodulated into a demodulated signal, which is input to the parallel-to-serial conversion circuit 6408. However, the demodulation circuit 64
04 operates at four times the speed of the demodulation circuit 6406.

One of the outputs from the binary filter bank 6402 is input to the demodulation circuit 6405. Demodulation circuit 6
The signal input to 405 is demodulated into a demodulated signal, and input to the parallel-to-serial conversion circuit 6408. The other of the outputs from the halving filter bank 6402 is input to the halving filter bank 6403. Two-wave filter bank 640
The signal input to 3 is split into two, and after being band-limited by filters having different pass bands, down-sampled and output.

One of the outputs of the two-wave filter bank 6403 is input to the demodulation circuit 6406, and after demodulation, is input to the parallel / serial conversion circuit 6408. The other is a demodulation circuit 6407
And demodulated, and then input to the parallel-to-serial conversion circuit 6408. The parallel data input to the parallel-to-serial conversion circuit 6408 is converted into one-system time-series data and output.

Here, the control circuit 6407 controls the operation / stop of each of the demodulation circuits 6404 to 6406. Also,
The control circuit 6407 sends the low-speed signals (data) input from the demodulation circuits 6404 to 6406 to the parallel-to-serial conversion circuit 6408 in three different low-speed signals of Fb, 2Fb, and 4Fb in one system. Series (time series)
Controls conversion when converting to signals.

FIGS. 43A and 43B show examples of output frequency spectra of the present embodiment when signals having transmission rates of 7 Fb and 5 Fb are input. Ch1 shown in FIGS. 43A and 43B is a modulation circuit
h2 denotes a modulation circuit 6303, and Ch3 denotes a modulation circuit 6304.
And Ch4 is a signal that has passed through the modulation circuit 6305. As shown in (a) and (b) of FIG. 43, in the example of the present embodiment, appropriate Ch1,
The transmission rate can be made variable by selecting Ch2, Ch3, and Ch4.

FIGS. 43A and 43B are examples in which the input low-speed signals are all different. Therefore, FIG.
The digital signal transmitting devices and digital signal receiving devices of the number 34 are examples of a configuration corresponding to a case where the speeds of the low speed signals are all different. The digital signal transmitting apparatus of FIG. 34 and the digital signal receiving apparatus of FIG. 33 are one configuration example in which the speeds of a plurality of low-speed signals are different, such as Fs, 2Fs, and 4Fs.

The cascade connection of the two multiplexing filter banks in the digital signal receiving apparatus of FIG. 33 is not limited to FIG. For example, when attention is paid only to the cascade connection of the two multiplex filter banks, the cascade connection of the two multiplex filter banks may be any of FIG. 54 to FIG.
Similarly, the cascade connection of the half-wave filter banks in the digital signal receiving apparatus of FIG. 34 is not limited to FIG. For example, when attention is paid only to the cascade connection portion of the two-wave filter bank, the cascade connection of the two-wave filter banks may be any of FIG. 59 to FIG.

(Embodiment 2-3) Embodiment 2 of the present invention
FIGS. 35 and 36 show a third embodiment. FIG. 35 is a block diagram illustrating an example of a configuration of a transmission device of the digital signal transmission device, and FIG. 36 is a block diagram illustrating an example of a configuration of a reception device of the digital signal transmission device. The digital signal transmission device according to the present invention includes at least one transmitting device and one receiving device. The digital signal transmission apparatus shown in FIGS. 35 and 36 shows an example of a configuration in which a maximum of four carrier waves are used.

In FIG. 35, numeral 6501 denotes a time division modulation circuit, 6502, 6503, and 6504 denote two multiplexing filter banks, and 6505 denotes a control circuit. FIG. 45 shows the configuration of the time division modulation circuit 6501. In the figure, reference numeral 7501 denotes a modulation circuit, and reference numeral 7502 denotes a switch. The two-multiplex filter bank is the same as that shown in the first example of the embodiment described above. The input data is modulated by the time division modulation circuit 6501 controlled by the control circuit 6505. Here, the control circuit 65
Reference numeral 05 controls the time-division modulation circuit 6501 to rearrange serial input signals into parallel signals, the order and number of modulation processes for the rearranged signals, and the output destination.

At this time, the time division modulator 6501 operates as shown in FIG.
Of the output T1 and the output T1 at the timing shown in FIG.
2. Output signals of up to four systems of output T3 and output T4. In FIG. 37, D1 to D8 are data input in the order of subscripts, and M1 to M18 are modulated signals obtained by modulating D1 to D8. Since the modulation signal is output at the timing shown in FIG. 37, the output T1 is 4 Fb, T2 is 2 Fb, T
3 and T4 will be the speed of Fb.

The output T3 and the output T4 are input to the two-multiplex filter bank 6502, respectively, are up-sampled by two times, and are band-limited by filters having different pass bands, and then are synthesized and output by the synthesis circuit. . The output T2 and the output of the two multiplexing filter bank 6502 are 2
The signals are input to a multiplexing filter bank 6503, each of which is up-sampled by a factor of two, band-limited by filters having different pass bands, and then synthesized and output by a synthesis circuit. Output T1, and two multiplexing filter bank 6
The output of 503 is input to a two-multiplex filter bank 6504. The input signals are up-sampled by a factor of two, band-limited by filters having different pass bands, output, and then synthesized and output by a synthesis circuit.
The output from the two-multiplex filter bank 6504 is input to the transmission circuit 6506 and transmitted from the antenna.

Next, the receiving apparatus shown in FIG. 36 will be described. In FIG. 36, the numerals 6601 to 6603 are 2
A demultiplexing filter bank, 6604 is a time division demodulation circuit,
05 represents a control circuit. Time division demodulation circuit 6604
46 is shown in FIG. In FIG.
1 is a switch and 7602 is a demodulation circuit. The half-wave filter bank is the same as that shown in the first example of the embodiment described above. A signal received from the antenna is input to the receiving circuit 6606.

The output from the receiving circuit 6606 is input to the two-wave filter bank 6601. The signal input to the divide-by-2 filter bank 6601 is branched into two, and after being band-limited by filters having different pass bands,
Downsampled and output. One of the outputs from the splitter filter bank 6601 is input to the splitter filter bank 6602. Two-wave filter bank 6601
Is input to the time-division demodulation circuit 6604.

[0144] The signal input to the two-wave filter bank 6602 is split into two, band-limited by filters having different pass bands, down-sampled and output. One of the outputs from the half-wave filter bank 6602 is input to the half-wave filter bank 6603.
The other of the outputs from the half-wave filter bank 6602 is input to the time division demodulation circuit 6604.

The signal input to the two-wave filter bank 6603 is branched into two, band-limited by filters having different pass bands, down-sampled and output. One and the other of the outputs from the half-wave filter bank 6603 are input to the time division demodulation circuit 6604. A signal input to the time-division demodulation circuit 6604 is demodulated by a control signal from the control circuit 6605 and output.

The control circuit 6605 controls the operation / stop of each of the demodulation circuits 6601 to 6603. Also,
The control circuit 6605 is a low-speed signal (data) input from each of the two-half-wave filter banks 6601 to 6603 to the time-division modulation / demodulation circuit 6604, and includes Fb, 2F
Control is performed to correctly rearrange and demodulate the order of three different low-speed signals, b and 4Fb, and to convert them into a single system of serial (time series) signals.

FIGS. 44 (a) and (b) show output frequency spectra of an example of the present embodiment when signals having transmission rates of 7 Fb and 5 Fb are input. Ch1 shown in FIGS. 44A and 44B is a time-division modulation circuit 6502.
Are output T1 and Ch2 of the time-division modulation circuit 6502.
2, Ch3 corresponds to the output T3 of the modulation circuit 6502, and Ch4 corresponds to the output T4 of the modulation circuit 6502. As shown in FIGS. 44 (a) and (b), in the present embodiment, appropriate Ch1, Ch2, Ch3,
The transmission speed can be made variable by selecting and Ch4.

FIGS. 44A and 44B are examples in which all input low-speed signals are different. Therefore, FIG.
5, 36 digital signal transmitting apparatuses and digital signal receiving apparatuses are one example of a configuration corresponding to a case where the speeds of low-speed signals are all different. Further, the digital signal transmitting apparatus of FIG. 35 and the digital signal receiving apparatus of FIG. 36 are one configuration example in which the speeds of a plurality of low-speed signals are different like Fs, 2Fs, and 4Fs.

The cascade connection of the two multiplexing filter banks in the digital signal receiving apparatus of FIG. 35 is not limited to FIG. For example, when attention is paid only to the cascade connection portion of the two multiplexing filter banks, the cascade connection of the two multiplexing filter banks may be any of FIG. 53 to FIG. Similarly, the cascade connection of the two-half filter banks in the digital signal receiving apparatus of FIG. 36 is not limited to FIG. For example, when attention is paid only to the vertical connection portion of the two-half filter bank, any of the vertical connection diagrams of FIG. 58 to FIG. 62 of the two-half filter bank may be used. That is,
By appropriately controlling the signal speed and output destination of the low-speed signal output from the time-division modulation circuit 6501, and the rearrangement and demodulation speed of the low-speed signal input to the time-division demodulation circuit, various cascade connections can be performed. Can respond to.

(2-4th Embodiment) The digital signal transmission apparatus according to the 2-4th embodiment is an input / output target for the digital signal transmission apparatus shown in the 2-3rd embodiment. It is configured to handle a plurality of serial signals. Hereinafter, only differences from the digital signal transmission device shown in the 2-3 will be described.

FIG. 48 shows a digital signal transmitting apparatus according to the present embodiment. 35 is different from the digital signal transmitting apparatus of FIG.
01 is a multi-input multi-output serial-parallel conversion circuit 8001 and a multi-input multi-output time-division modulation circuit 8002. Thus, the digital signal transmitting apparatus of FIG. 48 can perform processing on a plurality of serial signals (time-series data).

Note that the control circuit 8003 provides the multi-input multi-output serial-parallel conversion circuit 8001 with a process of converting a plurality of input serial signals into a plurality of low-speed signals and outputting the converted low-speed signals. Perform the preceding control. Further, the control circuit 8003 controls the low-speed signal to be modulated and the modulation timing for the time division modulation circuit 8002.

FIG. 49 shows a digital signal receiving apparatus according to the present embodiment. 36 is different from the digital signal receiving apparatus shown in FIG.
04 is a multi-input multi-output time-division demodulation circuit 8101 and a multi-input multi-output parallel-serial conversion circuit 8102. Thereby, the digital signal receiving apparatus of FIG. 49 can demodulate into a plurality of serial signals (time-series data). Further, the digital signal receiving apparatus of FIG. 49 includes a multi-input multi-output time-division modulation circuit 8103 at the subsequent stage of the multi-input multi-output parallel-serial conversion circuit 8102. Thus, the demodulated signal output from the multi-input multi-output parallel-serial conversion circuit 8102 can be output as a modulated signal according to the device (application) to which the signal is output. For example, an example of an application is a digital television (DVB: Digi
tal Video Broadcasting), the time-division modulation circuit 8
103 is a modulation circuit for DVB. In addition, the control circuit 8104 performs a process of converting a plurality of input low-speed signals into a single system of time-series digital signals in a correct combination to the multi-input multi-output parallel-serial conversion circuit 8102, and a plurality of time-series digital signals. Output control. The control circuit 8104 controls the time-division demodulation circuit 8101
It controls the serial signal to be demodulated and the demodulation timing. The control circuit 8104 includes a time-division modulation circuit 81
03, which input signal is to be modulated at which timing.

Next, the operation of the digital signal receiving apparatus of FIG. 49 will be described. Note that the operation up to the time-division demodulation circuit 8101 is only the output of one or a plurality of outputs of the time-division demodulation circuit 8101, and thus the subsequent operation will be described. The outputs from the time-division demodulation circuit are all input to the multi-input multi-output parallel-serial conversion circuit 8102 as a plurality of low-speed signals (A to H) at the same speed. The multi-input multi-output parallel-serial conversion circuit 8102 converts the input plurality of low-speed signals into an original system of time-series signals and outputs the signals. Here, the multi-input multi-output parallel-serial conversion circuit 8102 includes, for example, one system of signals A, C, E, and G, one system of signals B and D, one system of signal F, and one system of signal H. Output as a signal. Multi-input multi-output parallel-serial conversion circuit 810
2 are output from the time-division modulation circuit 810
3 is input. The time-division modulation circuit 8103 modulates the signals and outputs the modulated signals as modulated signals having four different bandwidths. (1), (2), and (3) in FIG. 50 are examples of signals at positions indicated by α, β, and ε in FIG. 49, respectively. FIG. 50 (1) shows an input signal to the first-stage two-wave filter bank. (2) of FIG. 50 shows a signal after channel demultiplexing, and (3) of FIG. 20 shows modulated signals of four systems having different bandwidths.

The channel multiplexing circuit 8004 shown in FIG.
Is not limited to FIG. 48. For example, when attention is paid only to the cascade connection of the two multiplex filter banks, the cascade connection of the two multiplex filter banks may be any of FIG. 54 to FIG. Similarly, the cascade connection of the two-segment filter banks in the channel separation circuit 8105 in FIG. 49 is not limited to FIG. For example, when attention is paid only to the cascade connection portion of the two-wave filter bank, the cascade connection of the two-wave filter banks may be any of FIG. 59 to FIG.

Next, an application example of the digital signal transmission apparatus according to the second to fourth embodiments will be described with reference to FIGS. In this application example, the transmission devices 8201 to 82
The digital signal transmission apparatus provided with each of the receivers 03 and 03 transmits an input signal using a different system bandwidth, and the digital signal transmission apparatus provided with the receiver 8204 outputs a modulated signal for the different system bandwidths. . 51 and 52, reference numerals 8211 to 8213
Is a transmission signal from a digital signal transmission device provided with each of the transmission devices 8201 to 8203, and this transmission signal is transmitted to the artificial satellite 8205. The artificial satellite 8205 that has received these transmission signals broadcasts them as a signal indicated by reference numeral 8214. The digital signal transmission device including the receiving device 8204 receives the broadcasted signal 8214, converts the signal into a time-series signal 8215 of each system, and modulates the signal 8215 into a modulated signal 8216 having three different bandwidths. Output.

In the embodiments 2-1 to 2-4, the digital signal transmitting apparatus has been described as including at least one digital signal transmitting apparatus and at least one digital signal receiving apparatus. But,
The present invention is not limited to this, and may be configured to include only one of the digital signal transmitting device and the digital signal receiving device.

Also, the 1-1 to 1-4 and 2-1
In the second to fourth embodiments, all of the filter bank, the waveform shaping filter, the modulation circuit, and the demodulation circuit, or some of the circuits may operate in a time-division manner. For example, a digital signal demultiplexer shown in FIG. 1 will be described as an example. The first stage of the digital signal demultiplexer
Assuming that the operating frequency of the demultiplexing filter bank 102 is α,
The operation speed of the second-stage splitter filter banks 103 and 104 is α / 2, the operation speed of the third-stage splitter filter banks 105 to 108 is α / 8, and the waveform shaping filter 2091.
The operation speed of each filter in the stage indicated by ２０2098 is α /
It becomes 8. For example, the second-stage two-wave filter bank 10
Reference numerals 3 and 104 denote one two-wave filter bank A, and a memory for storing data to be processed by the two-wave filter banks 103 and 104 is further provided. Also, the operating speed of the splitter filter bank A is α. At this time, the two-branch filter bank A switches the address of the memory area in which the data to be processed is stored in a time-sharing manner in accordance with an instruction from a control circuit (not shown), and processes each data,
The processing of the demultiplexing filter banks 103 and 104 can be performed by time division. Similarly, the third-stage second-half filter bank 10
5 to 108 are replaced by one half-wave filter bank B, the operation speed is set to α, and a predetermined memory area is provided. At this time, the two-branch filter banks B perform time-division processing to perform two-branch filter banks 105 to 1.
08 can be performed. Also, the waveform shaping filter 2091
Replace ~ 20983 with one waveform shaping filter C,
The operation speed is α, and a predetermined memory area is provided. At this time, the waveform shaping filter C can perform the processing of the waveform shaping filters 2091 to 2098 by performing the time division processing.

Similarly, in the other devices shown in the embodiments, the number of circuits can be reduced in each stage of the digital processing circuit and the operation speed can be increased, so that the time division processing T can be performed.

In addition, the 1-1 to 1-4 and 2-1
In the second to fourth embodiments, an example is described in which the cascade connection of the multiplexing and demultiplexing filter banks is three, but the number of cascade connections is not limited to this.

In addition, the 1-1 to 1-4 and 2-1
In the second to fourth embodiments, when the sampling rate fs of the filters included in each filter bank is set as
An example of four types of filters whose passband is included in fs has been described, but the present invention is not limited to this. The type of filter whose passband is included in fs is not limited to this, and a filter bank may be configured using, for example, eight, sixteen,... Filters. Note that the configuration of the filter bank and the relationship between these cascade connections are in a range that can be inferred from the case of four types of filters, and thus description thereof will be omitted.

In addition, 1-1 to 1-4 and 2-1
In the second to fourth embodiments, the digital signal after A / D conversion or the digital signal before D / A conversion has been described as being processed by the digital signal processing circuit. The processing of the digital signal is not limited to this, and all or some of the functions of each digital circuit may be software processing using a CPU or a DSP. In this case, the program for software processing includes an RO that constitutes a digital signal demultiplexer, a digital signal multiplexer, a digital signal transmitter, a digital signal transmitter, or a digital signal receiver.
It is stored in a recording medium such as M.

The embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiments, and the design and the like within the scope of the present invention are not limited. Is also included.

[0164]

As described above, the digital signal demultiplexing apparatus of the present invention uses four types of filters having different passbands for the frequency-multiplexed reception signal, thereby causing interference due to aliasing and joints between the filters. Demultiplexing can be performed without being affected by distortion.

Further, the digital signal multiplexing apparatus of the present invention can multiplex different transmission signals by using four types of filters having different passbands without being affected by interference due to aliasing and distortion due to joints between filters. Can be multiplexed in frequency.

Further, the digital signal demultiplexing apparatus and the digital signal multiplexing apparatus according to the present invention provide the filters A, B,
By making the impulse responses of C and D satisfy a predetermined calculation formula, the two-branch filter bank and the two-multiplex filter bank can be configured with the same calculation amount as the FIR filter of the real coefficient. Therefore, it is possible to realize a digital signal demultiplexing device and a digital signal multiplexing device that have a small device size and low power consumption.

Further, as described above, the digital signal transmission apparatus of the present invention can realize a digital signal transmission apparatus that has a high frequency utilization efficiency with a simple apparatus configuration and that enables a variable transmission rate. it can.

The digital signal transmission device according to the present invention
There is an advantage that the transmission rate can be made variable by selecting an appropriate modulation circuit according to the input transmission rate.

Further, the digital signal transmission device of the present invention
By using four filters having different passbands in signal multiplexing, it is possible to multiplex signals without being affected by aliasing and amplitude distortion when frequency-multiplexing each channel.

The digital signal transmission device according to the present invention
By using four filters with different passbands in signal multiplexing, when demultiplexing a frequency-multiplexed signal into each channel, the signal is separated without being affected by interference due to aliasing or amplitude distortion. Can wave.

Further, in the digital signal transmission apparatus of the present invention, since the speeds of the plurality of low-speed signals are different, the number of the modulation / demodulation circuits can be reduced as compared with the case where a constant-speed modulation / demodulation circuit is used.

Further, the digital signal transmission apparatus of the present invention is configured to cope with the case where the speeds of the low-speed signals input to the circuit for performing channel multiplexing are all different.
There is an advantage that the number of modulation circuits for obtaining the same transmission rate can be minimized.

Further, the digital signal transmission apparatus of the present invention is configured so as to cope with a case where output signals from circuits for performing channel demultiplexing are all mixed with low-speed signals of different speeds, so that the same transmission rate can be obtained. There is an advantage that the number of demodulation circuits to be obtained can be minimized.

In the digital signal transmission apparatus of the present invention, the sampling rates of the modulation circuit, the two multiplexing filter bank, the two-branch filter bank, and the demodulation circuit are different.
In addition, taking advantage of the fact that the lower the sampling speed, the greater the number of systems, the slower processing of multiple systems is executed in a time-division manner by a single higher-speed processing circuit. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a digital signal demultiplexing device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a digital signal demultiplexing apparatus according to a first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a digital signal multiplexer according to a first to third embodiments of the present invention;

FIG. 4 is a diagram illustrating a configuration example of a digital signal multiplexing device according to a first to fourth exemplary embodiments of the present invention.

FIG. 5 is a diagram illustrating frequency characteristics of a filter.

FIG. 6 is a timing chart of 1/2 down sampling.

FIG. 7 is a diagram (part 1) showing a spectrum in each state of FIG. 1;

FIG. 8 is a diagram (part 2) showing a spectrum in each state of FIG. 1;

FIG. 9 is a diagram (part 3) showing a spectrum in each state of FIG. 1;

FIG. 10 is a diagram (part 1) showing a spectrum in each state of FIG. 2;

FIG. 11 is a diagram (part 2) showing the spectrum in each state of FIG. 2;

FIG. 12 is a timing chart of double upsampling.

FIG. 13 is a diagram (part 1) showing a spectrum in each state of FIG. 3;

FIG. 14 is a diagram (part 2) showing the spectrum in each state of FIG. 3;

FIG. 15 is a diagram (part 3) showing a spectrum in each state of FIG. 3;

FIG. 16 is a diagram (part 4) showing the spectrum in each state of FIG. 3;

17 is a diagram (No. 1) showing a spectrum in each state of FIG. 4;

FIG. 18 is a diagram (part 2) showing the spectrum in each state of FIG. 4;

19 is a view (No. 3) showing a spectrum in each state of FIG. 4;

FIG. 20 is a diagram showing a first example of a conventional digital signal demultiplexer.

FIG. 21 is a diagram illustrating a second example of a conventional digital signal demultiplexer.

FIG. 22 is a diagram illustrating an example of a frequency-multiplexed signal.

FIG. 23 is a diagram (part 1) showing a spectrum in each state of FIG. 20;

FIG. 24 is a diagram (part 2) showing the spectrum in each state of FIG. 20;

FIG. 25 is a diagram illustrating an example of an input signal.

26 is a diagram (part 1) showing a spectrum in each state of FIG. 21;

FIG. 27 is a diagram (part 2) showing the spectrum in each state of FIG. 21;

FIG. 28 is a diagram (part 3) showing the spectrum in each state of FIG. 21;

FIG. 29 is a diagram illustrating frequency characteristics of an ideal rectangular filter.

FIG. 30 is a diagram showing frequency characteristics of a conventional high-pass filter and low-pass filter.

FIG. 31 is a diagram illustrating a transmission device according to a 2-1 embodiment of the present invention.

[Fig. 32] Fig. 32 is a diagram illustrating a receiving device according to Embodiment 2-1 of the present invention.

FIG. 33 is a diagram illustrating a transmission device according to a second embodiment of the present invention.

FIG. 34 is a diagram illustrating a receiving device according to a second embodiment of the present invention.

FIG. 35 is a diagram illustrating a transmission device according to a second to third embodiments of the present invention.

FIG. 36 is a diagram illustrating a receiving device according to a second to third embodiments of the present invention.

FIG. 37 is a diagram showing a timing of outputting a signal.

FIG. 38 is a diagram illustrating an example of a configuration of a two-wave filter bank.

FIG. 39 is a diagram illustrating an example of a configuration of a two-wave filter bank.

FIG. 40 is a diagram illustrating an example of a configuration of a conventional transmission device.

FIG. 41 is a diagram illustrating an example of a configuration of a conventional receiving device.

FIG. 42 is a diagram illustrating an output frequency spectrum according to Embodiment 2-1 of the present invention;

FIG. 43 is a diagram illustrating an output frequency spectrum according to the second embodiment of the present invention.

FIG. 44 is a diagram illustrating an output frequency spectrum according to the second to third embodiments of the present invention.

FIG. 45 is a diagram illustrating an example of a configuration of a time division modulation circuit.

FIG. 46 is a diagram illustrating an example of a configuration of a time division demodulation circuit.

FIG. 47 is a diagram illustrating frequency characteristics of a filter.

FIG. 48 is a diagram illustrating a transmission device according to a second to fourth embodiments of the present invention.

FIG. 49 is a diagram illustrating a receiving device according to a second to fourth embodiments of the present invention.

FIG. 50 is a diagram illustrating a frequency spectrum of each unit according to the second to fourth embodiments of the present invention.

FIG. 51 is a diagram for describing an application example of the digital signal transmission device according to the second to fourth embodiments of the present invention.

FIG. 52 is a diagram for describing an application example of the digital signal transmission device according to the second to fourth embodiments of the present invention.

FIG. 53 is a diagram illustrating an example of a cascade connection of two multiplexing filter banks.

FIG. 54 is a diagram illustrating an example of a cascade connection of two multiplexing filter banks.

FIG. 55 is a diagram illustrating an example of a cascade connection of two multiplexing filter banks.

FIG. 56 is a diagram showing an example of a cascade connection of two multiplexing filter banks.

FIG. 57 is a diagram illustrating an example of a cascade connection of two multiplexing filter banks.

FIG. 58 is a diagram showing an example of a cascade connection of a two-wave filter bank.

FIG. 59 is a diagram illustrating an example of a cascade connection of a two-wave filter bank.

FIG. 60 is a diagram showing an example of a cascade connection of a two-wave filter bank.

FIG. 61 is a diagram illustrating an example of a cascade connection of a two-wave filter bank.

FIG. 62 is a diagram illustrating an example of a cascade connection of a two-half filter bank.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 100 Detector 101 A / D converter, 102-108 2-branch filter bank 1021,1031,1051,1071 1st filter 1022,1032,1052,1072 2nd filter 1041,1061,1081 3rd filter 1042,1062, 1082 fourth filter 1023, 1024, 1033, 1034, 1043,
1044, 1053, 1054, 1063, 1064,
1073, 1074, 1083, 1084 Downsampler 200 Quadrature detector, 2011, 2012 A / D converter, 202 4-branch filter bank 203-206 2-branch filter bank 2021, 2031, 2051 First filter 2022, 2032, 2052 Second filter 2023, 2041, 2061 Third filter 2024, 2042, 2062 Fourth filter 2025 to 2028, 2033, 2034, 2043,
2044, 2053, 2054, 2063, 2064
Down samplers 2071-2078, 2091-2098 Waveform shaping filters 301-307 2 multiplexing filter banks 308 D / A converters 309 Modulators 3011, 3012, 3021, 3022, 3031,
3032, 3041, 3042, 3051, 3052,
3061, 3062, 3071, 3072 Upsampler, 3013, 3033, 3053, 3073 First filter 3014, 3034, 3054, 3074 Second filter bank 3023, 3043, 3063 Third filter 3024, 3044, 3064 Fourth filter 3015, 3025 , 3035, 3045, 3055,
3065, 3075 adders 3091 to 3098, 3101 to 3108 waveform shaping filters 401 to 404 2 multiplexing filter banks 406, 407 D / A converters 408 quadrature modulators 4011, 4012, 4021, 4022, 4031,
4032, 4041, 4042, 4051, 4052,
4053, 4054 Upsampler 4013, 4033, 4055 First filter 4014, 4034, 4056 Second filter 4015, 4025, 4035, 4045, 4059
Adders 4023, 4043, 4057 Third filters 4024, 4044, 4058 Fourth filters 6101, 6301 Serial / parallel conversion circuits 6101-6109, 6302-6305 Modulation circuits 6110-6116, 6306-6308 6502
6504 2 combining filter banks 6117, 6217, 6309, 6409, 6505,
6605, 8003 Control circuits 6118, 6310, 6506 Transmission circuits 6201-6207, 6401-6403, 6601
6603 2 branching filter bank 6208-6215, 6404-6407 demodulation circuit 6216, 6408 parallel-serial conversion circuit 6218, 6410, 6606 reception circuit 6501, 8002, 8103 time division modulation circuit 6604, 8101 time division demodulation circuit 6803, 6804 up sampler 6801, 6802, 6901, 6902 Digital filter 6903, 6904 Downsampler 8001 Multi-input multi-output serial-parallel conversion circuit 800
4 channel multiplexing circuit 8105 channel demultiplexing circuit 8102 multi-input multi-output parallel-serial conversion circuit

Continuation of the front page (72) Inventor Hiroshi Kazama 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5K004 AA04 EG11 EG12 5K022 AA03 AA10 AA16 AA26 AA41 5K041 AA02 CC07 FF02 FF03 FF27 FF32 HH41 JJ11 JJ30 JJ32

Claims (24)

[Claims] 1. A digital signal demultiplexer including a band splitter filter bank configured by cascade-connecting two splitter filter banks, wherein the splitter filter bank includes a filter for limiting a pass band. The sampling frequency of the output signal from the filter
The two-segment filter bank has a sampling rate of an input signal in each of the two-segment filter banks as fs, and the four types of filters whose passbands are included in fs are assigned A from the lower frequency. , B, C, and D, either a first two-branch filter bank including at least one of the filters A and B, or a second two-branch filter bank including at least one of the filters C and D The connection of the two-segment filter bank is such that the next-stage two-segment filter bank of the signal that has passed through the filter A is the first two-segment filter bank, and has passed through the filter B. The second-half filter bank at the next stage of the signal is the second two-wave filter bank, and the second-half filter bank at the next stage of the signal that has passed through the filter C is the previous one. A digital signal demultiplexing device, which is a first two-branch filter bank, wherein the next two-branch filter bank of a signal passed through the filter D is the second two-branch filter bank. . 2. The two-branch filter bank, wherein the signal that has passed through the filter A is input to the first two-branch filter bank, or the signal of the two-branch filter bank including the filter A A signal output as a signal having a sampling rate corresponding to the number of stages of the metal connection, and a signal passing through the filter B is input to the second half-wave filter bank or a two-wave filter including the filter B A signal having a sampling rate corresponding to the number of stages of the cascade connection of the bank is output, and a signal that has passed through the filter C is input to the first bi-segment filter bank, or 2 The signal that is output as a signal having a sampling rate corresponding to the number of cascade connections of the demultiplexing filter bank, and that has passed through the filter D is the second signal It is input to the 2-minute wave filter bank, or claim 1 which is output as a signal having a sampling rate corresponding to the number of stages of cascaded half wave filter bank containing the filter D
2. The digital signal demultiplexer according to claim 1. 3. A digital signal multiplexing device comprising a band combining filter bank constituted by cascading two multiplexing filter banks, wherein the two multiplexing filter banks determine a sampling frequency of an input signal and An upsampler for upsampling by a factor of two each time, a filter for filtering an output signal of the upsampler, and a means for synthesizing an output signal of each filter when there are two types of filters. The connection of the banks is such that the sampling rate of the output signal from each of the two multiplexing filter banks is fs, there are four types of filters whose passband is included in fs, and E, F, G, and H are used from the lower frequency. In this case, the output signal of the two-multiplex filter bank having at least one of the filters E and F is the two-multiplex filter filter having the filter E or G. A digital multiplexing filter bank including at least one of the filters G and H, and an output signal of the dual multiplexing filter bank including the filter F or H. Signal multiplexer. 4. The two-multiplexing filter bank, wherein an input signal to the two-multiplexing filter bank constituted by the filters E or G is a signal of the two-multiplexing filter bank including at least one of the filters E and F. An output signal or a signal having a sampling rate corresponding to the number of stages of the cascade connection of the two multiplexing filter banks constituted by the filters E or G, and to the two multiplexing filter banks constituted by the filters F or H. Is an output signal of a two-multiplex filter bank provided with at least one of the filters G and H, or a sampling according to the number of stages of the cascade connection of the two-multiplex filter bank constituted by the filters F and H. 4. The digital signal multiplexer according to claim 3, wherein the signal is a signal having a speed. 5. The first stage of the band splitting filter bank,
The digital signal demultiplexing device according to claim 1 or 2, further comprising any one or more of filters A, B, C, and D. 6. The digital signal multiplexing apparatus according to claim 3, wherein the last stage of the band synthesis filter bank includes any one or more of filters E, F, G, and H. 7. The filter A has a frequency at the lower end of the pass band equal to or higher than −fs / 4 and a frequency at the upper end of the pass band equal to or lower than fs / 2. And the frequency at the upper end of the pass band is 3 fs / 4 or less, and the frequency at the lower end of the pass band is -3 fs / 4 or more;
And a frequency at an upper end of the pass band is equal to or lower than 0, and a frequency of a lower end of the pass band is equal to or higher than -fs / 2 and a frequency of an upper end of the pass band is equal to or lower than fs / 4.
6. The digital signal demultiplexer according to any one of items 2 and 5. 8. The filter E has a frequency at the lower end of the pass band equal to or higher than −fs / 4 and a frequency at the upper end of the pass band equal to or lower than fs / 2. And the frequency at the upper end of the pass band is 3 fs / 4 or less, and the frequency at the lower end of the pass band is -3 fs / 4 or more.
And the frequency at the upper end of the pass band is equal to or lower than 0, and the frequency at the lower end of the pass band is equal to or higher than -fs / 2 and the frequency at the upper end of the pass band is equal to or lower than fs / 4.
A digital signal multiplexer according to any one of claims 4 and 6. 9. An impulse response A (n), B (n), C (n), D (n) of the filters A, B, C, D (1 ≦ n ≦ N,
where n is an integer) is the impulse response of the original filter with tap length N, I (n)
Where: (Equation 2) The digital signal demultiplexer according to claim 1, wherein the digital signal demultiplexer satisfies the following condition. 10. An impulse response E (n), F (n), G (n), H (n) of said filters E, F, G, H (1 ≦ n ≦
N, n are integers) is the impulse response of the original filter with tap length N, I (n)
Then, (Equation 4) The digital signal multiplexer according to any one of claims 3, 4, 6, and 8, wherein 11. A serial-parallel conversion means for serial-parallel conversion of an input signal into a plurality of low-speed signals, a modulation means for modulating a parallelized signal for each signal, and frequency-multiplexing and multiplexing the modulated signals. A digital signal transmitting device comprising: channel multiplexing means; and said channel multiplexing means: upsampling means for upsampling a sampling frequency of two input signals twice for each signal; And at least one two-combination filter bank comprising: two kinds of filters having different pass bands for filtering output signals of the means; and a means for combining output signals of the two kinds of filters. When the number of the two multiplexing filter banks is two or more, the configuration is such that the two multiplexing filter banks are cascaded in multiple stages. And the two outputs of each of the two modulating means are respectively input to one two-multiplexing filter bank. The two-multiplexing filter bank is divided into two, and each of the two two-multiplexing filter banks is divided into two. Is input to the next two-multiplexing filter bank, and the output of the two-multiplexing filter bank is further input to the next-stage two-multiplexing filter bank. The outputs of the two two-combination filter banks in the preceding stage are sequentially connected so that they are respectively input to the input, and the output of the one two-combination filter bank in the final stage is used as the output. Digital signal transmission device characterized by the above-mentioned. 12. The channel multiplexing unit multiplexes two or one modulation unit by frequency-multiplexing the two or one modulation unit using one of the two multiplexing filter banks. The output is multiplexed with the output of one of the other plural modulating means or the output of a different two multiplexing filter bank having the same sampling rate by the next two multiplexing filter banks. Further, the output of the two multiplexing filter bank and the output of one of the other plurality of modulating means or the output of a different two multiplexing filter bank having the same sampling rate are used in the next two multiplexing filter. 12. The digital signal transmitting apparatus according to claim 11, wherein the two multiplexing filter banks are sequentially connected so as to be multiplexed by a bank, and an output of one final two-multiplexing filter bank is used as an output of the digital signal transmitting apparatus.
A digital signal transmission device according to claim 1. 13. A channel demultiplexing means for demultiplexing a frequency-multiplexed signal into two signals, a plurality of demodulation means for demodulating an output of the channel demultiplexing means, and inputting each output of the demodulation means. A digital signal receiving apparatus comprising: a parallel / serial conversion unit; and the channel demultiplexing unit: a unit for demultiplexing an input signal into two signals by two types of filters having different passbands; Downsampling means for thinning out the sampling frequency of each of the two signals to そ れ ぞ れ, and one or more bifurcating filter banks consisting of: The channel demultiplexing means comprises: In this configuration, the output of the receiving circuit is input to the two-branch filter bank, and the two outputs of the two-branch filter bank are connected to each other. Connected to a different two-stage filter bank of the next stage, respectively, and connected to the two outputs of the two-stage filter banks of the respective next stages so as to be further input to different two-stage filter banks of the next stage, respectively. Outputs branched by the final-stage two-branch filter bank are respectively input to demodulation means, outputs of the respective demodulation means are input to parallel / serial conversion means, and outputs of the parallel / serial conversion means are output to a digital receiver. A digital signal receiving apparatus characterized in that: 14. The channel demultiplexing means has a configuration in which, when there are two or more two-division filter banks, the two-division filter banks are cascaded in multiple stages. One of the two outputs of the two-segment filter bank is input to the next-stage two-segment filter bank or demodulation means, and the other is input to a different two-segment filter bank of the next stage or a different one. 14. The apparatus according to claim 13, wherein the output is sequentially connected so as to be input to the demodulation means, the output of the last two-stage demultiplexing filter bank is input to the demodulation means, and the output of each demodulation means is input to the parallel-serial conversion means. The digital signal receiving device according to the above. 15. The digital signal transmitting apparatus according to claim 11, wherein said serial-parallel conversion means is a multi-input multi-output type serial-parallel conversion means for serial-parallel conversion of a plurality of input signals into a plurality of low-speed signals. 16. The digital signal receiving apparatus according to claim 13, wherein said parallel / serial conversion means is a multi-input / multi-output type parallel / serial conversion means for inputting each output of said demodulation means. 17. The digital signal receiving apparatus according to claim 16, further comprising a modulating means for modulating a plurality of outputs of said multi-input multi-output type parallel-serial conversion means. 18. The method according to claim 11, wherein at least a part of the modulation means and the channel multiplexing means operate in a time division manner.
16. The digital signal transmitting device according to any one of Items 2 and 15. 19. The apparatus according to claim 13, wherein at least a part of the demodulation unit and the channel demultiplexing unit operate in a time division manner.
The digital signal receiving device according to any one of 14, 16, and 17. 20. The digital signal transmission device according to claim 12, wherein the plurality of low-speed signals have different speeds in the digital signal transmission device. 21. The digital signal receiving apparatus according to claim 14, wherein the plurality of low-speed signals have different speeds in the digital signal receiving apparatus. 22. The connection according to claim 12, wherein the connection of the two multiplexing filter banks in the channel multiplexing means is performed so as to correspond to the case where the speeds of the low-speed signals input to the channel multiplexing means are all different. Digital signal transmitter. 23. The connection of the two-branch filter bank in the channel demultiplexing means is connected so as to correspond to a case where output signals from the channel demultiplexing means are all low-speed signals of different speeds. 15. The digital signal receiving device according to 14. 24. At least one digital signal transmitting device according to any one of claims 11, 12, and 15, and at least one digital signal receiving device according to any one of claims 13, 14, 16, and 17 A digital signal transmission device provided with at least one.