JP2014022488A - Semiconductor integrated circuit device and manufacturing method of dram consolidation semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in an LSI including an embedded DRAM, in order to avoid signal delay in a logic part caused by an increase in thickness of a premetal insulating layer, a wiring layer invasion type memory capacitor is proposed in which a memory capacitor invades an upper multi-layer embedded wiring layer, but it is made clear, in the wiring layer invasion type memory capacitor, a side face of a lower electrode (e.g. a titanium-nitride electrode) of a MIM type memory capacitor is in contact with a low dielectric constant insulating film, such that constituent atoms of the lower electrode are easily dispersed to the outside, and under such nitrogen dispersion into the low dielectric constant insulating film, reliability of the insulating film between neighboring memory capacitors may be decreased so as to lose retained data.SOLUTION: In a DRAM & logic consolidation type semiconductor integrated circuit device having a wiring layer invasion type memory capacitor, a hard insulating film is interposed between a low dielectric constant insulating film and a side face of a MIM type memory capacitor.

Description

  The present application relates to a method of manufacturing a semiconductor integrated circuit device (or semiconductor device) and a DRAM (Dynamic Random Access Memory) mixed semiconductor integrated circuit device, and more particularly to a device structure technology of a semiconductor integrated circuit device having a DRAM portion and a manufacturing technology thereof. And effective technology.

  Japanese Unexamined Patent Publication No. 2008-130614 (Patent Document 1) relates to a general DRAM having a COB (Capacitor Over Bitline) type memory cell structure. There is disclosed a technique of providing an oxidizing impurity diffusion blocking film outside a lower electrode in a cylinder type MIM (Metal-Insulator-Metal) memory capacitor in order to prevent introduction of oxidizing impurities from a base insulating film. Has been.

  Japanese Patent Laid-Open No. 2007-201101 (Patent Document 2) or US Pat. No. 7,659,567 (Patent Document 3) corresponding to this relates to a DRAM and logic mixed chip. There is disclosed a technique for forming a memory capacitor in a DRAM region in the same layer as a metal wiring layer in a logic region.

JP 2008-130614 A JP 2007-201101 A U.S. Pat. No. 7,759,567

  In an LSI (Large Scale Integration) having an embedded DRAM & logic chip, that is, an embedded DRAM, in order to avoid a signal delay in the logic portion due to an increase in the thickness of a premetal insulating layer, the memory capacity is increased in the upper multilayer. There has been proposed a “wiring layer intrusion memory capacity” that has penetrated into a buried wiring layer.

  However, according to a study by the present inventor, in the wiring layer intrusion type memory capacitor, the side surface of the lower electrode (for example, titanium nitride electrode) of the MIM (Metal Insulator Metal) type memory capacitor and the low-k interlayer insulating film ( That is, since the low dielectric constant insulating film is in contact, it has been clarified that the constituent atoms (for example, nitrogen) of the lower electrode are easily diffused to the outside. If there is such diffusion of nitrogen into the low-k interlayer insulating film (low dielectric constant insulating film), the reliability of the insulating film between adjacent memory capacitors is lowered, and there is a risk that retained data is lost. .

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, an outline of an embodiment of the present application is that a hard insulating film is interposed between the low dielectric constant insulating film and the side surface of the MIM type memory capacitor in a DRAM & logic mixed type semiconductor integrated circuit device having a wiring layer intrusion memory capacity. Is interposed.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the embodiment of the present application, it is possible to prevent diffusion of elements from the lower electrode of the MIM type memory capacitor to the low dielectric constant insulating film.

It is the whole semiconductor chip top view for demonstrating an example of the device structure in the semiconductor integrated circuit device of one embodiment of this application. FIG. 2 is a schematic circuit diagram of a DRAM array region corner cutout region R1 in FIG. 1. FIG. 3 is an enlarged top view of a chip corresponding to FIG. 2. FIG. 2 is a schematic device cross-sectional view substantially corresponding to the A-A ′ cross section of FIG. 1. FIG. 5 is a schematic device cross-sectional view during a manufacturing process (at the time of completion of formation of a second layer embedded wiring) of a portion corresponding to FIG. 4 for describing a main process in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present application; . 4 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time when the upper electrode and capacitor plate housing recess formation is completed) for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present application; It is. FIG. 5 is a schematic device cross-sectional view during a manufacturing step (at the time of completion of formation of an upper hard insulating film) of a portion corresponding to FIG. 4 for describing a main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of forming the memory capacity storage cylinder) of the portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of hard insulating film formation) of a portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of hard insulating film processing) of a portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; 4 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time of forming the TiN film for the capacitor lower electrode) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application; FIG. is there. Schematic device during the manufacturing process of the part corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application (when the formation of the resist film for processing the capacitor lower electrode TiN film is completed) It is sectional drawing. FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of processing of the lower capacitor electrode) of the portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of formation of the memory capacitor insulating film) of the portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; 4 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the TiN film for the capacitor upper electrode) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. is there. FIG. 6 is a schematic device cross-sectional view during a manufacturing step (at the time of completion of formation of a capacitor plate W film) of a portion corresponding to FIG. 4 for describing a main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; 4 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time when the formation of the insulating barrier film on the capacitor plate is completed) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application; It is. FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of completion of processing of a capacitor plate or the like) of a portion corresponding to FIG. 4 for describing the main process in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present application; 4 is a schematic device cross-section during the manufacturing process of the portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (when the formation of the planarizing silicon oxide insulating film is completed). FIG. FIG. 5 is a schematic device sectional view in the manufacturing process (at the time of planarization completion) of a portion corresponding to FIG. 4 for describing the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application; Schematic device during the manufacturing process of the portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application (when the third layer wiring auxiliary insulating barrier film formation is completed) It is sectional drawing. 4 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the third buried wiring layer) for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application; FIG. is there. FIG. 5 is a device schematic cross-sectional view corresponding to FIG. 4 for describing the outline of the device structure in the semiconductor integrated circuit device of the one embodiment of the present application.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a DRAM region and a logic region provided on the first main surface;
(C) a premetal insulating layer provided on the first main surface and provided in the DRAM region and the logic region;
(D) A multilayer embedded wiring layer provided on the premetal insulating layer and provided in the DRAM region and the logic region and having a low dielectric constant insulating film;
(E) a plurality of cylindrical MIM memory capacities in the DRAM region extending from the premetal insulating layer to the multilayer embedded wiring layer;
(F) A hard insulating film covering a space between the side surface of each cylindrical MIM type memory capacitor and the low dielectric constant insulating film.

  2. In the semiconductor integrated circuit device according to Item 1, the low dielectric constant insulating film is a porous film.

  3. In the semiconductor integrated circuit device according to Item 1 or 2, the hard insulating film is a silicon-based insulating film.

  4). In the semiconductor integrated circuit device according to Item 1 or 2, the hard insulating film is a silicon oxide insulating film.

  5. In the semiconductor integrated circuit device according to Item 1 or 2, the hard insulating film is a silicon oxide insulating film formed by plasma TEOS-CVD.

6). In the semiconductor integrated circuit device according to any one of Items 1 to 5, each cylindrical MIM type memory capacitor has the following:
(E1) lower electrode;
(E2) a capacitive insulating film provided in the lower electrode;
(E3) An upper electrode provided on the capacitive insulating film and provided in the lower electrode;
Here, the lower electrode is connected to a capacitor contact plug.

7). A method of manufacturing a DRAM-embedded semiconductor integrated circuit device including the following steps:
(A) forming a premetal insulating layer on the first main surface of the wafer;
(B) forming a multilayer embedded wiring layer having a low dielectric constant insulating film on the premetal insulating layer;
(C) exposing a top end of the capacitive contact plug from a bottom surface of the cylindrical hole by forming a plurality of cylindrical holes extending through the multilayer embedded wiring layer and reaching the inside of the premetal insulating layer;
(D) a step of forming a hard insulating film on the side surface, the bottom surface, and the outside of each cylindrical hole;
(E) exposing the upper end of the capacitive contact plug in a self-aligning manner by performing anisotropic dry etching on the hard insulating film;
(F) After the step (e), forming a lower metal electrode film on the side surface, the bottom surface, and the outside of each cylindrical hole.

  8). In the method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to Item 7, the low dielectric constant insulating film is a porous film.

  9. In the method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to Item 7 or 8, the hard insulating film is a silicon-based insulating film.

  10. In the method of manufacturing a DRAM mixed semiconductor integrated circuit device according to Item 7 or 8, the hard insulating film is a silicon oxide insulating film.

  11. In the manufacturing method of a DRAM mixed semiconductor integrated circuit device according to Item 7 or 8, the hard insulating film is a silicon oxide insulating film formed by plasma TEOS-CVD.

12 The method for manufacturing a DRAM-embedded semiconductor integrated circuit device according to any one of Items 7 to 11 further includes the following steps:
(G) removing the outer metal electrode film outside the cylindrical holes;
(H) After the step (g), forming a capacitor insulating film of an MIM type memory capacitor on the side surface, the bottom surface, and the outside of each cylindrical hole;
(I) A step of forming an upper metal electrode of the MIM type memory capacitor on the high dielectric constant insulating film.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). A silicon substrate) or a semiconductor chip packaged. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  The wafer process of today's semiconductor integrated circuit device, that is, LSI (Large Scale Integration), is usually considered in two parts. That is, the first is from the introduction of a silicon wafer as a raw material to the premetal process (formation of an interlayer insulation film between the lower end of the first layer wiring layer and the gate electrode structure, contact hole formation, tungsten plug, embedding, etc. FEOL (Front End of Line) process. The second is BEOL (Back End of) which starts from the formation of the first layer wiring layer and extends to the formation of the pad opening in the final passivation film on the aluminum-based pad electrode (including the process in the wafer level package process). Line) process.

  Correspondingly, the interlayer insulating film between the lower end of the first layer wiring layer and the gate electrode structure is called a “premetal insulating film” including a stress applying film and an etch stop film, and the layer is called a “premetal insulating layer”. Call. Further, in a device having an embedded wiring, a portion from the first embedded wiring layer to the uppermost embedded wiring layer is referred to as a “multilayer embedded wiring layer”.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Therefore, in the present application, for example, when “A is a main component”, “A is a main material”, “A is a main component”, etc., for example, about 80% The above represents A.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Although SiC has properties similar to SiN, SiON should be classified as a silicon oxide insulating film in many cases, but in the case of an etch stop film, it is close to SiC, SiN, or the like.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  Similarly, the term “nickel silicide” usually refers to nickel monosilicide, but includes not only relatively pure ones but also alloys, mixed crystals, and the like whose main components are nickel monosilicide. Further, the silicide is not limited to nickel silicide, but may be cobalt silicide, titanium silicide, tungsten silicide, or the like that has been proven in the past. In addition to the Ni (nickel) film, for example, a Ni-Pt alloy film (Ni and Pt alloy film), a Ni-V alloy film (Ni and V alloy film), A nickel alloy film such as a Ni—Pd alloy film (Ni—Pd alloy film), a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) is used. be able to. These silicides having nickel as a main metal element are collectively referred to as “nickel-based silicide”.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to substantially parallel.

  In addition, with respect to a certain region (for example, the surface of the wafer), “whole”, “whole”, “whole area” and the like include cases of “substantially whole”, “substantially whole”, “substantially whole area”, and the like. Therefore, for example, 80% or more of a certain region can be referred to as “substantially the whole”, “substantially general”, and “substantially the entire region”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be almost rectangular. The same applies to “annular” and the like.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element is said to be “almost periodic”. it can. Furthermore, if what is out of this range is, for example, less than about 20% of all elements that are targets of the periodicity, it can be said to be “substantially periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, “DRAM array region” refers to a region where DRAM memory cells are spread in a matrix, and “DRAM region” refers to a DRAM array region and a “DRAM peripheral circuit region”. Here, the DRAM peripheral circuit region refers to a region in the vicinity of the periphery of the memory array region where a sense amplifier, a word line driver, and the like are provided. The “logic area” refers to an area other than the DRAM area, in which a logic circuit is formed except for other memory areas.

  “Low dielectric constant interlayer insulating film”, “Low-k interlayer insulating film”, “low dielectric constant insulating film” and the like are, for example, non-porous insulating films or porous insulating films represented by SiOC, SiOCH, etc. An insulating film having a lower dielectric constant than a normal non-low dielectric constant TEOS-based silicon oxide CVD film or the like. In particular, “porous low dielectric constant interlayer insulating film”, “porous low-k interlayer insulating film” and the like are structures derived from molecular porous, porogen, etc. Both porous (or physically porous).

  7). In the present application, the “memory capacity storage cylinder” is a hole having a horizontal cross section such as a circle, an ellipse, a hexagon or the like, which is opened in an insulating film layer for forming a memory capacity. In the present application, mainly an embedded DRAM having a “wiring layer intrusive memory capacity” is mainly handled. In the present application, the “wiring layer intrusive memory capacity” refers to a multilayer embedded wiring from a premetal insulating layer. A memory capacity formed over a wiring layer such as a layer. The “cylindrical MIM type memory capacity” is a memory capacity whose main part is housed in a memory capacity housing cylinder, for example, a metal such as platinum, ruthenium, titanium, or a conductive material such as ruthenium oxide. A metal oxide, a conductive metal nitride such as titanium nitride, or the like is used as a material for both electrodes.

  Further, the “lower electrode of the memory capacitor” refers to a portion that is electrically connected to the metal plug for each individual electrode regardless of the microscopic positional top and bottom. On the other hand, the “upper electrode of the memory capacitor” refers to an electrode facing the lower electrode. In the present application, the capacitor plate and the upper electrode have different concepts.

  Further, in the present application, the “hard insulating film” is mainly a non-porous non-porous insulating material having a dielectric constant higher than that of non-porous low dielectric constant insulating films such as non-porous SiOC and non-porous SiOCH. An insulating film having a function of preventing undesired diffusion of elements constituting a memory capacitor. Note that SiC, SiCN, etc., which are often used as a copper diffusion barrier film, are included in the hard insulating film. Specifically, for example, an inorganic non-porous silicon oxide insulating film, an inorganic non-porous silicon nitride insulating film, etc. formed by CVD (Chemical Vapor Deposition). Examples of inorganic non-porous silicon oxide insulating films include, for example, TEOS-based P-CVD (Plasma-CVD) silicon oxide films, ozone TEOS thermal CVD silicon oxide films, monosilane-based P-CVD-SiON films, ALD ( A silicon oxide film or the like by atomic layer deposition). Examples of inorganic non-porous silicon nitride insulating films include monosilane-based P-CVD silicon nitride films.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

  For example, Japanese Patent Application No. 2011-191983 (Japan filing date September 2, 2011) as a prior patent application describing various improvements related to an insulating film around a memory capacitor in a semiconductor chip having a DRAM portion. There is.

1. Description of an example of a device structure in the semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 1 to 4)
In the following example, a DRAM layout with a folded bit line (Folded Bitline) structure will be specifically described as an example, but it goes without saying that a DRAM layout with an open bit line (Open Bitline) structure may be used. In the following example, a so-called close packed folded bit line layout will be specifically described by way of example, but a so-called half pitch folded bit line layout may be used. Needless to say.

  In the following, specific description will be given mainly using an embedded DRAM as an example, but it is needless to say that a dedicated DRAM may be used.

  In the following example, a wiring material containing copper as a main component will be specifically described as an embedded wiring material. However, it is needless to say that the present invention is not limited to this. The insulating barrier film will be specifically described by taking a SiCN film as an example. However, the present invention is not limited to this, and needless to say, SiN, SiC or the like may be used. Further, the low dielectric constant insulating film will be specifically described below mainly using a porous SiOC film and a porous SiOCH film as an example, but the present invention is not limited thereto. It goes without saying that a porous SiOCH film or the like may be used. The metal member of the pad layer will be specifically described by taking an aluminum member as an example, but is not limited to this, and may be a copper member, a tungsten member, or another metal member. Needless to say. Furthermore, tungsten-based plugs and bit lines are usually composed of a tungsten member as a main part and barrier films such as titanium and titanium nitride below and on the side, but in order to avoid complexity, details The structure is omitted. Similarly, the copper wiring is usually composed of a copper-based member of the main part and barrier films such as tantalum and tantalum nitride on the lower and side thereof, but the detailed structure is omitted in order to avoid complexity. To do. Needless to say, as the barrier film, in addition to tantalum and titanium, a ruthenium barrier film and the like can be applied.

  FIG. 1 is an overall top view of a semiconductor chip for explaining an example of a device structure in a semiconductor integrated circuit device according to an embodiment of the present application. FIG. 2 is a schematic circuit diagram of the DRAM array area corner cutout region R1 of FIG. FIG. 3 is an enlarged top view of a chip corresponding to FIG. FIG. 4 is a schematic device cross-sectional view substantially corresponding to the cross section A-A ′ of FIG. 1. Based on these, an example of a device structure in the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, as shown in FIG. 1, the upper surface 1 a of the semiconductor chip 2 can generally be divided into a chip peripheral region 5 and a chip internal region 6. A DRAM region 3 is provided in the internal region 6 of the upper surface 1a of the semiconductor chip 2, and other regions include, for example, a CMOS logic circuit region (logic region 4), an analog circuit region, and other memories. An area (SRAM area, nonvolatile memory area), an I / O circuit area, and the like are provided. The DRAM area 3 (memory area) includes a DRAM array area (memory array area) 3c in which unit memory cells UC (see FIG. 2; the same applies hereinafter) are arranged in a matrix and a peripheral DRAM peripheral circuit area (memory peripheral area). It is divided into 3p. In the memory peripheral area 3p, for example, memory peripheral circuits such as sense amplifiers SA1 and SA2 (see FIG. 2, the same applies hereinafter), word line drivers WD1, WD2, WD3, and WD4 are provided.

  Next, FIG. 2 shows a schematic circuit diagram of the memory area 3 of FIG. As shown in FIG. 2, in the memory array region 3c, a plurality of word lines WL1, WL2, WL3, WL4 are provided in the vertical direction, and a plurality of bits are orthogonally crossed in the horizontal direction. Lines BL1, BL2, BL3, and BL4 are provided. In this example, for example, the word lines WL1, WL2, WL3, WL4 are alternately controlled by word line drivers WD1, WD2, WD3, WD4 arranged in the memory peripheral area 3p on the opposite side of the memory array area 3c. ing. On the other hand, every other bit line BL1, BL2, BL3, BL4 forms a pair, and the sense amplifiers SA1, SA1 are alternately arranged in the memory peripheral region 3p on the opposite side of the memory array region 3c. Connected to SA2. Note that the arrangement of the word line drivers WD1, WD2, WD3, and WD4, the arrangement of the sense amplifiers SA1 and SA2, and the pair formation method of the bit lines BL1, BL2, BL3, and BL4 are not limited to those shown here. Not too long.

  Near a predetermined intersection of the word lines WL1, WL2, WL3, WL4 and the bit lines BL1, BL2, BL3, BL4, N-type MISFETs (access transistors) Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 and A unit memory cell UC composed of pairs of memory capacitors C1, C2, C3, C4, C5, C6, C7, and C8 is connected to each bit line and each word line. Here, one terminal of each of the memory capacitors C1, C2, C3, C4, C5, C6, C7, and C8 is connected to a plate potential Vp (in the half precharge method, an intermediate potential that is 1/2 of the power supply potential). ing.

  Next, FIG. 3 shows an enlarged plan view of the memory region corner portion peripheral cutout region R1 of FIG. As shown in FIG. 3, a plurality of active areas AC in the memory array are provided in a matrix on the surface 1a (first main surface) of the semiconductor substrate 1s. Here, an area other than the active area AC in the memory array is, for example, an STI (Shallow Trench Isolation) area 7 (element isolation area).

  On the surface 1a of the semiconductor substrate 1s, for example, a plurality of word lines WL (in this example, for example, polysilicon is a main material) are arranged in the vertical direction, and a plurality of bit lines are arranged in the horizontal direction. BLs (in this example, for example, tungsten is a main material) are arranged so as to be substantially orthogonal to each other. A bit line contact W plug 12 is provided below these bit lines BL and in a predetermined portion on the active area AC in the memory array. On the other hand, in the vicinity of a predetermined intersection of the plurality of word lines WL and the plurality of bit lines BL and on the active area AC in the memory array, the capacitor contact W plug 14 (in this example, for example, tungsten is used as a main material). The capacitor lower electrode 32 is provided thereon. Above these capacitor lower electrodes 32, a capacitor plate 35 (in this example, for example, tungsten is the main material) is provided so as to substantially cover the memory array region 3c.

  Next, FIG. 4 shows a chip cross-sectional view corresponding to the A-A ′ cross section of FIG. 1. As shown in FIG. 4, on the surface 1a (first main surface) of a semiconductor substrate 1s (for example, a P-type single crystal silicon substrate), the logic region 4 includes a P-type well region WPG and an N-type well region WNG. Is provided. On the other hand, a deep N type well region DWN is provided in the DRAM region 3 on the surface 1a of the semiconductor substrate 1s, and a P type well region WPC is provided on the surface thereof. The back surface 1b (second main surface) of the semiconductor substrate 1s other than these impurity doped regions is a substrate P-type region 1p, and between the DRAM region 3 and the logic region 4 on the surface 1a of the semiconductor substrate 1s. Is provided with an STI (Shallow Trench Isolation) region 7 (element isolation region).

  For example, an N-type source / drain region 8n constituting an N-type MISFET (Qng) is provided on the surface of the P-type well region WPG, and a P-type MISFET (Qpg) is formed on the surface of the N-type well region WNG. A P-type source / drain region 8p is provided. On the other hand, on the surface of the P-type well region WPC, for example, an N-type source / drain region 8n constituting an N-type MISFET (Qnc1, Qnc2) is provided. A gate electrode 10 (for example, a polysilicon electrode) is provided on each pair of N-type source / drain regions 8n via a gate insulating film 9, and a sidewall 11 is provided around the gate electrode. . A silicide film 15 (for example, a nickel silicide film) is provided on each gate electrode 10 and on each N-type source / drain region 8n and P-type source / drain region 8p.

  In this example, the silicide film 15 is also provided on the N-type source / drain region 8n and the gate electrode 10 constituting the N-type MISFET (Qnc1, Qnc2) in the DRAM region 3, but it goes without saying. That is optional. That is, there is an option in which the silicide film 15 is not formed on the N-type source / drain region 8n constituting the N-type MISFET (Qnc1, Qnc2) in the DRAM region 3. In that case, there is an advantage that the leakage current is reduced. As a result, the silicide film 15 is not provided on the gate electrode 10 constituting the N-type MISFET (Qnc1, Qnc2) in the DRAM region 3. Although there is a concern that the resistance of the word line becomes relatively high, an increase in the resistance value of the gate electrode is not as important as the logic region. In this regard, the same applies to the source / drain resistance. On the other hand, if the silicide film 15 is provided also on the N-type source / drain region 8n and the gate electrode 10 constituting the N-type MISFET (Qnc1, Qnc2) in the DRAM region 3, the leakage current slightly increases. There is an effect of reducing the word line resistance and the source / drain resistance. In general, since embedded DRAMs tend to focus on speed rather than leakage current, the reduction in word line resistance and source / drain resistance greatly contributes to improvement in overall performance. In addition to the nickel-based silicide, the silicide film material may be platinum-based silicide, titanium-based silicide, cobalt-based silicide, tungsten-based silicide, or the like.

  A premetal insulating layer PM is provided on the surface 1a of the semiconductor substrate 1s, and is composed of, for example, a lower layer premetal insulating layer PM1, a middle layer premetal insulating layer PM2, and an upper layer premetal insulating layer PM3. In this example, the lower premetal insulating layer PM1 is a layer that accommodates the gate structure, and the intermediate premetal insulating layer PM2 is the lower end of the memory capacitors Ca and Cb (cylindrical MIM type memory capacitors) and the bit line BL. The upper premetal insulating layer PM3 is a layer that accommodates the central portion of the memory capacitors Ca and Cb.

  On the premetal insulating layer PM, for example, a multilayer wiring layer M (multilayer embedded wiring layer) composed of several to a dozen layers of embedded wiring layers is provided. The first buried wiring layer M1, the second buried wiring layer M2, the third buried wiring layer M3, the fourth buried wiring layer M4, the uppermost buried wiring layer M5, and the like. In this example, the first buried wiring layer M1 is a layer that accommodates the central portion of the memory capacitors Ca and Cb and the first layer buried wiring 21w (for example, a copper buried wiring, the same applies hereinafter) by the single damascene method. The two-layer embedded wiring layer M2 is a layer that accommodates the upper ends of the memory capacitors Ca and Cb and the second layer embedded wiring 22w (including vias) by the dual damascene method. The third buried wiring layer M3 is a layer for accommodating the third buried wiring 23w (including vias) by the dual damascene method, and the fourth buried wiring layer M4 is the fourth buried wiring 24w by the dual damascene method. The uppermost buried wiring layer M5 is a layer that accommodates the uppermost buried wiring 25w (including vias).

  On the multilayer wiring layer M, for example, a pad layer AP for receiving a bonding pad 29 (or including a pad layer wiring or the like) such as an aluminum-based bonding pad is provided.

  Next, an example of details of the insulating film structure in FIG. 4 will be described. On the surface 1a of the semiconductor substrate 1s, for example, a plasma TEOS-based silicon oxide film (for example, a thickness) is provided through a relatively thin etch stop film, stress applying film, or the like as necessary so as to cover the gate structure. A lower premetal main insulating film 19f (non-porous non-low dielectric constant insulating film) mainly composed of, for example, about 150 nm) is formed. A bit line contact plug 16 and a lower logic portion contact plug 18f made of a tungsten plug or the like are embedded through the lower premetal main insulating film 19f and the like.

  On the lower premetal main insulating film 19f, for example, a bit line base insulating film 20b mainly composed of a plasma TEOS-based silicon oxide film (for example, a thickness of about 20 nm), that is, a TEOS-based silicon oxide film by plasma CVD is formed. Has been. On the bit line base insulating film 20b, for example, an intermediate-layer premetal main insulating film 19s mainly composed of a plasma TEOS-based silicon oxide film (for example, a thickness of about 150 nm) is formed. An intermediate layer logic portion contact plug 18s made of a tungsten plug or the like is embedded through the base insulating film 20b. Further, in the bit line base insulating film 20b and the intermediate pre-metal main insulating film 19s, a tungsten plug or the like is connected so that the upper ends thereof are connected to the capacitor lower electrodes 32 (for example, TiN films) of the memory capacitors Ca and Cb, respectively. The upper capacitor contact plug 17s thus configured is embedded.

  On the intermediate pre-metal main insulating film 19s, for example, a SiON film (for example, about 30 nm thick) by plasma CVD is provided as the pre-metal intermediate etch stop insulating film 20s. On this premetal intermediate etch stop insulating film 20s, an upper premetal main insulating film 19t mainly composed of, for example, a plasma TEOS-based silicon oxide film (for example, about 180 nm thick) is provided. An upper logic portion contact plug 18t made of a tungsten plug or the like is embedded through the premetal intermediate etch stop insulating film 20s and the upper premetal main insulating film 19t.

  On the upper premetal main insulating film 19t, for example, a SiCN film (for example, about 20 nm thick) by plasma CVD is formed as the first layer wiring insulating barrier film 21b. On the first layer wiring insulating barrier film 21b, for example, a first layer wiring main interlayer insulating film 21d (porous low dielectric constant film) mainly composed of a porous low dielectric constant insulating film such as a porous SiOC film formed by plasma CVD is used. Dielectric constant silicon oxide insulating film) is formed. The thickness of the first-layer wiring main interlayer insulating film 21d can be exemplified as a preferable thickness of about 80 nm, for example. The first-layer wiring main interlayer insulating film 21d may be a porous low dielectric constant insulating film or a non-porous low dielectric constant insulating film (for example, a non-porous SiOC film).

  On the first layer wiring main interlayer insulating film 21d, for example, a SiCN film (for example, about 30 nm thick) by plasma CVD is formed as the second layer wiring insulating barrier film 22b. On the second layer wiring insulating barrier film 22bt, for example, a second layer wiring main interlayer insulating film 22d (porous low dielectric constant insulating film mainly composed of a porous low dielectric constant insulating film such as a porous SiOC film formed by plasma CVD) is formed. Dielectric constant silicon oxide insulating film) is formed. The thickness of the second-layer wiring main interlayer insulating film 22d can be exemplified as a preferable thickness of about 150 nm, for example.

On the second-layer wiring main interlayer insulating film 22d in the logic region 4, a SiCN film (for example, about 15 nm thick) by plasma CVD is formed as a third-layer wiring insulating barrier film 23b. Next, the DRAM region 3 will be described. A memory capacity storage cylinder 36 (in this example, an elliptical cross section cylinder) formed from the middle layer premetal main insulating film 19s to the second layer wiring main interlayer insulating film 22d has a memory capacity. Main parts such as Ca and Cb are embedded. Each of the memory capacitors Ca and Cb includes, for example, a capacitor lower electrode 32 (for example, TiN film) having a thickness of about 5 nm, a memory capacitor insulating film 33 (for example, ZrO ₂ film) having a thickness of about 5 nm, and a capacitor upper electrode 34 having a thickness of about 30 nm. (For example, a TiN film), a capacity plate 35 (for example, a W film) having a thickness of about 40 nm, and the like. In this example, a part other than the capacitor lower electrode 32 is shared by a plurality of memory capacitors Ca and Cb. The upper ends of the memory capacitors Ca and Cb are, for example, the second layer wiring main interlayer via an upper hard insulating film 31 mainly composed of a plasma TEOS-based silicon oxide film (for example, about 30 nm thick) or the like. It is accommodated in the upper electrode & capacitor plate accommodating recess 30 formed on the surface of the insulating film 22d and the like. A planarizing silicon oxide insulating film 39 remains at the end of the capacitor plate 35. As a material (high dielectric constant material) of the memory capacitor insulating film 33, in addition to zirconium-based high dielectric constant insulators such as zirconium dioxide (ZrO ₂ ) and zirconium aluminate (ZrAlOx), tantalum oxide-based high dielectric constant insulation is used. And the like, and an alumina-based high dielectric constant insulator, a perovskite-based high dielectric constant insulator, and the like.

  Here, between the side surfaces of the respective memory capacitors Ca and Cb, that is, between the side surfaces of the capacitor lower electrode 32 and the like and the side surfaces of the memory capacitor storage cylinder 36, so as to avoid direct contact with the low dielectric constant insulating film, For example, a hard insulating film 37 mainly composed of a plasma TEOS-based silicon oxide film (for example, a thickness of about 5 nm) is provided. A suitable range for the thickness of the hard insulating film 37 is, for example, about 3 nm to 10 nm. That is, if it is too thin, for example, diffusion of nitrogen in titanium nitride to the porous low dielectric constant insulating film cannot be prevented, and if it is too thick, the size of the memory capacity increases.

  Examples of the material of the hard insulating film 37 and the upper hard insulating film 31 include a plasma TEOS-based silicon oxide film, a non-porous non-low dielectric constant silicon oxide-based insulating film such as a SiON film, a silicon nitride film, a SiCN film, and the like. Non-porous non-low dielectric constant silicon nitride insulating films by CVD or the like, non-porous non-low dielectric constant silicon carbide insulating films by CVD or the like such as SiC films, SiCN films, etc. can be exemplified as suitable ones. Here, the CVD includes ALD (Atomic Layer Deposition). The same material is used for the hard insulating film 37 and the upper hard insulating film 31 in terms of processing, but it goes without saying that different materials may be used.

  Thus, by interposing the hard insulating film 37, the reliability of the insulating film between the memory capacitors can be improved. In particular, when the low dielectric constant insulating film in contact with the side surface of the memory capacitor is porous, it is particularly important to insert such an intervening layer because the diffusion capacity of nitrogen or the like is increased. If the hard insulating film 37 is a silicon-based insulating film, the properties of the film are stable as used frequently in other parts of the device, and the reliability of the device is not adversely affected. In particular, when the silicon oxide insulating film is the hard insulating film 37, the distortion of the film is small, and the removal of the bottom portion of the cylinder is relatively easy. Further, when the silicon oxide insulating film formed by plasma TEOS-CVD is used as the hard insulating film 37, it is widely used in the process, and a hard film can be obtained at a relatively low temperature (advantageous on the thermal budget). There are benefits. Further, in an embedded DRAM having a cylindrical MIM memory capacity, the possibility of direct contact with a low dielectric constant insulating film is inevitably increased, and therefore the introduction of such an intervening hard film is particularly effective.

  Further, the upper surface of the capacitor plate 35 and the upper surface of the second layer embedded wiring 22w are substantially the same height, and the upper surface of the capacitor plate 35 has, for example, approximately the same thickness as the third-layer wiring insulating barrier film 23b. A SiCN film (for example, about 15 nm thick) by plasma CVD is formed as an insulating barrier film 35b on the capacitor plate.

  On the upper surfaces of the planarizing silicon oxide insulating film 39, the third-layer wiring insulating barrier film 23b, and the capacitor-board insulating barrier film 35b, for example, a SiCN film (for example, about 15 nm thick) formed by plasma CVD is provided. It is formed as a three-layer wiring auxiliary insulating barrier film 23c.

  On the third layer wiring auxiliary insulating barrier film 23c, for example, a third layer wiring main interlayer insulating film 23d (porous) mainly composed of a porous low dielectric constant insulating film such as a porous SiOC film formed by plasma CVD is used. A low dielectric constant silicon oxide insulating film) is formed.

  On the third-layer wiring main interlayer insulating film 23d, for example, a SiCN film (for example, about 30 nm thick) by plasma CVD is formed as the fourth-layer wiring insulating barrier film 24b. The detailed structure of the interlayer insulating film such as the fourth buried wiring layer M4, the uppermost buried wiring layer M5, etc. will be repeated, and the description thereof will be omitted.

  On the uppermost buried wiring layer M5, an under-pad interlayer insulating film 27 including an insulating barrier film (for example, a non-porous non-low dielectric constant silicon oxide insulating film is a main part) is formed. In general, a final passivation film 28 made of a non-porous non-low dielectric constant silicon-based insulating film such as a plasma TEOS-based silicon oxide film or a silicon nitride film formed by plasma CVD is provided.

2. Description of Main Processes in Manufacturing Method of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 5 to 22)
The following manufacturing method is an example of a manufacturing method for the device structure described in Section 1, and it goes without saying that various modifications can be made.

  The FEOL process is described on the premise of a gate first method and a polysilicon gate structure. However, a FUSI method, a gate last method, a source drain first (S / D first) method, Needless to say, an eclectic method (hybrid process) in which the gate-first method and the gate-last method are compromised may be used.

  FIG. 5 is a schematic device cross section during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the second layer embedded wiring) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. FIG. 6 is a schematic view during the manufacturing process of the portion corresponding to FIG. 4 (at the time when the upper electrode and capacitor plate storage recess formation is completed) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing. 7 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the upper hard insulating film) for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is. FIG. 8 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the completion of the formation of the memory capacity storage cylinder) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. It is. FIG. 9 is a schematic device sectional view in the manufacturing process (at the time of completion of hard insulating film formation) of a portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. is there. FIG. 10 is a schematic device sectional view in the manufacturing process (at the time of completion of hard insulating film processing) of a portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. is there. FIG. 11 is a schematic device during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the TiN film for the capacitor lower electrode) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. FIG. 12 is a diagram showing a main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, during the manufacturing process of the portion corresponding to FIG. 4 (at the time when the formation of the resist film for processing the capacitor lower electrode TiN film) is completed. It is typical device sectional drawing. FIG. 13 is a schematic device sectional view in the manufacturing process of the portion corresponding to FIG. 4 (at the time of processing of the capacitor lower electrode) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. is there. 14 is a schematic device cross-sectional view during the manufacturing process (at the time of completion of the formation of the memory capacitor insulating film) of the portion corresponding to FIG. 4 for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is. FIG. 15 is a schematic device during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the TiN film for the capacitor upper electrode) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. FIG. 16 is a schematic device cross-sectional view during the manufacturing process (at the time of completion of the formation of the capacitor plate W film) of the portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. It is. FIG. 17 is a schematic view during the manufacturing process of the portion corresponding to FIG. 4 (when the formation of the insulating barrier film on the capacitor plate is completed) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing. FIG. 18 is a schematic device cross-sectional view during the manufacturing process of the portion corresponding to FIG. 4 (at the completion of processing such as a capacitor plate) for explaining the main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. is there. FIG. 19 is a schematic view during the manufacturing process of the portion corresponding to FIG. 4 for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application (when the formation of the planarizing silicon oxide insulating film is completed). FIG. FIG. 20 is a schematic device sectional view in the manufacturing process (at the time of planarization completion) of the portion corresponding to FIG. 4 for describing the main processes in the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application. FIG. 21 is a diagram illustrating a main process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application, during the manufacturing process of the portion corresponding to FIG. 4 (when the third-layer wiring auxiliary insulating barrier film formation is completed). It is typical device sectional drawing. FIG. 22 is a schematic device during the manufacturing process of the portion corresponding to FIG. 4 (at the time of completion of the formation of the third buried wiring layer) for explaining the main process in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing. Based on these, the main processes and the like in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  The process up to the completion of the second buried wiring layer M2 is a general-purpose process and has no direct relationship with the subsequent processing. Therefore, in the following, in principle, the second buried wiring layer M2 is completed. The subsequent steps will be mainly described. In addition, as a wafer at the time of wafer introduction, for example, a 300-type P-type silicon single crystal wafer (for example, a thickness of about 800 micrometers) will be described as an example. 200φ and others may be used.

  As shown in FIG. 5, the third layer wiring insulating barrier film 23b is formed on the second layer wiring main interlayer insulating film 22d and the like on almost the entire surface 1a side of the wafer 1 by, for example, plasma CVD. For example, a SiCN film (for example, about 15 nm thick) is formed. Here, “substantially the entire surface” usually means that when a predetermined film is formed (formed) by CVD or coating rather than selectively on the wafer, a film is attached to the peripheral portion of the wafer due to various circumstances. This is because even if it is present or attached, it will be removed sooner or later. The same applies to the subsequent film forming processes.

  Further, a TEOS-based silicon oxide film (that is, a non-silicon oxide-based sacrificial insulating film 26 is formed on almost the entire surface of the wafer 1 on the surface 1a side as the silicon oxide-based sacrificial insulating film 26 by plasma CVD, for example. A porous non-low dielectric constant insulating film) is formed. The thickness of the silicon oxide-based sacrificial insulating film 26 formed here can be exemplified as a suitable thickness of, for example, about 10 nm.

  Next, as shown in FIG. 6, for example, a resist film for recess processing of the upper electrode and capacitor plate storage is formed on the surface 1a side of the wafer 1 by, for example, normal lithography. The upper electrode & capacitor plate housing recess 30 is formed in a fluorocarbon gas atmosphere. Thereafter, the resist film for recess processing of the upper electrode and capacitor plate storage that is no longer needed is removed by ashing or the like.

  Next, as shown in FIG. 7, for example, a TEOS-based silicon oxide film (that is, a non-porous non-low dielectric constant) is formed on almost the entire surface on the surface 1a side of the wafer 1 as the upper hard insulating film 31, for example, by plasma CVD. An insulating film) is formed. For example, the thickness of the upper hard insulating film 31 formed here is preferably about 35 nm.

  Next, as shown in FIG. 8, a resist film for forming a memory capacity storage cylinder is formed on the surface 1a side of the wafer 1 by, for example, ordinary lithography, and using it as a mask, for example, anisotropic dry etching ( For example, a plurality of memory capacity storage cylinders 36 are formed in a fluorocarbon gas atmosphere. Thereafter, the resist film for forming the memory capacity storage cylinder that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 9, as the hard insulating film 37, a TEOS-based silicon oxide film (that is, a non-porous non-low dielectric constant insulating film) is formed by plasma CVD, for example. The thickness of the hard insulating film 37 to be formed here can be exemplified as a suitable thickness of, for example, about 5 nm. The TEOS-based silicon oxide film formed by plasma CVD is conformal, but the gap fill property is not high, and the film thickness at the bottom of the cylinder is automatically thinned. It is advantageous to remove the membrane at the bottom of the cylinder. However, in terms of process, a silicon oxide film by ALD (a precursor is, for example, SiCl ₄ / H ₂ O) has a higher conformal, so that a relatively thin film is uniformly formed on the inner surface of the cylinder. It is advantageous. However, the processing time is shorter in normal CVD such as normal plasma CVD and thermal CVD. As normal CVD, ozone TEOS-based silicon oxide film or the like by sub-atmospheric thermal CVD is dominant, and conformality is higher than TEOS-based silicon oxide film by plasma CVD, but gap fill property Is also expensive.

  As for the method of forming the hard insulating film 37, CVD (including ALD) is generally advantageous. This is because the coating film generally has too high a gap fill property. As for the material of the hard insulating film 37, on the condition that the thermal burden during formation is not large, a silicon oxide insulating film, a silicon nitride insulating film, a silicon carbonitride insulating film, a silicon carbide insulating film, A silicon nitride oxide insulating film or the like can be exemplified as a preferable one.

  Next, as shown in FIG. 10, the bottom of the memory capacity storage cylinder 36 and the hard insulating film 37 outside thereof are removed in a self-aligning manner, for example, by anisotropic dry etching (for example, a fluorocarbon gas atmosphere). .

  Next, as shown in FIG. 11, for example, a titanium nitride film having a thickness of about 5 nm is formed on almost the entire surface on the surface 1a side of the wafer 1 by using, for example, ALD or MOCVD (Metal Organic CVD) as the capacitor lower electrode 32. Is deposited.

  Next, as shown in FIG. 12, for example, a positive resist is applied to almost the entire surface on the surface 1a side of the wafer 1, and the entire surface is exposed and developed. The resist film for processing 38 remains.

  Next, as shown in FIG. 13, for example, by performing dry etching (for example, a halogen-based gas atmosphere) on the surface 1 a side of the wafer 1 using the resist film 38 for processing the capacitor lower electrode as a mask, The capacitor lower electrode 32 is patterned. Thereafter, the capacitor lower electrode processing resist film 38 that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 14, a zirconium oxide film (for example, a thickness of about 5 nm) is formed as the memory capacitor insulating film 33 by, for example, ALD or the like on almost the entire surface 1a side of the wafer 1.

  Next, as shown in FIG. 15, a TiN film (for example, a thickness of about 30 nm) is formed as the capacitor upper electrode 34 on almost the entire surface of the zirconium oxide film 33 by, for example, ALD or MOCVD.

  Next, as shown in FIG. 16, a relatively thick tungsten film (for example, about 40 nm thick) is formed as the capacitor plate 35 on almost the entire surface of the capacitor upper electrode 34 by, eg, thermal CVD.

  Next, as shown in FIG. 17, a SiCN film (for example, a thickness of about 15 nm) is formed as an insulating barrier film 35b on the capacitor plate, for example, by plasma CVD on almost the entire surface of the wafer 1 on the surface 1a side. To do.

Next, as shown in FIG. 18, a capacitor plate processing resist film is formed on the surface 1 a side of the wafer 1 by, for example, ordinary lithography, and this is used as a mask to sequentially perform anisotropic dry etching or the like. The capacitor plate insulating barrier film 35b, the capacitor plate 35, the capacitor upper electrode 34, and the memory capacitor insulating film 33 are patterned. Here, as an etching atmosphere, for capacitive plates insulative barrier film 35b, for example, it can be exemplified a fluorocarbon-based etching gas atmosphere or SF ₆ -based etching gas atmosphere as suitable. For the capacitor plate 35, for example, an etching gas atmosphere containing chlorine-based and fluorine-based gas can be exemplified as a preferable one. For the capacitor upper electrode 34 and the memory capacitor insulating film 33, for example, an etching gas atmosphere such as BCl ₃ can be exemplified as a preferable one. Thereafter, the resist film for processing the capacity plate that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 19, a TEOS-based silicon oxide film (that is, a non-porous non-low film) is formed on the entire surface on the surface 1a side of the wafer 1 as a planarizing silicon oxide-based insulating film 39 by, for example, plasma CVD. A dielectric constant insulating film) is formed.

  Next, as shown in FIG. 20, a planarization process such as CMP (Chemical Mechanical Polishing) is performed on the surface 1 a side of the wafer 1. As a result, for example, the portions other than the recesses of the planarizing silicon oxide insulating film 39 and the upper hard insulating film 31 and the silicon oxide sacrificial insulating film 26 are removed.

  Next, as shown in FIG. 21, a SiCN film (for example, a thickness of about 15 nm) is formed on almost the entire surface of the wafer 1 on the surface 1a side as the third layer wiring auxiliary insulating barrier film 23c by, for example, plasma CVD. Form a film.

  Next, as shown in FIG. 22, as a third-layer wiring main interlayer insulating film 23d (porous low dielectric constant silicon oxide insulating film), for example, by plasma CVD, over almost the entire surface 1a side of the wafer 1, A SiOC film (for example, a thickness of about 150 nm) or the like is formed. Next, as with the second buried wiring layer M2, for example, a copper buried wiring 23w is buried by, for example, a dual damascene method.

  Thereafter, as shown in FIG. 4, the above steps are repeated until the uppermost buried wiring layer M5 is formed, then the pad layer AP is formed, and backgrinding, dicing, etc. are performed as necessary. The wafer 1 is divided into individual chips 2.

3. Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIG. 23)
FIG. 23 is a device schematic cross-sectional view corresponding to FIG. 4 for explaining the outline of the device structure in the semiconductor integrated circuit device according to the embodiment of the present application. Based on this, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Problems of COB (Capacitor Over Bitline) type embedded DRAM:
As described above, in the embedded DRAM (DRAM-embedded logic chip), for example, in the case of a COB type DRAM, for example, the height of the cylindrical memory capacity tends to become higher due to miniaturization. . When trying to store the memory capacity in the premetal insulation layer (referred to as “memory capacity in the premetal layer”), as the thickness of the premetal insulation layer increases, the contact plug becomes longer and longer in the logic area. turn into. This makes it difficult to maintain the performance of logic areas where speed is important. Therefore, by using a wiring layer interstitial memory capacity, an undesired increase in the thickness of the premetal insulating layer can be avoided. However, in general, a low dielectric constant insulating film (a non-porous low dielectric constant insulating film or a porous low dielectric constant insulating film) is often used in the lower half of the multilayer embedded wiring layer. A situation occurs in which the side surface of the capacitor (specifically, the lower electrode or the like) directly contacts the low dielectric constant insulating film. Here, considering the refractory metal nitrides such as titanium and tantalum (TiN, TaN, etc.) frequently used as the lower electrode of the memory capacity, etc., in general, the nitrogen in these refractory metal nitrides is If there is a member which is unstable and easily diffuses in the periphery, the member tends to diffuse to the outside and escape through the portion (desorption of nitrogen from the memory electrode). Relatively hard oxidation (generally speaking, the lower the dielectric constant, the lower the mechanical strength), which is adopted as a premetal insulating film if it is a premetal layer-containing memory capacity. Since it is surrounded by a silicon-based insulating film (non-porous non-low dielectric constant silicon oxide-based insulating film), there is no problem. On the other hand, in the case of the wiring layer intrusion memory capacity, the intrusion portion is mainly the lower half of the multi-layer embedded wiring layer. Therefore, the increase in leakage between the memory capacitors due to the above-mentioned “nitrogen separation from the memory electrode” is a problem. Become. This tendency becomes even stronger in recent advanced devices that tend to be porous low dielectric constant insulating films over several layers above the first buried wiring layer M1. This is because a porous low dielectric constant insulating film having a lower mechanical strength than a non-porous low dielectric constant insulating film is generally considered to have a high diffusibility for nitrogen.

(2) Outline of device structure of each embodiment (including modification) of the present application:
Therefore, in each of the embodiments (including modifications) of the present application, as shown in FIG. 23, in a buried DRAM having a low dielectric constant insulating film LK in a multilayer buried wiring layer M, a cylindrical wiring layer penetration type is provided. By interposing the hard insulating film 37 between the side surfaces of the memory capacitors Ca and Cb and the low dielectric constant insulating film LK, direct contact between the lower electrode of the memory capacitor and the low dielectric constant insulating film LK is avoided.

(3) Process outline of each embodiment (including modifications) of the present application:
In the technique disclosed in Japanese Unexamined Patent Publication No. 2008-130614 (Patent Document 1), an oxygen diffusion blocking film (SiN film) is left at the bottom of the cylinder in order to prevent oxygen from diffusing from below the memory capacity. There is a need. However, in each of the embodiments (including modifications) of the present application, there is no such request. Therefore, as shown in FIG. 10, a hard insulating film at the bottom of the cylinder is self-aligned without using a mask or the like. Can be removed. As shown in FIG. 11, the capacitor lower electrode 32 needs to be in direct contact with the upper-layer capacitor contact plug 17s, and the memory capacitor storage cylinder 36 (for example, diameter: about 150 nm, depth: about 400 nm) has a width. Since it is fine and deep, it is important in terms of process that it can be removed in a self-aligned manner.

4). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, specific description has been given mainly using the embedded metal wiring as an example. However, the present invention is not limited to this, and non-embedded metal wiring such as aluminum-based metal wiring is used. It goes without saying that it can also be applied to what has been done.

  Further, in the above-described embodiment, the description has been specifically given mainly by taking the case of forming a device on a P-type single crystal silicon substrate as an example. However, the present invention is not limited to this, and N-type or It goes without saying that it may be formed on various semiconductor layers on a P-type silicon single crystal substrate, various N-type or P-type epitaxial substrates, insulating substrates (including SOI substrates) and other semiconductor substrates. Absent.

  Further, in the above-described embodiment, the COB type DRAM has been mainly described as an example, but it goes without saying that it can be applied to other types of DRAMs.

1 Semiconductor wafer 1a Wafer or chip surface (first main surface)
1b Back surface of wafer or chip (second main surface)
1s semiconductor substrate (P-type single crystal silicon substrate)
1p substrate P-type region 2 semiconductor chip or chip region 3 DRAM region 3c DRAM array region 3p memory peripheral region (DRAM peripheral circuit region)
4 Logic area 5 Chip peripheral area 6 Chip internal area 7 STI area (element isolation area)
8n N-type source / drain region 8p P-type source / drain region 9 Gate insulating film 10 Gate electrode 11 Side wall 12 Bit line contact W plug 14, 14a, 14b Capacitor contact W plug 15 Silicide film 16 Bit line contact plug 17f Lower layer capacitor contact plug 17s Upper layer capacitor contact plug 18f Lower layer logic part contact plug 18s Middle layer logic part contact plug 18t Upper layer logic part contact plug 19f Lower layer premetal main insulating film 19s Middle layer premetal main insulating film 19t Upper layer premetal main insulating film 20b Bit line base insulating film 20s Premetal middle Etch stop insulating film 21b First layer wiring insulating barrier film 21d First layer wiring main interlayer insulating film (porous low dielectric constant silicon oxide insulating film)
21w First layer embedded wiring 22b Second layer wiring insulating barrier film 22d Second layer wiring main interlayer insulating film (porous low dielectric constant silicon oxide insulating film)
22w Second layer embedded wiring (including vias)
23b Third layer wiring insulating barrier film 23c Third layer wiring auxiliary insulating barrier film 23d Third layer wiring main interlayer insulating film (porous low dielectric constant silicon oxide insulating film)
23w Third layer embedded wiring (including vias)
24b Fourth-layer wiring insulating barrier film 24d Fourth-layer wiring main interlayer insulating film 24w Fourth-layer buried wiring (including vias)
25d Top layer wiring main interlayer insulating film 25w Top layer embedded wiring (including vias)
26 Silicon oxide-based sacrificial insulating film 27 Pad under-layer insulating film 28 Final passivation film 29 Bonding pad 30 Upper electrode & capacitor plate storage recess 31 Upper hard insulating film 32 Capacitor lower electrode (TiN film)
33 Memory capacity insulating film (ZrO ₂ film)
34 Capacitor upper electrode (TiN film)
35 Capacity plate (W film)
35b Insulating barrier film on capacitor plate 36 Memory capacity storage cylinder 37 Hard insulating film 38 Resist film for processing capacitor lower electrode 39 Planarization silicon oxide insulating film AC Active area in memory array AP pad layer BL, BL1, BL2, BL3 , BL4 bit line C1, C2, C3, C4, C5, C6, C7, C8, Ca, Cb Memory capacitor (cylindrical MIM type memory capacity)
DWN Deep N type well region in DRAM region LK Low dielectric constant insulating film M Multilayer wiring layer (Multilayer embedded wiring layer)
M1 First buried wiring layer M2 Second buried wiring layer M3 Third buried wiring layer M4 Fourth buried wiring layer M5 Uppermost buried wiring layer PM Premetal insulating layer PM1 Lower premetal insulating layer PM2 Middle premetal insulating layer PM3 Upper layer Pre-metal insulation layer Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Qnc1, Qnc2 N-type MISFET of memory cell part
Qnc1, Qnc2 N-type MISFET in DRAM area
Nng MISFET in Qng logic area
P-type MISFET in Qpg logic area
R1 DRAM array area Corner cut-out area SA1, SA2 Sense amplifier UC Unit memory cell Vp Plate potential WD1, WD2, WD3, WD4 Word line driver WL, WL1, WL2, WL3, WL4 Word line WNG N-type well area WPC in logic area P-type well region of DRAM region WPG P-type well region of logic region

Claims (12)

Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a DRAM region and a logic region provided on the first main surface;
(C) a premetal insulating layer provided on the first main surface and provided in the DRAM region and the logic region;
(D) A multilayer embedded wiring layer provided on the premetal insulating layer and provided in the DRAM region and the logic region and having a low dielectric constant insulating film;
(E) a plurality of cylindrical MIM memory capacities in the DRAM region extending from the premetal insulating layer to the multilayer embedded wiring layer;
(F) A hard insulating film covering a space between the side surface of each cylindrical MIM type memory capacitor and the low dielectric constant insulating film.     2. The semiconductor integrated circuit device according to claim 1, wherein the low dielectric constant insulating film is a porous film.     3. The semiconductor integrated circuit device according to claim 2, wherein the hard insulating film is a silicon-based insulating film.     3. The semiconductor integrated circuit device according to claim 2, wherein the hard insulating film is a silicon oxide insulating film.     3. The semiconductor integrated circuit device according to claim 2, wherein the hard insulating film is a silicon oxide insulating film formed by plasma TEOS-CVD. 6. The semiconductor integrated circuit device according to claim 5, wherein each cylindrical MIM type memory capacity has the following:
(E1) lower electrode;
(E2) a capacitive insulating film provided in the lower electrode;
(E3) An upper electrode provided on the capacitive insulating film and provided in the lower electrode;
Here, the lower electrode is connected to a capacitor contact plug. A method of manufacturing a DRAM-embedded semiconductor integrated circuit device including the following steps:
(A) forming a premetal insulating layer on the first main surface of the wafer;
(B) forming a multilayer embedded wiring layer having a low dielectric constant insulating film on the premetal insulating layer;
(C) exposing a top end of the capacitive contact plug from a bottom surface of the cylindrical hole by forming a plurality of cylindrical holes extending through the multilayer embedded wiring layer and reaching the inside of the premetal insulating layer;
(D) a step of forming a hard insulating film on the side surface, the bottom surface, and the outside of each cylindrical hole;
(E) exposing the upper end of the capacitive contact plug in a self-aligning manner by performing anisotropic dry etching on the hard insulating film;
(F) After the step (e), forming a lower metal electrode film on the side surface, the bottom surface, and the outside of each cylindrical hole.     8. The method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to claim 7, wherein the low dielectric constant insulating film is a porous film.     9. The method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to claim 8, wherein the hard insulating film is a silicon-based insulating film.     9. The method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to claim 8, wherein the hard insulating film is a silicon oxide insulating film.     9. The method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to claim 8, wherein the hard insulating film is a silicon oxide insulating film formed by plasma TEOS-CVD. 12. The method of manufacturing a DRAM-embedded semiconductor integrated circuit device according to claim 11, further comprising the following steps:
(G) removing the outer metal electrode film outside the cylindrical holes;
(H) After the step (g), forming a capacitor insulating film of an MIM type memory capacitor on the side surface, the bottom surface, and the outside of each cylindrical hole;
(I) A step of forming an upper metal electrode of the MIM type memory capacitor on the high dielectric constant insulating film.

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