JP2014021753A - Parallel bus circuit, and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of signal lines which connect ports to each other and to carry on serial communication even when bus abnormality is detected.SOLUTION: Serial communication interfaces 13, 23 are connected to respective bits of a parallel bus 4 through a majority circuit 14 or majority circuit 24. When each of the serial communication interfaces outputs data through the majority circuit 14 or the majority circuit 24, the same data is output to all the bits of the parallel bus 4. When data is input to each of the serial communication interfaces through the parallel bus 4, on the other hand, the majority circuit 14 or majority circuit 24 determines values which are indicated more among values of the respective bits of the parallel bus 4. Consequently, a need to install a serial bus is eliminated and even if abnormality occurs to the parallel bus 4, serial communication can be carried on.

Description

  The present invention relates to a parallel bus circuit method and a communication system, and more particularly to a parallel bus circuit and a communication system that enable continuation of serial communication even when an abnormality such as disconnection occurs in a bit of a parallel bus.

  In communication systems consisting of multiple devices, a bus failure such as preparing a dedicated monitoring bus or duplicating the bus in preparation for a failure of the bus used to transmit data between boards Measures are taken to prevent the loss of time communication paths. Thereby, small-scale data transmission can be continued. However, in order to apply such a device, the number of signals connected between the boards increases, and the communication bus line becomes large, resulting in a problem that the scale of the entire system is increased.

  As a well-known example technique in this field, Patent Document 1 describes system reliability by automatically switching between the active system and the standby system when a failure occurs in the own system or the counterpart system. Techniques for improving are disclosed. Specifically, the active system and the standby system include an operation state monitoring unit that monitors the operation state of the own system and generates an alarm signal. The active system and the standby system include a buffer unit that receives a switching state signal of the counterpart system. The active system and the standby system include connection control signal generation means for reading the received signal of the buffer unit and generating a connection control signal. In addition, the active system and the standby system include a switching control unit that generates a switching control signal using an alarm signal or a connection control signal. In addition, the active system and the standby system include a switching unit that connects or disconnects the transmission / reception line of the communication control unit from the outside by a switching control signal.

  Patent Document 2 discloses a technique for improving reliability by duplicating a common bus connecting between a plurality of load balancing processors and a diagnosis / test processor. Specifically, each of the plurality of load distribution processors has a function of detecting the necessity of its own diagnosis / test and making a diagnosis / test request to the diagnosis / test processor. The diagnosis / test processor has a function to cope with the above request, and also has a function to detect an abnormality in the state of exchanging business data via the common bus and cope with this abnormality.

  Patent Document 3 discloses a method for increasing the average failure interval of a computer system. Specifically, a spare line and a multiplexer are arranged in the bit transfer. For example, when the line of the signal C fails, the signal C is switched and input from one MUX to the other MUX. This switching input is realized by a selection signal. The same switching is performed for the input of two lines whose numbers are larger than the line number related to the failure.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that allows a host CPU to continue processing via an IOP serial interface as an alternative path when a PCI control unit of an IOP fails. Specifically, in an information processing system including an intelligent IO processor, a serial interface included in the intelligent IO processor and a serial interface included in the information processing system are connected via a changeover switch. Then, when an operation interface control unit with the host CPU of the intelligent IO processor fails, an alternative path for instructing control from the serial interface of the information processing system to the serial interface of the intelligent IO processor is established.

  Further, Patent Document 5 discloses a communication circuit, a communication network, and a connecting device that can realize highly reliable communication with a simple wiring system. Specifically, a signal distribution unit is provided that is connected to one end side of a signal line including three or more signal lines and distributes and transmits a signal input to the input terminal to each signal line. Also, a majority selection receiving circuit that is connected to the other end of the signal line and compares a plurality of received signals received via each signal line, selects and receives a received signal with a large number of matches as true, and outputs it to the output terminal. Prepare.

Japanese Examined Patent Publication No. 58-041535 Japanese Patent Publication No. 03-041863 Japanese Patent Publication No. 08-031856 JP 11-259378 A Japanese Patent Application Laid-Open No. 2011-146953

  The method of automatically switching between the active system and the standby system when a failure occurs, such as the device described in Patent Document 1, is an effective means for improving the system reliability. However, the scale of the communication bus line cannot always be reduced for the reasons described later. The method described in Patent Document 2 is also an effective means for improving the reliability of the system. However, like the device described in Patent Document 1, the scale of the bus line for communication cannot always be reduced.

  A method for increasing the average failure interval of a computer system, such as the device described in Patent Document 3, is also an effective means for improving the reliability of the system. However, like the device described in Patent Document 1, the scale of the bus line for communication cannot always be reduced. A method of providing an alternative path to the host CPU in case the IOP PCI control unit fails, such as the device described in Patent Document 4, is an effective means for improving the reliability of the system. However, like the device described in Patent Document 1, the scale of the bus line for communication cannot always be reduced.

  Furthermore, a circuit that realizes highly reliable communication by a simple wiring system using a majority selection receiving circuit, such as the circuit described in Patent Document 5, does not correspond to a failure, and does not necessarily It is not always possible to reduce the scale of a communication bus line.

  By the way, in a communication system configured by incorporating a plurality of devices, a bus dedicated for monitoring is prepared or a bus is duplicated in case a bus used for data transmission between boards fails. It is necessary to take measures to prevent the communication path at the time of failure from being lost. However, the conventional parallel bus circuit as described above has a problem that the circuit scale of the entire system becomes large. Hereinafter, this point will be described with reference to FIG.

  FIG. 4 is a circuit diagram showing a circuit configuration of a conventional parallel bus circuit. In the figure, the board 1 and the board 2 are connected by a parallel bus 4, a bus abnormality notification line 3 and a serial bus 5. In the board 1, the parallel bus 4 is connected to the communication host 11 via the parallel communication interface 12. Similarly, in the board 2, the parallel bus 4 is connected to the communication host 21 via the parallel communication interface 22. In the board 1, the serial bus 5 is connected to the communication host 11 via the serial communication interface 13.

  Similarly, in the board 2, the serial bus 5 is connected to the communication host 21 via the serial communication interface 23. Furthermore, the bus abnormality notification line 3 is connected to the communication host 11 in the board 1. Similarly, in the board 2, the bus abnormality notification line 3 is connected to the communication host 21. When the communication host 11 and the communication host 21 detect a bus abnormality, the abnormality is notified to the opposite communication host via the bus abnormality notification line 3, and the communication is continued by switching the communication path to the serial bus 5. . However, in such a conventional parallel bus circuit, since it is necessary to prepare a spare communication interface, it is a problem that the number of signal lines connecting between boards increases.

  The present invention has been made in view of the above problems, and it is possible to save the number of signal lines connecting between boards, and to enable serial communication to be continued even when a bus abnormality is detected, and a parallel bus circuit and The object is to provide a communication system.

  In order to solve the above-described problems, a parallel bus circuit according to the present invention includes a parallel communication interface unit included in each of the plurality of boards for performing parallel communication between the plurality of boards, and serial communication between the plurality of boards. Serial communication interface means included in each of the plurality of boards, a parallel bus connecting the plurality of boards, a majority circuit connected between the parallel bus and the serial communication interface means, and parallel communication It is connected to the interface means and the serial communication interface means, and has means for detecting the abnormality of the parallel bus. When the parallel bus is normal, it transmits / receives information to / from other boards via the parallel communication interface means. Communication interface means and majority circuit Includes a communications host to transmit and receive other boards and information over to connect the communication between a plurality of boards hosts, the abnormality of the parallel bus and a bus abnormality notification line for notifying each other between the communicating hosts.

  The communication system according to the present invention includes the parallel bus circuit described above.

  As is apparent from the above description, according to the present invention, the serial bus that connects the boards is unnecessary, and an abnormality such as disconnection occurs in any bit of the parallel bus that connects the boards. Even if it exists, serial communication between boards can be continued.

It is a circuit diagram which shows the circuit structure of the parallel bus circuit which concerns on embodiment of this invention. FIG. 10 is an explanatory diagram showing a correspondence relationship as an example when a serial communication interface input signal is converted into a parallel communication interface output signal in the majority circuit. FIG. 5 is an explanatory diagram showing a correspondence relationship as an example when a parallel communication interface input signal is converted into a serial communication interface output signal in the majority circuit. It is a circuit diagram which shows the circuit structure of the conventional parallel bus circuit.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a parallel bus circuit and a communication system of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration of a parallel bus circuit according to an embodiment of the present invention. In the figure, the same reference numerals are given to the portions overlapping with those in FIG. In the figure, the parallel bus circuit of this embodiment includes boards 1 and 2, a bus abnormality notification line 3, a parallel bus 4, communication hosts 11 and 21, parallel communication interfaces 12 and 22, serial communication interfaces 13 and 23, and a majority decision. Circuits 14 and 24 are provided. The parallel bus circuit of the present invention is a built-in type such as a radio base station apparatus, and can be applied to a general system in which boards are connected by a parallel bus.

  The characteristic functions of the parallel bus circuit of this embodiment will be described below with reference to FIG. In the parallel bus circuit of this embodiment, when a bus abnormality is detected in the parallel bus circuit, the transmitting side outputs the same serial data to all the bits of the bus, and the receiving side extracts serial data using a majority circuit. To do. Thus, even when a bus abnormality is detected, the communication can be continued at a low speed.

  Hereinafter, connection between circuit elements in the parallel bus circuit of the present embodiment will be described with reference to FIG. In FIG. 1, the board 1 and the board 2 are connected by a parallel bus 4 and a bus abnormality notification line 3. More specifically, the parallel bus 4 in the board 1 is connected to the communication host 11 via the parallel communication interface 12. Similarly, the parallel bus 4 in the board 2 is connected to the communication host 21 via the parallel communication interface 22. In the board 1, the parallel bus 4 is connected to the communication host 11 via the majority circuit 14 and the serial communication interface 13.

  Similarly, the parallel bus 4 in the board 2 is connected to the communication host 21 via the majority circuit 24 and the serial communication interface 23. Further, the bus abnormality notification line 3 in the board 1 is connected to the communication host 11. Similarly, the bus abnormality notification line 3 in the board 2 is connected to the communication host 21.

  The operation of the parallel bus circuit of this embodiment will be described below with reference to FIG. Usually, the board 1 and the board 2 communicate via the parallel bus 4. On the other hand, when the communication host 11 or the communication host 21 detects an abnormality in the parallel bus 4, an abnormal state is output to the bus abnormality notification line 3. Then, the communication host 11 and the communication host 21 that have input the abnormal state via the bus abnormality notification line 3 switch the communication path to the serial communication interface 13 and the serial communication interface 23.

  The serial communication interface 13 and the serial communication interface 23 are connected to each bit of the parallel bus 4 via the majority circuit 14 or the majority circuit 24. When data is output to the parallel bus 4 via the majority circuit 14 or the majority circuit 24 of each serial communication interface, the same data is output to all the bits of the parallel bus 4.

  On the contrary, at the time of data input to each serial communication interface via the parallel bus 4, the majority circuit 14 or the majority circuit 24 indicates the value which is indicated more in the value of each bit of the parallel bus 4. To decide. Therefore, for example, a value of 1 is determined if 1 is shown, and a value of 0 is determined if 0 is shown. With this configuration, a parallel bus circuit that can continuously perform serial communication even when an abnormality such as disconnection occurs in a bit of the parallel bus 4 is realized.

  The operation when a failure occurs in the parallel bus circuit of this embodiment will be described below with reference to FIG. Usually, the board 1 and the board 2 communicate via the parallel bus 4. Hereinafter, as an example, an operation when a disconnection occurs in a certain bit of the parallel bus 4 will be described. When the communication host 11 detects an abnormality in the parallel bus 4, the communication host 11 outputs an abnormal state to the bus abnormality notification line 3, and the serial communication interface 13 and the majority circuit 14 are connected to the communication path with the communication host 21. Switch to the communication path.

  When the abnormal state is input via the bus abnormality notification line 3, the communication host 21 switches the communication path with the communication host 11 to the communication path via the serial communication interface 23 and the majority circuit 24. Similarly, when the communication host 21 detects an abnormality in the parallel bus 4, the communication path with the communication host 11 is switched to the communication path via the serial communication interface 23 and the majority circuit 24 as described above.

  FIG. 2 is an explanatory diagram showing a correspondence relationship as an example when the serial communication interface input signal is converted into a parallel communication interface output signal in the majority circuit 14. As shown in the figure, when a failure occurs in the parallel bus 4 and the communication path is switched as described above, the majority circuit 14 converts the value input from the serial communication interface 13 into the parallel as shown in FIG. Output to all the bits constituting the bus 4.

  FIG. 3 is an explanatory diagram showing a correspondence relationship as an example when the majority communication circuit 14 converts a parallel communication interface input signal into a serial communication interface output signal. The data input from the parallel bus 4 to the majority circuit 14 counts the number of binary numbers, which are the values of the bits constituting the data, for each of the above values, and uses the larger number of binary numbers for serial communication. It is output as the value of the bits constituting the output signal of the interface 13. However, if the number of bits having a binary value of 0 is the same as the number of bits having a value of 1 of the binary number, the output signal of the serial communication interface 13 is configured with a binary number of 0. Output as bit value. The majority circuit 24 also operates in the same manner as the majority circuit 14 described above.

  In this example, since a disconnection has occurred in a certain bit of the parallel bus 4, the 8-bit data received by the majority circuit 14 or the majority circuit 24 may be erroneous by 1 bit. However, since the correct data is received in the other 7 bits, the majority circuit 14 or the majority circuit 24 can correctly determine the original serial data as a majority output in units of 8 bits of data. In this example, the case where the parallel bus 4 is a bus composed of 8-bit signal lines is shown, but in this case, any of the 8-bit signal lines constituting the parallel bus 4 can be up to 3 bits. If the signal line is faulty, serial communication can be performed normally.

  In the parallel bus circuit according to this embodiment, when the abnormality of the parallel bus 4 is detected, the board 1 and the board 2 are switched to a circuit system that performs serial communication. In any board, the value of the bit of the serial communication signal is output to all bits constituting the parallel bus 4 at the time of transmission. At the time of reception, the value of the serial bit is determined using the majority circuit 14 or the majority circuit 24. With this configuration, it is not necessary to install a serial bus that connects boards, and serial communication between boards can be performed even if an abnormality such as disconnection occurs in any bit of the parallel bus 4. There is an effect that can be carried out continuously.

  In addition, due to the above effects, it is not necessary to install double communication paths between the board 1 and the board 2, and a parallel bus 4 for parallel communication is installed between the board 1 and the board 2. You can just do it. In this way, the circuit scale of the entire system including the board 1 and the board 2 can be reduced.

  In the parallel bus circuit according to the above-described embodiment, the number of bits of the parallel bus 4 is 8 bits. However, in general, the number of bits of the parallel bus 4 of the parallel bus circuit according to the present invention is not limited. In general, when the parallel bus 4 is an N-bit bus, the above-described implementation is performed even if there is an N / 2-1 bit error when N is an even number and an N / 2 (truncated) bit error when N is an odd number. Serial communication can be continued by the same operation as the parallel bus circuit according to the embodiment.

  Further, in the parallel bus circuit according to the above-described embodiment, two boards are connected by the parallel bus 4, but in general, in the parallel bus circuit according to the present invention, a system having a configuration in which a plurality of arbitrary boards are connected. It is also possible to apply to. In this case, a bus arbitration circuit can be added. As a method for detecting an abnormality in the parallel bus, a method of adding a commonly known parity bit or CRC to the system is also possible.

1 board 2 board 3 bus abnormality notification line 4 parallel bus 11 communication host 21 communication host 12 parallel communication interface 22 parallel communication interface 13 serial communication interface 23 serial communication interface 14 majority circuit 24 majority circuit

Claims (4)

Parallel communication interface means included in each of the plurality of boards for performing parallel communication between the plurality of boards;
Serial communication interface means included in each of the plurality of boards for performing serial communication between the plurality of boards;
A parallel bus connecting the plurality of boards;
A majority circuit connected between the parallel bus and the serial communication interface means;
Connected to the parallel communication interface means and the serial communication interface means, and has means for detecting an abnormality of the parallel bus, and when the parallel bus is normal, transmits and receives information to and from other boards via the parallel communication interface means. A communication host that transmits and receives information to and from other boards via the serial communication interface means and the majority circuit when the parallel bus is abnormal;
A parallel bus circuit comprising: a bus abnormality notification line for connecting the communication hosts of the plurality of boards and notifying the communication host of the occurrence of an abnormality in the parallel bus. The serial communication interface means inputs a transmission signal sent from the communication host at the time of transmission and sends a predetermined output signal corresponding to the input to the majority circuit, and is sent from the majority circuit at the time of reception. The parallel bus circuit according to claim 1, wherein a transmission signal is input and a predetermined output signal corresponding to the input is transmitted to the communication host. The majority circuit sends a binary signal sent from the serial communication interface means to all the communication lines in bit units constituting the parallel bus at the time of transmission, and a bit unit constituting the parallel bus at the time of reception. The parallel bus circuit according to claim 2, wherein a binary signal determined by majority decision of binary signal values of all communication lines is sent to the serial communication interface means.   A communication system comprising the parallel bus circuit according to any one of claims 1 to 3.

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