JP2014017528A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce wiring resistance of a wire which connects an output pad formed in a semiconductor element and an output terminal of an internal circuit.SOLUTION: For each of a plurality of wiring regions each formed along each side of a substrate, wiring resistance values per unit wiring length of wires formed in the respective wiring regions are made different from each other. The semiconductor element comprises, for example: a plurality of first output pads formed along one side of the outer periphery of the substrate; a plurality of second output pads formed along at least one of a side opposite to the one side and a side adjacent to the one side; and a plurality of internal circuits each of which includes an output terminal connected to any of the first and second output pads, and which are formed on the substrate along one side such that each output terminal is arranged on the one side. The wiring region includes first and second wiring regions adjacent to the first and second output pads, respectively. The wiring resistance value per unit wiring length of the wire formed in the second wiring region is lower than the wiring resistance value per unit wiring length of the wire formed in the first wiring region.

Description

  The present invention relates to a semiconductor element, and more particularly to a semiconductor element in which output pads are arranged along a plurality of sides on the outer periphery thereof.

  In the display device, a driver for driving and controlling each pixel is mounted. However, in recent years, the number of outputs of one driver has increased with the increase in the size and definition of the display device and the reduction in the number of mounted drivers. There is a tendency. The number of outputs is generally 480 or 720, but 960-class drivers are also beginning to be required.

  The driver is formed with an IC chip (semiconductor element), but when the number of outputs increases, a plurality of output pads for outputting output signals to an external display panel are arranged along one side of the outer periphery of the semiconductor element. Not only that, it is necessary to arrange them on other sides.

  The number of output pads is at least the number of internal circuits (circuits that generate output signals from input signals and output them to the output pads) provided in the semiconductor element, but the pitch between the output pads is the output terminal provided in each internal circuit. If the output pad is provided along only one side of the semiconductor element, the area of the semiconductor element increases. Therefore, output pads are formed along a plurality of sides on the outer periphery of the semiconductor element to suppress an increase in the area of the semiconductor element. Note that the input pads for inputting input signals from the outside to the internal circuit are commonly used in a plurality of internal circuits (for example, switching to input each input signal with a time difference), and the number of input pads is greater than that of the output pads. Less is enough.

  FIG. 5 is a diagram illustrating an arrangement example of output pads. As shown in FIG. 5, a plurality of output pads are formed along one side (hereinafter referred to as a first side) 121 of the outer periphery of the semiconductor element 100. A plurality of input pads are formed along the second side 122 at the center in the extending direction of a side 122 (hereinafter referred to as a second side) opposite to the first side 121. Further, a plurality of output pads are formed along the second side 122 at both sides in the extending direction of the second side 122.

  Further, as shown in FIG. 5, a plurality of internal circuits 110 are formed in the central portion of the semiconductor element 100. Each of these internal circuits 110 is arranged in a certain direction so that each of its output terminals 112 is arranged along the first side 121 side. The output terminal 112 and the output pad of each internal circuit 110 are connected by wiring, and the input terminal 111 and the input pad of each internal circuit 110 are connected by wiring (illustration of wiring is omitted here). .

  However, in order to connect the output terminal 112 of the internal circuit 110 and the output pad formed along the second side 122, it is necessary to form a routing wiring that bypasses the internal circuit group. This increases the wiring length and the wiring resistance.

  As a result, the length of each wiring connecting the output terminal 112 of the internal circuit 110 and the output pad varies, and the wiring resistance varies.

  By the way, the following Patent Document 1 describes a liquid crystal driver for the purpose of preventing an increase in chip size. Specifically, the signal lines of the liquid crystal panel are sequentially grouped by an integer multiple of 3 in the liquid crystal driver, and a positive / negative pair of gradation voltage selection decoders and positive / negative are set for two adjacent groups. Provide a set of output amplifiers. Further, a switch for passing or blocking the image signal corresponding to each signal line of the liquid crystal panel is provided, and signals transmitted between the switch and the output amplifier and to the previous stage of the decoder are passed or crossed. By providing a switching circuit, an increase in chip size is prevented.

  Further, in Patent Document 2 below, a connection wiring connected to a wiring pattern is formed on an insulating film, and a semiconductor element surface bump is formed in addition to the peripheral portion on the semiconductor element. There is described a semiconductor device that connects an element surface bump and a wiring pattern, and further connects a semiconductor element surface bump and another semiconductor element surface bump.

JP 2007-163913 A JP 2006-80167 A

  However, as described above, the technique described in Patent Document 1 is a configuration in which signal lines of a liquid crystal panel are grouped and a decoder and an output amplifier are provided corresponding to the group, and the configuration depends on the liquid crystal panel. However, there is a problem that it is impossible to prevent an increase in chip size with a single semiconductor element.

  Further, in the technique described in Patent Document 2, although it is possible to reduce the number of routing wires, there is no contrivance for suppressing the resistance value of each routing wire.

  The present invention has been proposed to solve the above-described problems, and provides a semiconductor element capable of suppressing the wiring resistance of the wiring connecting the output pad formed in the semiconductor element and the output terminal of the internal circuit. The purpose is to do.

  In order to achieve the above object, the semiconductor element of the present invention has a wiring resistance value per unit wiring length of a wiring formed in each wiring region for each of a plurality of wiring regions formed along each side of the substrate. It is characterized by different. For example, a plurality of first output pads formed along one side of the outer periphery of the substrate, and a plurality of second output pads formed along at least one of the side opposite to the one side and the side adjacent to the one side And an output terminal connected to any one of the plurality of first output pads and the plurality of second output pads, wherein each of the output terminals is arranged along the one side. A plurality of internal circuits formed on the substrate along the one side, and the wiring region is a wiring region adjacent to the plurality of first output pads, and one of the plurality of output terminals. A wiring region adjacent to each of the plurality of second output pads; a wiring region adjacent to each of the plurality of first output pads; and a wiring region adjacent to the plurality of second output pads. Multiple second output pads A resistance value per unit wiring length of the wiring formed in the second wiring area is formed in the first wiring area. It is characterized by being lower than the resistance value per unit wiring length.

  Since the wiring formed in the first wiring area is formed without bypassing other internal circuits, the wiring length can be short. However, the wiring formed in the second wiring area bypasses the other internal circuits. Therefore, the wiring length becomes longer than the wiring in the first wiring region, and the wiring resistance value increases. Accordingly, the wiring resistance of the entire second wiring region can be suppressed by forming the wiring of the second wiring region so that the resistance value per unit wiring length is lower than that of the wiring of the first wiring region.

  Note that, by varying the wiring width per unit wiring length, the resistance value per unit wiring length of the wiring formed in the second wiring region is changed to the unit wiring of the wiring formed in the first wiring region. You may make it lower than the resistance value per length.

  Also, a plurality of wiring layers are stacked on the substrate, and the resistance value per unit wiring length of the wiring formed in the second wiring region can be obtained by varying the number of wiring layers. You may make it lower than the resistance value per unit wiring length of the wiring formed in 1 wiring area | region.

  Further, by varying the wiring thickness per unit wiring length, the resistance value per unit wiring length of the wiring formed in the second wiring region is changed to the unit wiring of the wiring formed in the first wiring region. You may make it lower than the resistance value per length.

  Further, by using a material having a different resistivity, the resistance value per unit wiring length of the wiring formed in the second wiring region can be reduced per unit wiring length of the wiring formed in the first wiring region. You may make it make it lower than resistance value.

  As described above, according to the present invention, it is possible to suppress the wiring resistance of the wiring connecting the output pad formed in the semiconductor element and the output terminal of the internal circuit.

It is a figure which shows the structural example of the semiconductor element which concerns on 1st Embodiment. It is the enlarged view to which the part enclosed with the broken line of FIG. 1 was expanded. It is a figure which shows the other structural example of a semiconductor element. It is a figure which shows the structural example of the semiconductor element which concerns on 2nd Embodiment. It is a figure which shows the example of arrangement | positioning of the input pad in a semiconductor element, an output pad, and an internal circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a diagram illustrating a configuration example of a semiconductor element 10 according to the present embodiment.

  As shown in FIG. 1, the semiconductor element 10 according to the present embodiment is rectangular, and the outer periphery thereof has a rectangular shape composed of a pair of long sides and a pair of short sides. In the present embodiment, one side of the pair of long sides (upper side in FIG. 1) is referred to as a first side 31, and the side facing the first side 31 is referred to as a second side 32. . Also, one side of the pair of short sides (the left side in FIG. 1) is referred to as a third side 33, and the side facing the third side 33 is referred to as a fourth side 34.

  A plurality of output pads are formed in a region along the first side 31. A plurality of input pads 12 are formed along the second side 32 in the central portion in the extending direction of the second side 32 facing the first side 31. Further, a plurality of output pads are formed along the second side 32 on both sides in the extending direction of the second side 32.

  In the following description, the output pad formed along the first side 31 is referred to as a first output pad 14A, and is adjacent to the second side 32 and the first side 31 facing the first side 31. The output pad formed along at least one of the third side 33 and the fourth side 34 (the output pad formed along the second side 32 in the example shown in FIG. 1) The two output pads 14B are called and distinguished. However, since the first output pad 14A and the second output pad 14B have the same configuration and the same function, when they are described without distinction between them, the reference numeral is omitted and the output pad 14 is referred to. .

  As shown in FIG. 1, a plurality of internal circuits 16 are formed in the central portion of the semiconductor element 10. Each internal circuit 16 includes an input terminal 17 and an output terminal 18. Each of the input terminals 17 is connected to one of the plurality of input pads 12, and each of the output terminals 18 is connected to one of the plurality of output pads 14. Has been. The internal circuit 16 generates an output signal based on the input signal input from the input pad 12 and outputs the output signal to the output pad 14 connected to the output terminal 18. The plurality of internal circuits 16 are formed side by side along the first side 31 in a fixed orientation so that each of the output terminals 18 is arranged along the first side 31 side. .

  In the present embodiment, each of a plurality of wirings connecting any one of the output terminals 18 of the plurality of internal circuits 16 and one of the first output pads 14A is referred to as a first wiring 41, and the outputs of the plurality of internal circuits 16 are connected. Each of the plurality of wirings connecting any one of the terminals 18 and any one of the second output pads 14B is referred to as a second wiring 42. In FIG. 1, the wiring for connecting the input pad 12 and the input terminal 17 is not shown.

  As shown in FIG. 1, the first wiring 41 connects the first output pad 14 </ b> A formed along the first side 31 and the output terminal 18 arranged along the first side 31. Therefore, the wiring is formed without bypassing the other internal circuit 16. Therefore, the wiring length can be short. However, the second wiring 42 is a wiring that connects the second output pad 14B formed along the second side 32 and the output terminal 18 arranged along the first side 31 side. It is formed by being routed so as to bypass the other internal circuit 16. This increases the wiring length and increases the wiring resistance value.

  In the present embodiment, a plurality of second wirings 42 are formed as described below in order to suppress variations in wiring resistance caused by variations in wiring length, and each unit wiring length of each second wiring 42 is determined. The wiring resistance value of the first wiring 41 is lower than that of the plurality of first wirings 41.

  FIG. 2 is an enlarged view in which a portion surrounded by a broken line in FIG. 1 is enlarged.

  In the present embodiment, each of the second wirings 42 is formed so as to have a wiring width that is thicker than each of the first wirings 41 on average. In other words, the wiring width per unit wiring length of each second wiring 42 is formed to be wider than the wiring width per unit wiring length of each first wiring 41.

  Further, in the present embodiment, each second wiring 42 is formed so that the wiring width in the region closer to the second side 32 is larger. That is, as shown in FIG. 2, the wiring width of the region along the third side 33 of each second wiring 42 is made wider than the wiring width of the region along the first side 31, and the second side The wiring width in the region along 32 is made wider than the wiring width in the region along the third side 33.

  Of the regions where the routing wires of the second wires 42 are arranged, the regions along both ends of the side (second side 32) on the input pad 12 arrangement side are regions where the wiring density is particularly low (sparse). Since there is a margin, wiring can be performed without increasing the chip area even if the wiring width is increased. Further, the region along the third side 33 is also compared with the region along the first side 31 in which the arrangement density is increased by forming the first wiring 41 that connects the first output pad 14A and the output terminal 18. Thus, since the wiring density is low (sparse), the wiring width can be made wider than the area along the first side 31.

  Although not shown in FIG. 2, the first wiring 41 that connects the output terminal 18 and the first output pad 14A is formed in a region along the first side 31 having a high wiring density. The wiring 42 is formed with a narrow wiring width that is substantially the same as the wiring width in the region along the first side 31.

  Such a wiring structure is formed by using a well-known lithography technique, and a fine wiring pattern is formed by etching.

The overall wiring resistance value R is obtained by the following formulas (1) and (2).
R = L × r (1)
r = ρ / (W × H) (2)
Here, r: wiring resistance value per unit wiring length, ρ: resistivity, L: wiring length, W: wiring width, H: wiring height (wiring thickness).

  Accordingly, the second wiring 42 is formed by increasing the wiring width W so that the wiring resistance value per unit wiring length is lower than that of the first wiring 41 even when the wiring length L of the second wiring 42 is increased. As a result, the wiring resistance value R is suppressed.

  FIG. 3 is a diagram illustrating another configuration example of the semiconductor element. In this configuration example, the output pad 14 is formed not only in the region along the first side 31 and the second side 32 on the outer periphery of the semiconductor element but also in the region along the third side 33. The output pad 14 formed in the region along the third side 33 is also referred to as a second output pad 14B. Similarly to the above, each of the wirings connecting the second output pad 14B and the output terminal 18 is referred to as a second wiring 42.

  Also in this configuration example, the second wiring 42 that connects the output terminal 18 of the internal circuit 16 and the second output pad 14B is formed so as to be thicker than the wiring width of the first wiring 41 on average. In other words, the wiring width per unit wiring length of the second wiring 42 is formed to be wider than the wiring width per unit wiring length of the first wiring 41. Further, in this configuration example, each second wiring 42 is formed so that the wiring in the region closer to the second side 32 has a larger wiring width. That is, as shown in FIG. 3, the wiring width of the region along the third side 33 of each second wiring 42 is made wider than the wiring width of the region along the first side 31, and the second side The wiring width in the region along 32 is made wider than the wiring width in the region along the third side 33.

  Even with such a configuration, the same effect as described above can be obtained.

  Even when the second output pad 14B is formed along the fourth side 34, the same effect as described above can be obtained by forming the second wiring 42 by increasing the wiring width as described above. can get.

  Further, the present invention is not limited to the semiconductor element of the above-described embodiment. For example, the wiring width in the region along the third side 33 is not widened, and only the wiring width in the region along the second side 32 is wide. You may make it do.

  [Second Embodiment]

  In the first embodiment, the example in which the second wiring 42 is formed so that the wiring width per unit wiring length of the second wiring 42 is wider than the wiring width per unit wiring length of the first wiring 41 has been described. However, in the present embodiment, an example in which the second wiring 42 is formed using a plurality of wiring layers to suppress wiring resistance will be described.

  A semiconductor element generally has a multilayer wiring structure in which a plurality of wiring layers are stacked on a silicon substrate. By using the plurality of wiring layers and increasing the number of wiring layers used for forming the second wiring 42 than the number of wiring layers used for forming the first wiring 41, wiring per unit wiring length of the second wiring 42 The resistance value can be kept low.

  FIG. 4 shows a configuration example of the semiconductor element of this embodiment. In this configuration example, the second output pad 14B is formed not only in the region along the first side 31 and the second side 32 on the outer periphery of the semiconductor element but also in the region along the third side 33. Yes. Except for the arrangement of the output pad 14 and the wiring method of the second wiring 42, the configuration is the same as that of FIG. 1 of the first embodiment, and thus further description thereof is omitted here.

  As shown in FIG. 4, only the uppermost layer (first layer) of the plurality of stacked wiring layers is used for a region along the first side 31 (hereinafter referred to as a first region), and each first The wiring 41 and a part of each second wiring 42 are formed.

  In a region along the third side 33 (hereinafter referred to as a third region), a part of each second wiring 42 is formed by using a first layer and a wiring layer (second layer) below the first layer. Form.

  More specifically, a through hole for connecting the first layer and the second layer is formed at each of predetermined branch positions on the wiring path of each second wiring 42 in the third region, and Each of the second-layer wirings 42 of the first layer routed from the first region is branched from the branch position, and is also formed on the second layer. Thus, each of the second wirings 42 is formed in a state where the first layer wirings and the second layer wirings are routed side by side in the vertical direction (stacking direction of the plurality of wiring layers).

  In the region along the second side 32 (hereinafter referred to as the second region), the first layer, the second layer, and the wiring layer (third layer) below the second layer are used to form the second wiring 42. Form part.

  More specifically, a through hole for connecting the first layer, the second layer, and the third layer is provided at each of predetermined branch positions on the wiring path of each second wiring 42 in the second region. In the same manner as described above, each of the second wirings 42 is branched and formed into three wiring layers of the first layer to the third layer. Thus, each of the second wirings 42 is formed in a state where the first layer wiring, the second layer wiring, and the third layer wiring are routed side by side in the vertical direction (stacking direction of the plurality of wiring layers). Is done.

  In order to connect the end of each second wiring 42 to the second output pad 14B, it is necessary to join (short-circuit) each second wiring 42 formed in a plurality of layers into one wiring layer. Accordingly, a through hole is formed at each of the predetermined joining positions on the wiring path of each second wiring 42 in the second region, and the first wiring 41 branched into three wiring layers at the joining position is, for example, the first wiring 41. Each of the ends of the second wiring 42 is connected to the first output pad 14A.

  As described above, since the number of wiring layers used for forming each of the second wirings 42 is larger than the number of wiring layers used for forming each of the first wirings 41, the second wiring 42 is formed. The wiring resistance value of the wiring 42 can be suppressed.

  Even when the second output pad 14B is formed along the fourth side 34, the same effect as described above can be obtained by forming the second wiring 42 using a plurality of wiring layers as described above. Is obtained.

  The present invention is not limited to the semiconductor element of the above embodiment. For example, the region along the third side 33 is formed using only one wiring layer, and only in the region along the second side 32. You may make it form using a some wiring layer.

  [Other embodiments]

  Further, each of the plurality of second wirings 42 may be formed in a wiring layer that is higher than each of the plurality of first wirings 41. As for the wiring layer laminated | stacked on a semiconductor element, there are many things whose layer thickness becomes thick, so that an upper layer (wiring thickness becomes thick). Therefore, by forming the plurality of second wirings 42 in the wiring layer that is higher than each of the plurality of first wirings 41, the wiring thickness per unit wiring length of each of the second wirings 42 is larger than that of the first wiring 41. The wiring resistance per unit wiring length can be suppressed.

  Furthermore, each of the plurality of second wirings 42 may be formed of a material having a lower resistivity than each of the plurality of first wirings 41. For example, among the plurality of wiring layers, the first layer is a wiring layer made of Cu, the second layer is a wiring layer made of Al, each of the second wirings 42 is a first layer, and each of the first wirings 41 is a first wiring layer. Formed in two layers. Cu is a material having a lower resistivity than Al. Therefore, the wiring resistance per unit wiring length can be kept lower than that of the first wiring 41 by forming the second wiring 42 with a material having a low resistivity.

  The method for forming the second wiring 42 by increasing the wiring width described in the “first embodiment”, and the second wiring using the plurality of wiring layers described in the “second embodiment”. Any one of a method for forming the second wiring 42, a method for forming the second wiring 42 by increasing the wiring thickness described in the “other embodiments”, and a method for forming the second wiring 42 with a material having a low resistivity. The second wiring 42 may be formed by combining the above methods.

DESCRIPTION OF SYMBOLS 10 Semiconductor element 12 Input pad 14A 1st output pad 14B 2nd output pad 16 Internal circuit 17 Input terminal 18 Output terminal 31 1st edge | side 32 2nd edge | side 33 3rd edge | side 34 4th edge | side 41 1st wiring 42 Second wiring

Claims (6)

  A semiconductor element characterized in that a resistance value per unit wiring length of a wiring formed in each wiring region is made different for each of a plurality of wiring regions formed along each side of the substrate. A plurality of first output pads formed along one side of the outer periphery of the substrate;
A plurality of second output pads formed along at least one of a side opposite to the one side and a side adjacent to the one side;
Output terminals connected to any one of the plurality of first output pads and the plurality of second output pads, and each of the output terminals is arranged along the one side. A plurality of internal circuits formed along the one side on the substrate,
The wiring area is
A first wiring region adjacent to the plurality of first output pads, wherein a wiring that connects any of the plurality of output terminals and any of the plurality of first output pads is formed;
A wiring region adjacent to the plurality of second output pads, wherein a second wiring region in which a wiring connecting each of the plurality of output terminals and any of the plurality of second output pads is formed; Including
2. A resistance value per unit wiring length of a wiring formed in the second wiring region is lower than a resistance value per unit wiring length of a wiring formed in the first wiring region. The semiconductor element as described in.   By differentiating the wiring width per unit wiring length, the resistance value per unit wiring length of the wiring formed in the second wiring area can be calculated per unit wiring length of the wiring formed in the first wiring area. The semiconductor element according to claim 2, wherein the resistance value is lower than the resistance value of the semiconductor element.   A plurality of wiring layers are stacked on the substrate, and the resistance value per unit wiring length of the wiring formed in the second wiring region is changed by changing the number of wiring layers. 3. The semiconductor element according to claim 2, wherein the resistance value is lower than a resistance value per unit wiring length of the wiring formed in the wiring region.   By differentiating the wiring thickness per unit wiring length, the resistance value per unit wiring length of the wiring formed in the second wiring region can be obtained per unit wiring length of the wiring formed in the first wiring region. The semiconductor element according to claim 2, wherein the resistance value is lower than the resistance value of the semiconductor element.   By using materials having different resistivities, the resistance value per unit wiring length of the wiring formed in the second wiring region is changed to the resistance value per unit wiring length of the wiring formed in the first wiring region. The semiconductor element according to claim 2, wherein the semiconductor element is lower.

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