JP2014016452A - Optical branching element and optical semiconductor integrated circuit device - Google Patents

Optical branching element and optical semiconductor integrated circuit device Download PDF

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JP2014016452A
JP2014016452A JP2012153452A JP2012153452A JP2014016452A JP 2014016452 A JP2014016452 A JP 2014016452A JP 2012153452 A JP2012153452 A JP 2012153452A JP 2012153452 A JP2012153452 A JP 2012153452A JP 2014016452 A JP2014016452 A JP 2014016452A
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Kazumasa Takabayashi
和雅 高林
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Fujitsu Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide an optical branching element and an optical semiconductor integrated circuit device having a multimode interference waveguide, in which distribution of distortion caused by an insulating film is suppressed to decrease deviation.SOLUTION: A layered structure of a semiconductor clad layer, a semiconductor waveguide core layer and a semiconductor clad layer is prepared, and at least the underside semiconductor clad layer is partially etched to form a mesa type multimode interference waveguide. An upper surface of the obtained waveguide is covered with a first insulating film while a side surface is covered with a second insulating film having a coefficient of thermal expansion in an opposite magnitude relation with the coefficients of thermal expansion of the semiconductor clad layer and of the semiconductor waveguide core layer, to the magnitude relation between the first insulating film and the above layers.

Description

本発明は、光分岐器及び光半導体集積回路装置に関するものであり、例えば、導波路側面が半導体材料で埋め込まれていないハイメサ導波路構造を持つ多モード干渉(Multi Mode Interference;MMI)導波路用いた光分岐器(光結合器)及びそれを用いた光半導体集積回路装置に関する。   The present invention relates to an optical branching device and an optical semiconductor integrated circuit device. For example, for a multi-mode interference (MMI) waveguide having a high-mesa waveguide structure in which a waveguide side surface is not embedded with a semiconductor material. The present invention relates to an optical branching device (optical coupler) and an optical semiconductor integrated circuit device using the same.

近年の光通信用デバイスの高機能化に伴い、複数の半導体レーザや半導体光変調器、フォトダイオード(PD)を単一の半導体基板にモノリシックに集積した光半導体集積回路装置が用いられるようになっている。これらの光半導体集積回路装置では、半導体レーザ・半導体光変調器からの信号光を結合したり、信号光を複数のPDに向けて分岐したりする光分岐器(光結合器)が必須となる。   With the recent enhancement of functionality of optical communication devices, optical semiconductor integrated circuit devices in which a plurality of semiconductor lasers, semiconductor optical modulators, and photodiodes (PDs) are monolithically integrated on a single semiconductor substrate have come to be used. ing. In these optical semiconductor integrated circuit devices, an optical branching device (optical coupler) that couples signal light from a semiconductor laser / semiconductor optical modulator or branches the signal light toward a plurality of PDs is essential. .

その中で、半導体で構成された多モード干渉(MMI)導波路を用いた光分岐器(光結合器)は、半導体レーザや半導体光変調器、PDとのモノリシック集積が容易であり、かつ、小型で挿入損失が小さいという利点がある。MMI導波路では、幅の広い導波路内部で横高次モードを複数発生させて、ある一定距離伝播させることにより、導波路出力端において入力端における光強度分布が再現される現象、即ち、自己結像が発生する。この自己結像を利用して光分岐器を形成することが可能になる(例えば、非特許文献1参照)。   Among them, an optical branching unit (optical coupler) using a multimode interference (MMI) waveguide made of a semiconductor is easy to monolithically integrate with a semiconductor laser, a semiconductor optical modulator, and a PD, and There is an advantage that it is small and insertion loss is small. In the MMI waveguide, a phenomenon in which the light intensity distribution at the input end is reproduced at the output end of the waveguide by generating a plurality of transverse higher-order modes inside the wide waveguide and propagating it for a certain distance, ie, self Imaging occurs. An optical branching device can be formed using this self-imaging (see, for example, Non-Patent Document 1).

図13は、従来のMMI光分岐器を含む光半導体集積回路装置の概念的平面図であり、入力導波路61、4×4MMI光分岐器62、出力導波路63及び4つのPD64が順次接続された構造になっている(非特許文献3)。この光半導体集積回路装置では、入射光を4つのPDに向けて4等分するための光分岐器として4×4MMIが用いられている例を示しているが、4×4MMIは入力側の4つの導波路に入射された光を出力側の1つの導波路に結合する光結合器として用いることができる。   FIG. 13 is a conceptual plan view of an optical semiconductor integrated circuit device including a conventional MMI optical branching device, in which an input waveguide 61, a 4 × 4 MMI optical branching device 62, an output waveguide 63, and four PDs 64 are sequentially connected. (Non-Patent Document 3). In this optical semiconductor integrated circuit device, an example is shown in which 4 × 4 MMI is used as an optical branching device for dividing incident light into four PDs into four equal parts, but 4 × 4 MMI is 4 on the input side. It can be used as an optical coupler that couples light incident on one waveguide to one waveguide on the output side.

図14は、4×4MMI光分岐器の概念的平面図であり、幅の広い導波路部からなるMMI導波路62と、4本の入力ポート62と4本の出力ポート62を備えている。 Figure 14 is a schematic plan view of a 4 × 4 MMI optical splitter comprises an MMI waveguide 62 2 consisting of a wide waveguide portion having a width, the four input ports 62 1 and four output ports 62 3 ing.

半導体でMMI光分岐器を形成する場合、損失低減や複数の出力ポート間で出力光強度のばらつき、即ち、偏差の抑制の観点から、導波路コア層の側面がむき出しになっているか、或いは、半導体以外の材料で覆われているハイメサ型の導波路が好ましい。   When the MMI optical branching device is formed of a semiconductor, the side surface of the waveguide core layer is exposed from the viewpoint of reducing loss and variation in output light intensity among a plurality of output ports, that is, suppressing the deviation, or A high-mesa waveguide covered with a material other than a semiconductor is preferable.

これは、横方向の光閉じ込めが強くなるため、より高い次数の横高次モードが発生し、自己結像がより理想的に起こるようになるためである。また、多モード干渉導波路の実効幅が狭くなるため、実効幅の二乗に比例する多モード干渉導波路の長さが短縮され小型化の観点でも有利である。   This is because the lateral optical confinement becomes stronger, so that a higher-order lateral higher-order mode is generated and self-imaging occurs more ideally. Further, since the effective width of the multimode interference waveguide is narrowed, the length of the multimode interference waveguide proportional to the square of the effective width is shortened, which is advantageous from the viewpoint of miniaturization.

ハイメサ型の半導体導波路では、一般的に導波路の保護のためにSiOやSiNなどの絶縁体膜でその導波路メサ構造の上面、側面および底面即ち、メサに接続する平坦面を覆う(例えば、特許文献1参照)。 In a high-mesa type semiconductor waveguide, generally, an insulating film such as SiO 2 or SiN covers the top, side and bottom surfaces of the waveguide mesa structure, that is, a flat surface connected to the mesa for protecting the waveguide ( For example, see Patent Document 1).

図15は、従来の4×4MMI光分岐器の説明図であり、図15(a)は平面図であり、図15(b)は図15(a)のA−A′を結ぶ一点鎖線に沿った断面図である。このハイメサ型の4×4MMI光分岐器70は、下部クラッド層71上にコア層72及び上部クラッド層73を順次堆積し、メサエッチングにより形成されたハイメサ構造のMMI導波路75と、ハイメサ構造の4本の入力ポート74とハイメサ構造の4本の出力ポート76からなる。また、各ハイメサ構造の上面、側面および底面(メサの両脇の表面)は絶縁体膜77で被覆されている。   FIG. 15 is an explanatory diagram of a conventional 4 × 4 MMI optical splitter, FIG. 15 (a) is a plan view, and FIG. 15 (b) is an alternate long and short dash line connecting AA ′ in FIG. 15 (a). FIG. The high mesa type 4 × 4 MMI optical splitter 70 sequentially deposits a core layer 72 and an upper clad layer 73 on a lower clad layer 71, and a high mesa structure MMI waveguide 75 formed by mesa etching, and a high mesa structure. It consists of four input ports 74 and four output ports 76 having a high mesa structure. Further, the top surface, side surface, and bottom surface (surfaces on both sides of the mesa) of each high mesa structure are covered with an insulator film 77.

特開2010−226062号公報JP 2010-226062 A

Soldano et.al.,J.LIGHTWAVE TECHNOLOGY,VOL.13,NO.4,APRIL1995 pp.615−627Soldano et. al. , J .; LIGHTWAVE TECHNOLOGY, VOL. 13, NO. 4, APRIL 1995 pp. 615-627 Optoelectronic and Microelectronic Materials and Devices,2004 Conference on,pp.97−100Optoelectronic and Microelectronic Materials and Devices, 2004 Conference on, pp. 97-100 H.G.Bach et.al., Waveguide−integrated Components Based 100Gb/s Photoreceivers:FromDirect to Coherent Detection, 2010 International Conference on Indium Phosphide and RelatedMaterials,Conference Proceedings,pp.445−448H. G. Bach et. al. , Waveguide-integrated Components Based 100 Gb / s Photoreceivers: From Direct to Coherent Detection, 2010 International Conference on Indium Phosphoretics. 445-448

しかし、保護膜として形成される絶縁体膜は一般に高温で形成され、かつ、半導体と熱膨張係数が異なるため、室温において歪が発生する。特に、ハイメサ構造では、導波路の上面と側面に絶縁体膜が形成されるため導波路内部で歪分布が発生しやすいという問題があるので、この事情を図16を参照して説明する。   However, since the insulator film formed as the protective film is generally formed at a high temperature and has a different thermal expansion coefficient from that of the semiconductor, distortion occurs at room temperature. In particular, in the high mesa structure, since an insulator film is formed on the upper surface and side surfaces of the waveguide, there is a problem that a strain distribution is likely to occur inside the waveguide. This situation will be described with reference to FIG.

図16は、従来のMMI導波路の横方向の歪分布の説明図であり、図15(b)において太い破線で示す位置、即ち、中心部から一方の端面に向かった各位置の歪を示している。保護膜として半導体よりも熱膨張係数が小さいSiN膜を用いた場合、SiN膜の成膜温度は一般的に200℃以上と室温より高いため、室温まで温度を下げた場合に、半導体の方がより収縮し、降温による収縮が小さいSiN膜に引っ張られることになる。   FIG. 16 is an explanatory diagram of the strain distribution in the lateral direction of the conventional MMI waveguide, and shows the strain indicated by the thick broken line in FIG. 15B, that is, the strain at each position from the center toward one end face. ing. When a SiN film having a thermal expansion coefficient smaller than that of a semiconductor is used as the protective film, the deposition temperature of the SiN film is generally 200 ° C. or higher, which is higher than room temperature. It shrinks more and is pulled by the SiN film that is less shrunk due to the temperature drop.

ハイメサ構造の多モード干渉導波路構造においては、導波路メサ上面には水平方向の引張歪が発生する。一方、側面には、上下方向の引張歪が発生し、導波路メサ上面の水平方向には逆に圧縮歪が発生する。その結果、多モード干渉導波路のコア層における水平方向の歪は、導波路中心付近(位置0μm)では引張方向(グラフで+方向)に、導波路端付近(位置11μm)では圧縮方向(グラフで−方向)に発生し、端と中央で歪の状態の差が大きくなる。   In a high-mesa multimode interference waveguide structure, a horizontal tensile strain is generated on the top surface of the waveguide mesa. On the other hand, a tensile strain in the vertical direction is generated on the side surface, and a compressive strain is generated in the horizontal direction on the top surface of the waveguide mesa. As a result, the horizontal strain in the core layer of the multimode interference waveguide is in the tensile direction (+ direction in the graph) near the waveguide center (position 0 μm), and in the compression direction (graph 11) near the waveguide end (position 11 μm). In the negative direction), and the difference in strain state between the end and the center increases.

このような歪分布は半導体導波路の屈折率分布となるため、MMI導波路の特性を劣化させ、偏差を増大させてしまう。このように、従来のハイメサ導波路では保護膜となる絶縁体膜によって発生する歪分布を十分抑えられないため、偏差を十分低減することができないという問題がある。   Since such a strain distribution becomes a refractive index distribution of the semiconductor waveguide, the characteristics of the MMI waveguide are deteriorated and the deviation is increased. As described above, in the conventional high mesa waveguide, the strain distribution generated by the insulating film serving as the protective film cannot be sufficiently suppressed, and thus there is a problem that the deviation cannot be sufficiently reduced.

したがって、ハイメサ構造の多モード干渉導波路において、絶縁体膜に起因する歪分布を抑制して偏差を低減することを目的とする。   Accordingly, an object of the present invention is to suppress the strain distribution caused by the insulator film and reduce the deviation in the high-mesa multimode interference waveguide.

開示する一観点からは、基板と、前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値であることを特徴とする光分岐器が提供される。   From one aspect disclosed, a substrate, a semiconductor waveguide core layer provided above the substrate, a semiconductor clad layer disposed above and below the semiconductor waveguide core layer and having a refractive index lower than that of the semiconductor waveguide core layer, A mesa-shaped multimode interference waveguide having a stacked structure of: a first insulator film provided on the upper surface of the multimode interference waveguide; and a second insulator provided on a side surface of the multimode interference waveguide A thermal expansion coefficient of the semiconductor waveguide core layer and the cladding layer is a value between the thermal expansion coefficient of the first insulator film and the thermal expansion coefficient of the second insulator film. An optical branching device is provided.

また、開示する別の観点からは、基板上に、前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値である光分岐器と、半導体レーザ、半導体光増幅器、半導体光変調器或いはフォトダイオードのうちの少なくとも一種類の光半導体素子とがモノリシックに集積されていることを特徴とする光半導体集積回路装置が提供される。   From another viewpoint to be disclosed, a semiconductor waveguide core layer provided above the substrate on the substrate, and disposed above and below the semiconductor waveguide core layer, the refractive index is lower than that of the semiconductor waveguide core layer. A mesa-shaped multimode interference waveguide having a laminated structure with a semiconductor cladding layer, a first insulator film provided on the top surface of the multimode interference waveguide, and a first insulator film provided on a side surface of the multimode interference waveguide Two insulating films, and the thermal expansion coefficient of the semiconductor waveguide core layer and the cladding layer is between the thermal expansion coefficient of the first insulating film and the thermal expansion coefficient of the second insulating film. An optical semiconductor integrated circuit device comprising: an optical branching device that is a value; and at least one optical semiconductor element of a semiconductor laser, a semiconductor optical amplifier, a semiconductor optical modulator, or a photodiode are monolithically integrated Is provided.

開示の光分岐器及び光半導体集積回路装置によれば、絶縁体膜に起因する歪分布を抑制して偏差を低減することが可能になる。   According to the disclosed optical branching device and the optical semiconductor integrated circuit device, it is possible to reduce the deviation by suppressing the strain distribution caused by the insulator film.

本発明の実施の形態の光分岐器の説明図である。It is explanatory drawing of the optical branching device of embodiment of this invention. SiN膜の熱膨張係数の成膜温度依存性の説明図である。It is explanatory drawing of the film-forming temperature dependence of the thermal expansion coefficient of a SiN film | membrane. 本発明の実施例1の4×4MMI光分岐器の説明図である。It is explanatory drawing of the 4x4 MMI optical splitter of Example 1 of this invention. 本発明の実施例1の4×4MMI光分岐器の歪分布の説明図である。It is explanatory drawing of the distortion distribution of the 4x4 MMI optical splitter of Example 1 of this invention. 本発明の実施例1の4×4MMI光分岐器の製造工程の途中までの説明図である。It is explanatory drawing to the middle of the manufacturing process of the 4x4 MMI optical splitter of Example 1 of this invention. 本発明の実施例1の4×4MMI光分岐器の製造工程の図5以降の途中までの説明図である。It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of the 4 * 4 MMI optical splitter of Example 1 of this invention. 本発明の実施例1の4×4MMI光分岐器の製造工程の図6以降の説明図である。It is explanatory drawing after FIG. 6 of the manufacturing process of the 4 * 4 MMI optical splitter of Example 1 of this invention. 本発明の実施例2の4×4MMI光分岐器の説明図である。It is explanatory drawing of the 4x4 MMI optical splitter of Example 2 of this invention. 本発明の実施例2の4×4MMI光分岐器の製造工程の途中までの説明図である。It is explanatory drawing to the middle of the manufacturing process of the 4x4 MMI optical splitter of Example 2 of this invention. 本発明の実施例2の4×4MMI光分岐器の製造工程の図9以降の説明図である。It is explanatory drawing after FIG. 9 of the manufacturing process of the 4 * 4 MMI optical splitter of Example 2 of this invention. 本発明の実施例3の4×4MMI光分岐器の説明図である。It is explanatory drawing of the 4x4 MMI optical splitter of Example 3 of this invention. 本発明の実施例4の光半導体集積回路装置の平面図である。It is a top view of the optical semiconductor integrated circuit device of Example 4 of this invention. 従来のMMI光分岐器を含む光半導体集積回路装置の概念的平面図である。It is a conceptual top view of the optical semiconductor integrated circuit device containing the conventional MMI optical branching device. 4×4MMI光分岐器の概念的平面図である。It is a notional top view of a 4x4 MMI optical splitter. 従来の4×4MMI光分岐器の説明図である。It is explanatory drawing of the conventional 4x4 MMI optical splitter. 従来のMMI導波路の横方向の歪分布の説明図である。It is explanatory drawing of the distortion distribution of the horizontal direction of the conventional MMI waveguide.

ここで、図1及び図2を参照して、本発明の実施の形態の光分岐器を説明する。図1は本発明の実施の形態の光分岐器の説明図であり、図1(a)は平面図であり、図1(b)は図1(a)におけるA−A′を結ぶ一点鎖線に沿った断面図である。   Here, with reference to FIG.1 and FIG.2, the optical branching device of embodiment of this invention is demonstrated. FIG. 1 is an explanatory diagram of an optical branching device according to an embodiment of the present invention, FIG. 1 (a) is a plan view, and FIG. 1 (b) is an alternate long and short dash line connecting AA 'in FIG. 1 (a). FIG.

本発明の実施の形態の光分岐器は、半導体導波路コア層11と、半導体導波路コア層11の上下に配置され半導体導波路コア層11より屈折率が低い半導体クラッド層12,13との積層構造を少なくとも下側の半導体クラッド層12の一部までエッチングすることによって形成されたメサ構造からなるMMI導波路14と、入力導波路17及び出力導波路18を有している。MMI導波路14の伝搬光の導波方向に垂直な幅は、伝搬光の横2次モードのカットオフ幅より広くしている。   An optical branching device according to an embodiment of the present invention includes a semiconductor waveguide core layer 11 and semiconductor clad layers 12 and 13 disposed above and below the semiconductor waveguide core layer 11 and having a refractive index lower than that of the semiconductor waveguide core layer 11. An MMI waveguide 14 having a mesa structure formed by etching the laminated structure to at least a part of the lower semiconductor clad layer 12, an input waveguide 17, and an output waveguide 18 are provided. The width perpendicular to the waveguide direction of the propagation light of the MMI waveguide 14 is made wider than the cut-off width of the transverse secondary mode of the propagation light.

MMI導波路14の上面は第1の絶縁体膜15で覆っており、また、MMI導波路14の側面は第2の絶縁体膜16で覆っている。第1の絶縁体膜15と第2の絶縁体膜16は、半導体導波路コア層11及び半導体クラッド層12,13の熱膨張係数が、第1の絶縁体膜15の熱膨張係数と第2の絶縁体膜16の熱膨張係数の間の値になる材料を選択する。なお、底面(メサの両脇の平面)も第2の絶縁体膜16で覆うようにしても良い。   The upper surface of the MMI waveguide 14 is covered with a first insulator film 15, and the side surface of the MMI waveguide 14 is covered with a second insulator film 16. The first insulator film 15 and the second insulator film 16 are such that the thermal expansion coefficient of the semiconductor waveguide core layer 11 and the semiconductor cladding layers 12 and 13 is the same as that of the first insulator film 15 and the second coefficient of thermal expansion. A material having a value between the thermal expansion coefficients of the insulating film 16 is selected. Note that the bottom surface (planes on both sides of the mesa) may also be covered with the second insulator film 16.

なお、第1の絶縁体膜15が第2の絶縁体膜16を覆うように、メサ構造の側面及び底面に延在させても良いし、或いは、第2の絶縁体膜16が第1の絶縁体膜15を覆うようにメサの上面に延在させても良い。   The first insulator film 15 may extend to the side surface and the bottom surface of the mesa structure so as to cover the second insulator film 16, or the second insulator film 16 may be the first insulator film 16. You may extend on the upper surface of a mesa so that the insulator film 15 may be covered.

第1の絶縁体膜15としてはSiOが典型的なものであり、また、第2の絶縁体膜16としてはSiNが典型的なものである。例えば、減圧化学気相成長法(LP−CVD法)を用いて、340℃の成膜温度で形成したSiO膜の熱膨張係数は7.97×10−6−1となる。一方、プラズマCVD法を用いて280℃の成膜温度で形成したSiN膜の熱膨張係数は4×10−6−1となる。InPの熱膨張係数は4.5×10−6−1であるので、SiO>InP>SiNの関係が得られる。 The first insulator film 15 is typically SiO 2 , and the second insulator film 16 is typically SiN. For example, the thermal expansion coefficient of a SiO 2 film formed at a film forming temperature of 340 ° C. using a low pressure chemical vapor deposition method (LP-CVD method) is 7.97 × 10 −6 K −1 . On the other hand, the thermal expansion coefficient of the SiN film formed at 280 ° C. using the plasma CVD method is 4 × 10 −6 K −1 . Since the thermal expansion coefficient of InP is 4.5 × 10 −6 K −1 , the relationship SiO 2 >InP> SiN is obtained.

なお、InPより熱膨張係数が小さい絶縁体膜としては、石英(SiO)が挙げられ、InPより熱膨張係数が大きい絶縁体膜としては、LiF、MgF、CaF、BaF、水晶(SiO)、Alが挙げられる。なお、SiNは成膜条件により熱膨張係数が変化し、InPの熱膨張係数より大きくも小さくもなる。 Insulating films having a smaller thermal expansion coefficient than InP include quartz (SiO 2 ), and insulating films having a larger thermal expansion coefficient than InP include LiF, MgF, CaF 2 , BaF 2 , quartz (SiO 2) . 2) include Al 2 O 3. Note that the thermal expansion coefficient of SiN varies depending on the film forming conditions, and is larger or smaller than the thermal expansion coefficient of InP.

図2は、SiN膜の熱膨張係数の成膜温度依存性の説明図であり(非特許文献2参照)、成膜温度が高いほど、熱膨張係数が小さくなり、例えば、250℃では5×10−6−1程度となり、InPの熱膨張係数より大きくなる。 FIG. 2 is an explanatory diagram of the film formation temperature dependence of the thermal expansion coefficient of the SiN film (see Non-Patent Document 2). The higher the film formation temperature, the smaller the thermal expansion coefficient, for example, 5 × at 250 ° C. It becomes about 10 −6 K −1 and becomes larger than the thermal expansion coefficient of InP.

このように、本発明の実施の形態においては、MMI導波路14のメサの上面と側面とで導波路コア層11に対する熱膨張係数大小関係が反対の2種類の絶縁体膜が形成されているので、導波路コア層11の印加される歪の分布を低減することができる。   As described above, in the embodiment of the present invention, two types of insulator films having opposite thermal expansion coefficient magnitude relationships with respect to the waveguide core layer 11 are formed between the top surface and the side surface of the mesa of the MMI waveguide 14. Therefore, the distribution of strain applied to the waveguide core layer 11 can be reduced.

たとえば、メサの上面では水平方向に圧縮歪が入り、側面には上下方向に引張歪が入るようにすることができる。側面の絶縁体膜による水平方向の歪は圧縮歪となり、導波路全体の水平方向に圧縮歪が入るようになるため歪の分布は抑制される。その結果、導波路内部の屈折率分布を低減し、多モード干渉導波路の偏差を低減することが可能となる。   For example, the upper surface of the mesa may have a compressive strain in the horizontal direction, and the side surface may have a tensile strain in the vertical direction. The strain in the horizontal direction due to the insulating film on the side surface becomes a compressive strain, and the compressive strain enters in the horizontal direction of the entire waveguide, so that the strain distribution is suppressed. As a result, the refractive index distribution inside the waveguide can be reduced, and the deviation of the multimode interference waveguide can be reduced.

また、第1の絶縁体膜15が第2の絶縁体膜16を覆うように、メサ構造の側面及び底面に延在させた場合も、或いは、第2の絶縁体膜16が第1の絶縁体膜15を覆うようにメサの上面に延在させても延在させる側の絶縁体膜を相対的に薄くすれば良い。   Further, when the first insulator film 15 extends to the side surface and the bottom surface of the mesa structure so as to cover the second insulator film 16, or the second insulator film 16 is used as the first insulation film. Even if it extends to the upper surface of the mesa so as to cover the body film 15, the insulating film on the extending side may be made relatively thin.

なお、熱膨張率の関係は逆でも良く、その場合にはメサの上面では水平方向に引張歪が入り、側面には上下方向に圧縮歪が入ることになる。また、多モード干渉導波路を構成する半導体材料はInGaAsP/InP系に限られるものではなく、AlGaInAs/InP系、InGaAs/GaAs系やAlGaAs/GaAs系の他の半導体材料にも適用されるものである。その場合には、使用する半導体材料の熱膨張係数に応じて第1の絶縁体膜及び第2の絶縁体膜の材料及び成膜温度を選択すれば良い。   Note that the relationship between the thermal expansion coefficients may be reversed. In this case, the upper surface of the mesa has a tensile strain in the horizontal direction, and the side surface has a compressive strain in the vertical direction. The semiconductor material constituting the multimode interference waveguide is not limited to the InGaAsP / InP system, but can be applied to other semiconductor materials such as AlGaInAs / InP system, InGaAs / GaAs system, and AlGaAs / GaAs system. is there. In that case, the material and film formation temperature of the first insulator film and the second insulator film may be selected in accordance with the thermal expansion coefficient of the semiconductor material to be used.

次に、図3乃至図7を参照して、本発明の実施例1の4×4MMI光分岐器を説明する。図3は、本発明の実施例1の4×4MMI光分岐器の説明図であり、図3(a)は平面図であり、図3(b)は図3(b)におけるA−A′を結ぶ一点鎖線に沿った断面図である。   Next, a 4 × 4 MMI optical splitter according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 7. FIG. 3 is an explanatory diagram of the 4 × 4 MMI optical splitter according to the first embodiment of the present invention, FIG. 3A is a plan view, and FIG. 3B is AA ′ in FIG. It is sectional drawing along the dashed-dotted line which connects.

i型InGaAsPコア層23は、厚さが0.5μmで組成波長が1.05μmのInGaAsPからなり、下部クラッドとなるi型InPバッファ層22と、上部クラッドとなる厚さが1.0μmのi型InPクラッド層24に挟まれて導波路を構成している。4×4MMI光分岐器のMMI導波路は、i型InPクラッド層24、i型InGaAsPコア層23及びi型InPバッファ層22の一部を除去することによってハイメサ型の導波路構造を形成している。   The i-type InGaAsP core layer 23 is made of InGaAsP having a thickness of 0.5 μm and a composition wavelength of 1.05 μm. The i-type InP buffer layer 22 serving as a lower clad and the i-type InP buffer layer 22 serving as an upper clad are 1.0 μm thick. A waveguide is configured by being sandwiched between the type InP cladding layers 24. The MMI waveguide of the 4 × 4 MMI optical splitter forms a high-mesa waveguide structure by removing a part of the i-type InP cladding layer 24, the i-type InGaAsP core layer 23, and the i-type InP buffer layer 22. Yes.

メサ構造のMMI導波路の幅は22μmで、長さが450μmであり、メサ構造の上面には、厚さが300nmのSiO2膜29が形成され、また、側面には厚さが300nmのSiN膜31が形成される。MMI導波路の幅は、少なくとも3つ以上の横モードが発生するように、横2次モードのカットオフ幅よりも広い値とする。MMI導波路の長さは所望の自己結像が起こるように調整された値である。   The mesa structure MMI waveguide has a width of 22 μm and a length of 450 μm. A 300 nm thick SiO 2 film 29 is formed on the top surface of the mesa structure, and a 300 nm thick SiN film is formed on the side surface. 31 is formed. The width of the MMI waveguide is set to a value wider than the cutoff width of the transverse secondary mode so that at least three transverse modes are generated. The length of the MMI waveguide is a value adjusted so that the desired self-imaging occurs.

SiOおよびSiNなどの絶縁体膜の熱膨張係数は、膜形成条件によって異なるが、ここでは、SiO、InP(InGaAsP)、SiNの熱膨張係数の関係が、SiO>InP(InGaAsP)>SiNとなるようにする。このような熱膨張係数の関係では、成膜時から室温に降温した場合に、SiOが形成された部分では半導体側に膜と平行方向に圧縮歪が入り、SiN膜が形成されている部分には半導体側に膜と平行方向に引張歪が入る。 The thermal expansion coefficient of an insulator film such as SiO 2 and SiN varies depending on the film formation conditions. Here, the relationship between the thermal expansion coefficients of SiO 2 , InP (InGaAsP), and SiN is SiO 2 > InP (InGaAsP)> SiN is used. In such a relationship of the thermal expansion coefficient, when the temperature is lowered to room temperature from the time of film formation, the portion where SiO 2 is formed has compressive strain in the direction parallel to the film on the semiconductor side, and the portion where the SiN film is formed Has tensile strain in the direction parallel to the film on the semiconductor side.

このように、MMI導波路に熱膨張係数が異なるSiOとSiNの2種類の絶縁体膜を形成している。したがって、MMI導波路の上面からSiO膜29によって導波路に与えられる水平方向の歪と、導波路側面からSiN膜31によって導波路に与えられる水平方向の歪を、両者ともに圧縮歪の方向にすることが可能となる。 Thus, two types of insulator films of SiO 2 and SiN having different thermal expansion coefficients are formed in the MMI waveguide. Therefore, the horizontal strain applied to the waveguide by the SiO 2 film 29 from the upper surface of the MMI waveguide and the horizontal strain applied to the waveguide by the SiN film 31 from the side of the waveguide are both in the direction of compressive strain. It becomes possible to do.

その結果、従来の導波路全面をSiN膜等の絶縁体膜で均一に覆った場合と比較して、導波路内部の歪の分布を抑制することが可能となる。図4には、従来構造と実施例1の構造においてi型InGaAsPコア層23の中心部における水平方向の歪を計算した結果を示す。計算では、InP、SiN、SiOの熱膨張係数を、それぞれ、4.5×10−6、2.5×10−6及び11.6×10−6を仮定した。なお、図4には後述する実施例2の歪分布も併せて示している。 As a result, the strain distribution inside the waveguide can be suppressed as compared with the conventional case where the entire surface of the waveguide is uniformly covered with an insulator film such as a SiN film. FIG. 4 shows the result of calculating the horizontal strain at the center of the i-type InGaAsP core layer 23 in the conventional structure and the structure of the first embodiment. In the calculation, the thermal expansion coefficients of InP, SiN, and SiO 2 were assumed to be 4.5 × 10 −6 , 2.5 × 10 −6, and 11.6 × 10 −6 , respectively. FIG. 4 also shows the strain distribution of Example 2 described later.

図4に示すように、従来構造では導波路中心付近で引張歪(+の歪)が、導波路側面付近で圧縮歪(−の歪)がかかっており、分布が大きくなっている。一方、本発明の実施例1の構造では、導波路中央部および側面付近ともに圧縮歪がかかり、歪分布が低減されていることが分かる。これにより、導波路内部の屈折率分布を低減して、4×4MMI導波路の特性を改善し、偏差を低減することが可能となる。   As shown in FIG. 4, in the conventional structure, tensile strain (+ strain) is applied near the center of the waveguide, and compressive strain (-strain) is applied near the side surface of the waveguide, and the distribution is large. On the other hand, in the structure of Example 1 of the present invention, it can be seen that compressive strain is applied to both the central portion of the waveguide and the vicinity of the side surface, and the strain distribution is reduced. Thereby, the refractive index distribution inside the waveguide can be reduced, the characteristics of the 4 × 4 MMI waveguide can be improved, and the deviation can be reduced.

次に、図5乃至図7を参照して、本発明の実施例1の4×4MMI光分岐器の製造方法を説明する。なお、各図における左図は平面図であり、右図は左図におけるA−A′を結ぶ一点鎖線に沿った断面図である。まず、図5(a)に示すように、半絶縁性InP基板21上に、下部クラッドとなる厚さが1.0μmのi型InPバッファ層22、厚さが0.5μmのi型InGaAsPコア層23及び厚さが1.0μmのi型InPクラッド層24を順次堆積する。   Next, a manufacturing method of the 4 × 4 MMI optical splitter according to the first embodiment of the present invention will be described with reference to FIGS. In each figure, the left figure is a plan view, and the right figure is a cross-sectional view taken along the alternate long and short dash line connecting AA 'in the left figure. First, as shown in FIG. 5A, an i-type InP buffer layer 22 having a thickness of 1.0 μm and a i-type InGaAsP core having a thickness of 0.5 μm are formed on a semi-insulating InP substrate 21. A layer 23 and an i-type InP cladding layer 24 having a thickness of 1.0 μm are sequentially deposited.

次いで、図5(b)に示すように、全面にSiO膜を形成したのち、通常のフォトリソグラフィー工程及びエッチング工程によりMMI導波路及びその出入力導波路を形成する部分に、SiOマスク25を形成する。次いで、このSiOマスクをマスクとしてドライエッチングを施すことによってハイメサ構造のMMI導波路26、入力導波路27及び出力導波路28を形成する。なお、ここでは、MMI導波路のサイズは22μm×450μmとし、入力導波路27及び出力導波路28のストライプ幅は2.5μmとする。 Next, as shown in FIG. 5B, after an SiO 2 film is formed on the entire surface, an SiO 2 mask 25 is formed on a portion where the MMI waveguide and its input / output waveguide are formed by a normal photolithography process and etching process. Form. Next, dry etching is performed using the SiO 2 mask as a mask to form the high-mesa MMI waveguide 26, the input waveguide 27, and the output waveguide 28. Here, the size of the MMI waveguide is 22 μm × 450 μm, and the stripe width of the input waveguide 27 and the output waveguide 28 is 2.5 μm.

次いで、図6(c)に示すように、SiO2マスクを除去したのち、減圧化学気相成長法(LP−CVD法)を用いて全面に厚さが300nmのSiO2膜29を形成する。次いで、図6(d)に示すように、レジストパターン30をマスクとして、バッファードフッ酸を用いてSiO2膜29の露出部を除去する。この時、レジストパターニングなどの精度を考慮してSiO2膜29の端部とMMI導波路26の端部との距離は1.0μmとする。MMI導波路26の上面は、第1の絶縁膜であるSiO2膜でその大部分(例えば9割以上)が覆われていれば良く、このようにMMI導波路26の上面の端の一部分が覆われていなくても構わない。   Next, as shown in FIG. 6C, after removing the SiO 2 mask, a 300 nm thick SiO 2 film 29 is formed on the entire surface by using a low pressure chemical vapor deposition method (LP-CVD method). Next, as shown in FIG. 6D, the exposed portion of the SiO 2 film 29 is removed using buffered hydrofluoric acid using the resist pattern 30 as a mask. At this time, the distance between the end portion of the SiO 2 film 29 and the end portion of the MMI waveguide 26 is set to 1.0 μm in consideration of accuracy such as resist patterning. The upper surface of the MMI waveguide 26 only needs to be covered with the SiO2 film as the first insulating film (for example, 90% or more), and a part of the end of the upper surface of the MMI waveguide 26 is thus covered. You don't have to be.

次いで、図7(e)に示すように、プラズマCVD法を用いて、全面に厚さが300nのSiN膜31を形成する。次いで、図7(f)に示すように、ドライエッチングによるエッチバックを行うことによって、SiO膜29の上面のSiN膜31を除去することによって、本発明の実施例1の4×4MMI光分岐器の基本構造が完成する。なお、底面にSiN膜31が残っていても良い。また、エッチバックにより導波路側面に形成されているSiN膜31の上部の一部がエッチングされても良く、導波路コア層の側面及びその付近が第2の絶縁膜であるSiN膜31で覆われていれば良い。 Next, as shown in FIG. 7E, an SiN film 31 having a thickness of 300 n is formed on the entire surface by plasma CVD. Next, as shown in FIG. 7F, the 4 × 4 MMI optical branching of the first embodiment of the present invention is performed by removing the SiN film 31 on the upper surface of the SiO 2 film 29 by performing etch back by dry etching. The basic structure of the vessel is completed. Note that the SiN film 31 may remain on the bottom surface. Further, a part of the upper portion of the SiN film 31 formed on the side surface of the waveguide may be etched by etch back, and the side surface of the waveguide core layer and the vicinity thereof are covered with the SiN film 31 which is the second insulating film. It should be.

なお、上記の実施例1においては、メサエッチングのマスクとなるSiOマスクを除去したのち、新たなSiO膜を設けて保護膜としているが、SiOマスクを所定パターンに再度エッチングしてそのまま保護膜として用いても良い。その場合には、その上から全面にSiN膜を成膜することで同様の構造が得られる。また、メサ底面に堆積したSiO膜29及びSiN膜31は必須ではなく、必要に応じて除去しても良い。 In Example 1 described above, after removing the SiO 2 mask serving as a mesa etching mask, a new SiO 2 film is provided as a protective film. However, the SiO 2 mask is etched again into a predetermined pattern and remains as it is. It may be used as a protective film. In that case, a similar structure can be obtained by forming a SiN film over the entire surface. Further, the SiO 2 film 29 and the SiN film 31 deposited on the mesa bottom surface are not essential, and may be removed as necessary.

次に、図8乃至図10を参照して、本発明の実施例2の4×4MMI光分岐器を説明する。図8は、本発明の実施例2の4×4MMI光分岐器の説明図であり、図8(a)は平面図であり、図8(b)は図8(b)におけるA−A′を結ぶ一点鎖線に沿った断面図である。   Next, a 4 × 4 MMI optical splitter according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 8 is an explanatory diagram of a 4 × 4 MMI optical splitter according to a second embodiment of the present invention, FIG. 8A is a plan view, and FIG. 8B is AA ′ in FIG. It is sectional drawing along the dashed-dotted line which connects.

i型InGaAsPコア層23は、厚さが0.5μmで組成波長が1.05μmのInGaAsPからなり、下部クラッドとなるi型InPバッファ層22と、上部クラッドとなる厚さが1.0μmのi型InPクラッド層24に挟まれて導波路を構成している。4×4MMI導波路の光結合器部は、i型InPクラッド層24、i型InGaAsPコア層及びi型InPバッファ層の一部を除去することによってハイメサ型の導波路構造を形成している。   The i-type InGaAsP core layer 23 is made of InGaAsP having a thickness of 0.5 μm and a composition wavelength of 1.05 μm. The i-type InP buffer layer 22 serving as a lower clad and the i-type InP buffer layer 22 serving as an upper clad are 1.0 μm thick. A waveguide is configured by being sandwiched between the type InP cladding layers 24. The optical coupler portion of the 4 × 4 MMI waveguide forms a high-mesa waveguide structure by removing a part of the i-type InP cladding layer 24, the i-type InGaAsP core layer, and the i-type InP buffer layer.

メサ構造のMMI導波路の幅は22μmで、長さが450μmであり、メサ構造の側面及び底面には、厚さが300nmのSiN膜32が形成され、また、上面にはSiN膜32を覆うように厚さが150nmのSiO膜34が形成される。ここでも、SiO、InP(InGaAsP)、SiNの熱膨張係数の関係が、SiO>InP>SiNとなるようにする。 The mesa structure MMI waveguide has a width of 22 μm and a length of 450 μm. A 300 nm thick SiN film 32 is formed on the side surface and bottom surface of the mesa structure, and the SiN film 32 is covered on the top surface. Thus, the SiO 2 film 34 having a thickness of 150 nm is formed. Again, the relationship between the thermal expansion coefficients of SiO 2 , InP (InGaAsP), and SiN is set to satisfy SiO 2 >InP> SiN.

この実施例2の構造では、MMI導波路のメサ上面にはSiOが形成されているため、絶縁体膜によるメサ上面からの水平方向の歪の方向は圧縮歪となる。一方で、側面には相対的に厚いSiN膜の外側に相対的に薄いSiO膜が形成されているため、歪のかかる方向としてはSiN膜の熱膨張係数に支配され、上下方向に引張歪になり、水平方向からみた場合にはMMI導波路に対して圧縮歪となる。 In the structure of Example 2, since SiO 2 is formed on the mesa upper surface of the MMI waveguide, the horizontal strain direction from the mesa upper surface by the insulator film is a compressive strain. On the other hand, since the relatively thin SiO 2 film on the outside of the relatively thick SiN film is formed on a side surface, the direction according distortion is dominated by the thermal expansion coefficient of the SiN film, tensile strain in the vertical direction Therefore, when viewed from the horizontal direction, the strain is compressive with respect to the MMI waveguide.

その結果、導波路全体に水平方向に圧縮歪がかかるようになるため、導波路内部での歪分布を低減することが可能となり、導波路内部の屈折率分布を抑えて、MMI導波路の特性を改善し偏差を抑制することが可能となる。   As a result, since the compressive strain is applied to the entire waveguide in the horizontal direction, the strain distribution inside the waveguide can be reduced, and the refractive index distribution inside the waveguide is suppressed, and the characteristics of the MMI waveguide are reduced. Can be improved and the deviation can be suppressed.

先に示した図4に実施例2の構造において導波路コア層中央部における水平方向の歪を計算した結果を示しているが、実施例1の構造と同様に導波路中央部および側面付近ともに圧縮歪がかかり、歪分布が低減されていることが分かる。これにより、導波路内部の屈折率分布を低減して、MMI導波路の特性を改善し、偏差を低減することが確認される。   FIG. 4 shows the result of calculating the horizontal distortion in the central portion of the waveguide core layer in the structure of the second embodiment. As in the structure of the first embodiment, both the central portion of the waveguide and the vicinity of the side surface are shown. It can be seen that compression strain is applied and the strain distribution is reduced. This confirms that the refractive index distribution inside the waveguide is reduced, the characteristics of the MMI waveguide are improved, and the deviation is reduced.

次に、図9及び図10を参照して、本発明の実施例2の4×4のMMI光分岐器の製造工程を説明する。まず、図9(a)に示すように、上記の実施例1と全く同様にハイメサ構造のMMI導波路を形成する。次いで、図9(b)に示すように、プラズマCVD法を用いて全面に厚さが300nmのSiN膜32を形成する。   Next, with reference to FIG.9 and FIG.10, the manufacturing process of the 4 * 4 MMI optical splitter of Example 2 of this invention is demonstrated. First, as shown in FIG. 9A, a high-mesa MMI waveguide is formed in the same manner as in the first embodiment. Next, as shown in FIG. 9B, a SiN film 32 having a thickness of 300 nm is formed on the entire surface by plasma CVD.

次いで、図10(c)に示すように、レジストパターン33をマスクとしてバッファードフッ酸によるエッチングによりSiN膜32の露出部を除去する。この際、レジストパターニングの精度を考慮し、MMI導波路の上面の端1μm程度にはSiN膜32を残すようにする。次いで、図10(d)に示すように、レジストパターン33を除去したのち、全面に厚さが150nmのSiO膜34を形成することで、本発明の実施例2の4×4のMMI光分岐器の基本構造が完成する。 Next, as shown in FIG. 10C, the exposed portion of the SiN film 32 is removed by etching with buffered hydrofluoric acid using the resist pattern 33 as a mask. At this time, in consideration of the accuracy of resist patterning, the SiN film 32 is left at about 1 μm at the end of the upper surface of the MMI waveguide. Next, as shown in FIG. 10 (d), after removing the resist pattern 33, a SiO 2 film 34 having a thickness of 150 nm is formed on the entire surface, so that the 4 × 4 MMI light of Example 2 of the present invention is obtained. The basic structure of the turnout is completed.

本発明の実施例2においてはメサ側面部を覆うSiN膜とSiO膜の膜厚の差を利用して歪分布を低減しているので、絶縁体膜のエッチング工程が1回で良く、エッチバック工程が不要となるので、製造工程が簡素化される。また、全面にSiO膜34が形成され、その後にエッチングを実施しないため、導波路全体が絶縁膜に保護されるようになるため、素子の信頼性の観点からも好ましい。 In Example 2 of the present invention, the strain distribution is reduced by utilizing the difference in film thickness between the SiN film covering the side surface of the mesa and the SiO 2 film. Since the back process is not necessary, the manufacturing process is simplified. In addition, since the SiO 2 film 34 is formed on the entire surface and etching is not performed thereafter, the entire waveguide is protected by the insulating film, which is preferable from the viewpoint of device reliability.

次に、図11を参照して本発明の実施例3の4×4MMI光分岐器を説明するが、基本的な製造工程は上記の実施例1の全く同様であり、最後のエッチバック工程を行わないだけであるので製造工程の説明は省略する。図11は、本発明の実施例3の4×4MMI光分岐器の説明図であり、図11(a)は平面図であり、図11(b)は図11(b)におけるA−A′を結ぶ一点鎖線に沿った断面図である。   Next, the 4 × 4 MMI optical branching device according to the third embodiment of the present invention will be described with reference to FIG. 11. The basic manufacturing process is exactly the same as that of the first embodiment, and the last etch back process is performed. Since it is only not performed, description of a manufacturing process is abbreviate | omitted. FIG. 11 is an explanatory diagram of a 4 × 4 MMI optical splitter according to a third embodiment of the present invention, FIG. 11A is a plan view, and FIG. 11B is an AA ′ in FIG. It is sectional drawing along the dashed-dotted line which connects.

i型InGaAsPコア層23は、厚さが0.5μmで組成波長が1.05μmのInGaAsPからなり、下部クラッドとなるi型InPバッファ層22と、上部クラッドとなる厚さが1.0μmのi型InPクラッド層24に挟まれて導波路を構成している。4×4MMI光分岐器のMMI導波路は、i型InPクラッド層24、i型InGaAsPコア層及びi型InPバッファ層の一部を除去することによってハイメサ型の導波路構造を形成している。   The i-type InGaAsP core layer 23 is made of InGaAsP having a thickness of 0.5 μm and a composition wavelength of 1.05 μm. The i-type InP buffer layer 22 serving as a lower clad and the i-type InP buffer layer 22 serving as an upper clad are 1.0 μm thick. A waveguide is configured by being sandwiched between the type InP cladding layers 24. The MMI waveguide of the 4 × 4 MMI optical splitter forms a high-mesa waveguide structure by removing a part of the i-type InP cladding layer 24, the i-type InGaAsP core layer, and the i-type InP buffer layer.

メサ構造のMMI導波路の幅は22μmで、長さが450μmであり、メサ構造の上面には、厚さが300nmのSiO2膜29が形成され、また、側面および底面には厚さが150nmSiN膜31がSiO膜を覆うように形成される。ここでも、SiO、InP(InGaAsP)、SiNの熱膨張係数の関係が、SiO>InP(InGaAsP)>SiNとなるようにする。 The mesa structure MMI waveguide has a width of 22 μm and a length of 450 μm. A 300 nm thick SiO 2 film 29 is formed on the top surface of the mesa structure, and a 150 nm SiN film on the side and bottom surfaces. 31 is formed so as to cover the SiO 2 film. Again, the relationship between the thermal expansion coefficients of SiO 2 , InP (InGaAsP), and SiN is set to satisfy SiO 2 > InP (InGaAsP)> SiN.

この実施例3ではMMI導波路のメサ上面に2層の絶縁体膜が、側面及び底面に1層の絶縁体膜が形成されており、メサ上面にはSiO膜とその上に形成されたSiN膜が存在する。相対的にSiO膜の方が厚いため、SiO膜の熱膨張係数が支配的になり、メサ上面の絶縁体膜による水平方向の歪は圧縮歪となる。一方、メサ側面にはSiN膜が形成されているため、側面の絶縁体膜による上下方向の歪は引張歪となり、水平方向には圧縮歪となる。 In Example 3, two layers of insulator films are formed on the top surface of the mesa of the MMI waveguide, and one layer of insulator film is formed on the side and bottom surfaces. The SiO 2 film is formed on the top surface of the mesa. A SiN film exists. Since the SiO 2 film is relatively thick, the thermal expansion coefficient of the SiO 2 film becomes dominant, and the horizontal strain due to the insulator film on the upper surface of the mesa becomes a compressive strain. On the other hand, since the SiN film is formed on the side surface of the mesa, the strain in the vertical direction due to the insulator film on the side surface becomes tensile strain, and becomes compressive strain in the horizontal direction.

上述の実施例1或いは実施例2の場合と同様に、全体的に水平方向に圧縮歪がかかった歪分布となるため、歪分布は抑制される。その結果、導波路内部の屈折率分布が抑制されてMMI導波路の特性を改善することが可能となる。   As in the case of the first embodiment or the second embodiment described above, the strain distribution is suppressed because the overall strain distribution is a compressive strain in the horizontal direction. As a result, the refractive index distribution inside the waveguide is suppressed, and the characteristics of the MMI waveguide can be improved.

この本発明の実施例3においては、メサ上面を覆うSiO膜とSiN膜の膜厚の差を利用して歪分布を低減しているので、絶縁体膜のエッチング工程が1回良く、エッチバック工程が不要となるので、製造工程が簡素化される。 In the third embodiment of the present invention, the strain distribution is reduced by utilizing the difference in film thickness between the SiO 2 film and the SiN film covering the upper surface of the mesa. Since the back process is not necessary, the manufacturing process is simplified.

次に、図12を参照して、本発明の実施例4の光半導体集積回路装置を説明する。ここでは、上記の実施例1の4×4MMI光分岐器を各ポート間で位相が90°ずれるフォトダイオード集積90°ハイブリッド素子に適用した例を説明する。   Next, an optical semiconductor integrated circuit device according to Example 4 of the present invention will be described with reference to FIG. Here, an example in which the 4 × 4 MMI optical branching device of the first embodiment is applied to a photodiode integrated 90 ° hybrid element in which the phase is shifted by 90 ° between the ports will be described.

図12は、本発明の実施例4の光半導体集積回路装置の平面図であり、4本の導波路を備えた入力導波路部41、4×4MMI光分岐器42、4本の導波路を備えた出力導波路部43及び4つのフォトダイオードを備えたPD部44からなる。   FIG. 12 is a plan view of an optical semiconductor integrated circuit device according to a fourth embodiment of the present invention. The input waveguide section 41 includes four waveguides, the 4 × 4 MMI optical branching device 42, and the four waveguides. The output waveguide section 43 includes a PD section 44 including four photodiodes.

入力導波路41の例えば左から1番目の導波路に位相変調信号光が、3番目の導波路に局所発振光が入射され、4×4MMI光分岐器42においてそれぞれ4等分に分岐された後に、出力導波路63を介してPD部44のフォトダイオード44〜44に入力される。フォトダイオード44〜44では入力した光の強度に比例して電流が出力される。 For example, after the phase-modulated signal light is incident on the first waveguide from the left of the input waveguide 41 and the local oscillation light is incident on the third waveguide and branched into four equal parts in the 4 × 4 MMI optical splitter 42, respectively. The light is input to the photodiodes 44 1 to 44 4 of the PD unit 44 through the output waveguide 63. In the photodiodes 44 1 to 44 4 , a current is output in proportion to the intensity of the input light.

フォトダイオード44〜44に入力する光の強度は、位相変調信号光と局所発振光の位相関係で決まり、フォトダイオード44とフォトダイオード44の出力電流の差分及びフォトダイオード44とフォトダイオード44の出力電流の差分をモニタすることにより、位相変調信号光の位相状態を検出することができる。フォトダイオード44〜44への位相変調信号光および局所発振光が4×4MMI光分岐器42において正確に4等分されないと(偏差があると)、この差分信号にずれが生じ、位相変調信号光の位相状態を正確に検出することができない。 The intensity of light input to the photodiode 44 1-44 4, the phase-modulated optical signal and determined by the phase relationship between the local oscillation light, the photodiode 44 1 and the differential and the photodiode 44 3 and the photo of the photodiode 44 and second output current by monitoring the difference between the output current of the diode 44 4, it is possible to detect the phase state of the phase-modulated optical signal. If the phase-modulated signal light and local oscillation light to the photodiodes 44 1 to 44 4 are not accurately divided into four equal parts (if there is a deviation) in the 4 × 4 MMI optical branching unit 42, the difference signal is shifted and phase modulation is performed. The phase state of the signal light cannot be accurately detected.

また、各フォトダイオード44〜44は、半絶縁性InP基板上に順次成膜されたn型InPバッファ層、i型InGaAsP光吸収層、p型InPクラッド層及びp型InGaAsコンタクト層をメサエッチすることによって形成される。また、各フォトダイオード44〜44には、それぞれn側電極45〜45及びp側電極46〜46が設けられている。 In addition, each of the photodiodes 44 1 to 44 4 mesa-etches an n-type InP buffer layer, an i-type InGaAsP light absorption layer, a p-type InP cladding layer, and a p-type InGaAs contact layer that are sequentially formed on a semi-insulating InP substrate. It is formed by doing. In addition, each photodiode 44 1 ~ 44 4, n-side electrodes 45 1 to 45 4 and the p-side electrode 46 1-46 4 are provided, respectively.

また、入力導波路及び出力導波路は4×4MMI光分岐器と同じ積層構造を有しており、メサ構造のフォトダイオード44〜44にバットジョイント接合するように下部クラッド層、コア層及び上部クラッド層を積層したのち、ハイメサ構造となるようにエッチングして形成する。ここでは、MMI導波路の上面のみSiO膜29で、それ以外のMMI導波路の側面および底面をSiN膜31で覆っているので、フォトダイオード44〜44に対するパッシベーション膜もSiN膜31で形成する。PD部44のパッシベーション膜としては、SiO膜よりSiNの方が適しているため、MMI導波路を覆う2層の絶縁膜のうち、SiN膜がMMI導波路の上面以外の部分に直接形成されるような上記の構造の方が望ましい。 The input waveguide and the output waveguide have the same stacked structure as the 4 × 4 MMI optical splitter, and the lower cladding layer, the core layer, and the mesa structure photodiodes 44 1 to 44 4 are butt-jointed to each other. After the upper clad layer is laminated, it is etched to form a high mesa structure. Here, since only the upper surface of the MMI waveguide is covered with the SiO 2 film 29 and the other side surfaces and the bottom surface of the MMI waveguide are covered with the SiN film 31, the passivation film for the photodiodes 44 1 to 44 4 is also the SiN film 31. Form. As the passivation film of the PD portion 44, SiN is more suitable than the SiO 2 film, and therefore, the SiN film is formed directly on the portion other than the upper surface of the MMI waveguide, out of the two insulating films covering the MMI waveguide. The above structure is preferable.

この実施例4においても、4×4MMI光分岐器は実施例1の場合と同様に4×4MMI導波路の歪分布を緩和し、MMIの偏差を抑制することが可能となる。その結果、偏差によるフォトダイオード44とフォトダイオード44の差分信号及びフォトダイオード44とフォトダイオード44の差分信号のズレを抑制し、位相変調信号光の位相状態を正確に検出することが可能となる。 Also in the fourth embodiment, the 4 × 4 MMI optical branching unit can relax the strain distribution of the 4 × 4 MMI waveguide and suppress the deviation of the MMI as in the first embodiment. As a result, it possible to suppress the deviation of the photodiode 44 1 and the photodiode 44 second difference signal and the difference signal of the photodiode 44 3 and the photodiode 44 4 by deviations, to accurately detect the phase state of the phase-modulated optical signal It becomes possible.

上記の各実施例においては、MMI光分岐器として、入力ポート及び出力ポートが4本ずつの4×4MMI光分岐器として説明しているが、入力ポートが2本の2×4MMI光分岐器や、その他の構成のMMI光分岐器にも適用されるものである。   In each of the above embodiments, the MMI optical branching device has been described as a 4 × 4 MMI optical branching device having four input ports and four output ports, but a 2 × 4 MMI optical branching device having two input ports, The present invention is also applicable to MMI optical branching devices having other configurations.

また、実施例4においては、光分岐器とPDとを集積した光半導体素子について説明したが、PDの代わりに、半導体レーザ、半導体光増幅器、半導体光変調器などの他の光半導体素子をMMI導波路とモノリシックに集積化しても良いものである。その際、半導体レーザ、半導体光増幅器、半導体光変調器を覆う絶縁膜がそれぞれの素子のパッシベーション膜としてより適した絶縁膜になるように、MMI導波路の上面の絶縁膜とそれ以外のMMI導波路の側面及び底面を覆う絶縁膜を選択するのが望ましい。具体的には、MMI導波路を覆う2つの絶縁膜のうち、MMI導波路の側面及び底面を覆う方の絶縁膜を、各素子のパッシベーション膜として適した絶縁膜にするのが望ましい。   In the fourth embodiment, the optical semiconductor element in which the optical branching device and the PD are integrated has been described. Instead of the PD, another optical semiconductor element such as a semiconductor laser, a semiconductor optical amplifier, or a semiconductor optical modulator is used as the MMI. It may be monolithically integrated with the waveguide. At that time, the insulating film on the upper surface of the MMI waveguide and other MMI waveguides are formed so that the insulating film covering the semiconductor laser, the semiconductor optical amplifier, and the semiconductor optical modulator becomes a more suitable insulating film as a passivation film of each element. It is desirable to select an insulating film that covers the side and bottom surfaces of the waveguide. Specifically, among the two insulating films covering the MMI waveguide, it is desirable that the insulating film covering the side and bottom surfaces of the MMI waveguide is an insulating film suitable as a passivation film for each element.

ここで、実施例1乃至実施例4を含む本発明の実施の形態に関して、以下の付記を付す。
(付記1)基板と、前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値であることを特徴とする光分岐器。
(付記2)前記第1の絶縁膜は、更に、前記第2の絶縁膜を覆っていることを特徴とする付記1に記載の光分岐器。
(付記3)前記第1の絶縁膜が前記第2の絶縁膜より薄いことを特徴とする付記2に記載の光分岐器。
(付記4)前記第1の絶縁膜が更に前記第2の絶縁膜で覆われていることを特徴とする付記1に記載の光分岐器。
(付記5)前記第2の絶縁膜が前記第1の絶縁膜より薄いことを特徴とする付記4に記載の光分岐器。
(付記6) 前記多モード干渉導波路の半導体上面を直接接して覆う第1の絶縁膜と半導体上面を直接接して覆う第2の絶縁膜の少なくともいずれかが、前記半導体上面と側面とが交わる角の近傍において半導体表面に直接接していないことを特徴とする付記1乃至付記5のいずれか1つに記載の光分岐器。
(付記7)基板上に、前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値である光分岐器と、半導体レーザ、半導体光増幅器、半導体光変調器或いはフォトダイオードのうちの少なくとも一種類の光半導体素子とがモノリシックに集積されていることを特徴とする光半導体集積回路装置。
(付記8)前記光半導体素子を被覆するパッシベーション膜が、前記第1の絶縁体膜或いは前記第2の絶縁体膜のいずれかであることを特徴とする付記7に記載の光半導体集積回路。
(付記9)前記光半導体素子がフォトダイオードであり、前記フォトダイオードと、前記フォトダイオードと前記光分岐器とを接続する接続導波路と、前記光分岐器と、前記光分岐器に接続する入力導波路とを順に配置したことを特徴とする付記7または付記8に記載の光半導体集積回路装置。
Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 4.
(Additional remark 1) Laminated structure of a substrate, a semiconductor waveguide core layer provided above the substrate, and a semiconductor clad layer disposed above and below the semiconductor waveguide core layer and having a refractive index lower than that of the semiconductor waveguide core layer A mesa-shaped multimode interference waveguide having: a first insulator film provided on an upper surface of the multimode interference waveguide; and a second insulator film provided on a side surface of the multimode interference waveguide. The coefficient of thermal expansion of the semiconductor waveguide core layer and the cladding layer is a value between the coefficient of thermal expansion of the first insulator film and the coefficient of thermal expansion of the second insulator film. Optical branching device.
(Supplementary note 2) The optical branching device according to supplementary note 1, wherein the first insulating film further covers the second insulating film.
(Supplementary note 3) The optical branching device according to supplementary note 2, wherein the first insulating film is thinner than the second insulating film.
(Supplementary note 4) The optical branching device according to supplementary note 1, wherein the first insulating film is further covered with the second insulating film.
(Supplementary note 5) The optical branching device according to supplementary note 4, wherein the second insulating film is thinner than the first insulating film.
(Appendix 6) At least one of the first insulating film that directly covers and covers the semiconductor upper surface of the multimode interference waveguide and the second insulating film that covers and directly contacts the semiconductor upper surface intersect the semiconductor upper surface and the side surface. 6. The optical branching device according to any one of appendices 1 to 5, wherein the optical splitter is not in direct contact with the semiconductor surface in the vicinity of the corner.
(Appendix 7) Lamination of a semiconductor waveguide core layer provided above the substrate and a semiconductor clad layer disposed above and below the semiconductor waveguide core layer and having a refractive index lower than that of the semiconductor waveguide core layer on the substrate A mesa-shaped multimode interference waveguide having a structure, a first insulator film provided on an upper surface of the multimode interference waveguide, and a second insulator film provided on a side surface of the multimode interference waveguide; An optical branching device in which the thermal expansion coefficient of the semiconductor waveguide core layer and the cladding layer is a value between the thermal expansion coefficient of the first insulator film and the thermal expansion coefficient of the second insulator film And a semiconductor laser, a semiconductor optical amplifier, a semiconductor optical modulator, or at least one optical semiconductor element of a photodiode are monolithically integrated.
(Additional remark 8) The optical semiconductor integrated circuit of Additional remark 7 characterized by the above-mentioned. The passivation film which coat | covers the said optical semiconductor element is either the said 1st insulator film or the said 2nd insulator film.
(Supplementary Note 9) The optical semiconductor element is a photodiode, the photodiode, a connection waveguide connecting the photodiode and the optical branching device, the optical branching device, and an input connected to the optical branching device. 9. The optical semiconductor integrated circuit device according to appendix 7 or appendix 8, wherein waveguides are arranged in order.

11 半導体導波路コア層
12,13 半導体クラッド層
14 MMI導波路
15 第1の絶縁体膜
16 第2の絶縁体膜
17 入力導波路
18 出力導波路
21 半絶縁性InP基板
22 i型InPバッファ層
23 i型InGaAsPコア層
24 i型InPクラッド層
25 SiOマスク
26 MMI導波路
27 入力導波路
28 出力導波路
29,34 SiO
30,33 レジストパターン
31,32 SiN膜
41 入力導波路部
42 4×4MMI光分岐器
43 出力導波路部
44 PD部
44〜44 フォトダイオード
45〜45 n側電極
46〜46 p側電極
61 入力導波路
62 4×4MMI光分岐器
62 入力ポート
62 MMI導波路
62 出力ポート
63 出力導波路
64 PD
70 4×4MMI光分岐器
71 下部クラッド層
72 コア層
73 上部クラッド層
74 入力ポート
75 MMI導波路
76 出力ポート
77 絶縁体膜
DESCRIPTION OF SYMBOLS 11 Semiconductor waveguide core layers 12 and 13 Semiconductor clad layer 14 MMI waveguide 15 1st insulator film 16 2nd insulator film 17 Input waveguide 18 Output waveguide 21 Semi-insulating InP substrate 22 i-type InP buffer layer 23 i-type InGaAsP core layer 24 i-type InP clad layer 25 SiO 2 mask 26 MMI waveguide 27 input waveguide 28 output waveguide 29, 34 SiO 2 film 30, 33 resist pattern 31, 32 SiN film 41 input waveguide section 42 4 × 4 MMI optical splitter 43 Output waveguide portion 44 PD portion 44 1 to 44 4 Photo diode 45 1 to 45 4 n-side electrode 46 1 to 46 4 p-side electrode 61 Input waveguide 62 4 × 4 MMI optical splitter 62 1 Input port 62 2 MMI waveguide 62 3 Output port 63 Output waveguide 64 PD
70 4 × 4 MMI optical splitter 71 Lower cladding layer 72 Core layer 73 Upper cladding layer 74 Input port 75 MMI waveguide 76 Output port 77 Insulator film

Claims (4)

基板と、
前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、
前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、
前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、
前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値であることを特徴とする光分岐器。
A substrate,
A mesa-shaped multimode having a laminated structure of a semiconductor waveguide core layer provided above the substrate and a semiconductor clad layer disposed above and below the semiconductor waveguide core layer and having a refractive index lower than that of the semiconductor waveguide core layer An interference waveguide;
A first insulator film provided on an upper surface of the multimode interference waveguide;
A second insulator film provided on a side surface of the multimode interference waveguide,
The light whose thermal expansion coefficient of the said semiconductor waveguide core layer and a clad layer is a value between the thermal expansion coefficient of the said 1st insulator film, and the thermal expansion coefficient of the said 2nd insulator film, Turnout.
前記第1の絶縁膜は、更に、前記第2の絶縁膜を覆っていることを特徴とする請求項1に記載の光分岐器。   The optical branching device according to claim 1, wherein the first insulating film further covers the second insulating film. 前記第2の絶縁膜は、更に、前記第1の絶縁膜を覆っていることを特徴とする請求項1に記載の光分岐器。   The optical branching device according to claim 1, wherein the second insulating film further covers the first insulating film. 基板上に、
前記基板の上方に設けた半導体導波路コア層と、前記半導体導波路コア層の上下に配置され前記半導体導波路コア層より屈折率が低い半導体クラッド層との積層構造を有するメサ状の多モード干渉導波路と、前記多モード干渉導波路の上面に設けた第1の絶縁体膜と、前記多モード干渉導波路の側面に設けた第2の絶縁体膜とを備え、前記半導体導波路コア層及びクラッド層の熱膨張係数が、前記第1の絶縁体膜の熱膨張係数と前記第2の絶縁体膜の熱膨張係数の間の値である光分岐器と、
半導体レーザ、半導体光増幅器、半導体光変調器或いはフォトダイオードのうちの少なくとも一種類の光半導体素子とがモノリシックに集積されていることを特徴とする光半導体集積回路装置。
On the board
A mesa-shaped multimode having a laminated structure of a semiconductor waveguide core layer provided above the substrate and a semiconductor clad layer disposed above and below the semiconductor waveguide core layer and having a refractive index lower than that of the semiconductor waveguide core layer The semiconductor waveguide core, comprising: an interference waveguide; a first insulator film provided on an upper surface of the multimode interference waveguide; and a second insulator film provided on a side surface of the multimode interference waveguide. An optical branching device in which a coefficient of thermal expansion of the layer and the cladding layer is a value between a coefficient of thermal expansion of the first insulator film and a coefficient of thermal expansion of the second insulator film;
An optical semiconductor integrated circuit device, wherein at least one kind of optical semiconductor element of a semiconductor laser, a semiconductor optical amplifier, a semiconductor optical modulator, or a photodiode is monolithically integrated.
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JP2016111108A (en) * 2014-12-03 2016-06-20 富士通株式会社 Optical function element, optical reception device and optical transmission device
JP2016194655A (en) * 2015-04-01 2016-11-17 日本電信電話株式会社 Optical waveguide device

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JP2010226062A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical waveguide element, manufacturing method therefor, semiconductor device, laser module, and optical transmission system

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JP2010226062A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical waveguide element, manufacturing method therefor, semiconductor device, laser module, and optical transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016111108A (en) * 2014-12-03 2016-06-20 富士通株式会社 Optical function element, optical reception device and optical transmission device
JP2016194655A (en) * 2015-04-01 2016-11-17 日本電信電話株式会社 Optical waveguide device

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