JP2014014118A - Signal transmitter/receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmitter/receiver capable of transmitting/receiving a plurality of types of digital signals on an as small number of transmission paths as possible.SOLUTION: A signal transmitter/receiver includes: a clock generation section 100 having a plurality of time-division time slots for generating a clock signal for ticking one cycle for each time slot, and for transmitting the clock signal to the outside; a reset generation section 110 for generating a reset signal for ticking one cycle each time the time-division time slot circulates once, and for transmitting the reset signal to the outside; a master side transmission section 120 configured to generate and transmit a pulse having pulse width corresponding to a sample value of a signal to be transmitted for transmitting the pulse synchronously with a predetermined time slot among the respective time slots; and a master side reception section 130 configured to receive a signal having pulse width corresponding to the sample value of the signal, and to demodulate the signal corresponding to the pulse width for receiving the signal synchronously with the predetermined time slot among the respective time slots, on the master side.

Description

  The present invention relates to a signal transmission / reception apparatus for digital signals.

  In the conventional digital signal transmission / reception apparatus, when a plurality of types of data are transmitted / received, a plurality of sets of transmission systems are required. In other words, since a digital signal is usually a signal based on one bit of “0” and “1”, it is necessary to have only one path for transfer, and even if transmission / reception is performed, 2 is required. A route should be sufficient, but it also requires a clock signal, a reset signal, and other routes for synchronizing signals.

  In such a state, as the number of digital signals to be transmitted / received increases, the required number of transmission paths increases, which is a big problem.

  The present invention has been devised in view of the above problems, and is intended to provide a configuration of a signal transmission / reception apparatus capable of transmitting and receiving a plurality of types of digital signals through as few transmission paths as possible.

The configuration of the invention relating to the signal transmitting / receiving apparatus of the present invention is as follows:
A plurality of time-division time slots on the master side, a clock generating means for generating a clock signal that ticks one period for each time slot and sending the clock signal to the outside;
A reset generation means for generating a reset signal for engraving one period each time the time-division time slot makes a round, and sending the reset signal to the outside;
Signal transmitting means for generating and transmitting a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, the transmitting means transmitting the pulse in synchronization with a predetermined time slot among the time slots; ,
A signal receiving means for receiving a signal having a pulse width corresponding to a sample value of the signal and demodulating the signal corresponding to the pulse width, wherein the signal is synchronized with a predetermined time slot among the time slots; Receiving means for receiving,
On the slave side,
A time-division time slot synchronization means for generating a time-division time slot synchronized with the master side by receiving a reset signal sent from the clock and reset generation means sent by the clock generation means;
Signal transmitting means for generating and transmitting a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, the transmitting means transmitting the pulse in synchronization with a predetermined time slot among the time slots; ,
A signal receiving means for receiving a signal having a pulse width corresponding to a sample value of the signal and demodulating the signal corresponding to the pulse width, wherein the signal is synchronized with a predetermined time slot among the time slots; It has a basic feature of having receiving means for receiving.

  In the first signal transmitting / receiving apparatus, more specifically, the time slot on the master side or the slave side is formed by a counter that counts the clock, and the time slot on the master side or the slave side is A configuration formed by a counter that counts the clock is desirable.

  Further, in the configuration of the first signal transmitting / receiving apparatus, the clock, the reset signal, and the transfer transmitting / receiving signal are preferably composed of a pair of signals having opposite logics and are transmitted / received through a twisted pair path.

  According to the above configuration, the master side is provided with the clock generation means and the reset means, and the bit clock and the reset signal are placed on the transmission path between the master and the slave, so that a plurality of types of transmission paths can be set in one set. Signals can be sent and received.

  According to the configuration of the present invention, the master side is provided with the clock generation means and the reset means, and the bit clock and the reset signal are placed on the transmission path between the master and the slave, so that one set of transmission paths. There is an excellent effect that a plurality of types of signals can be transmitted and received.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 and FIG. 2 are block diagrams of a configuration capable of transmitting and receiving 4 signals × 2 (T1 to T4 and S1 to S4) pulse width modulation analog signals transmitted and received according to an embodiment of the first invention. is there. Among them, the configuration in FIG. 1 is a configuration on the master side of the signal transmission / reception device, and the configuration in FIG. 2 is a configuration on the slave side of the signal transmission / reception device.

  On the master side of the signal transmission / reception apparatus, a plurality of time-division time slots are provided, a clock signal generating one cycle for each time slot is generated and sent to the outside, and the time division The configuration is such that a reset signal that divides a cycle every time slot is generated and is transmitted to the outside, and a pulse having a pulse width corresponding to the sample value of the signal to be transmitted is generated and transmitted. The master-side transmitting unit 120 that transmits the pulse in synchronization with a predetermined time slot among the time slots, and receives a signal having a pulse width corresponding to the sample value of the signal, according to the pulse width And a master side receiving unit 130 that receives the signal in synchronization with a predetermined time slot among the time slots. To have.

  The slave side of the apparatus receives a clock sent from the clock generator 100 and a reset signal sent from the reset generator 110, and generates a time-division time slot synchronized with the master side. The synchronization unit 140 generates and transmits a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, and transmits the pulse in synchronization with a predetermined time slot among the time slots. The slave-side transmitter 150 is configured to receive a signal having a pulse width corresponding to the sample value of the signal and demodulate the signal corresponding to the pulse width, and is synchronized with a predetermined time slot among the time slots. And a slave side receiving unit 160 for receiving the signal.

  The configuration of the master side of the signal transmitting / receiving apparatus will be described in further detail. First, the clock generation unit 100 and the reset generation unit 110 are configured only on the master side.

  Among them, the clock generation unit 100 is a normal clock generator, and the generated clock signal CLK is used on the master side and also sent to the slave side to be used for synchronization between the master and the slave. With this configuration, as shown in FIG. 3, a plurality of time-division time slots (eight in this example) are set, but the clock signal CLK has one cycle for each time slot.

  As shown in FIG. 3 and above, the reset generator 110 is configured to generate a reset signal RST that ticks one cycle every time the time-division time slot goes around, and to send the signal to the slave side. Therefore, it is composed of a NAND circuit. When any of timing signals b0, b1 or b2 (see FIG. 8) generated by the octal counter 121 described later is OFF (when one is Low), the reset signal RST is set to High and output. When all of the signals are ON (when all are High), the reset signal RST is set to Low and output. This reset signal RST is output to the slave side.

  The clock signal CLK is input to the CK of the octal counter 121 of the master side transmission unit 120 to generate time-division timing signals b0, b1, and b2 obtained by dividing the clock signal CLK by 2, 4, and 8, respectively. . b0 to b2 form eight time-division time slots from the Low / High combination of the signals. In the eight time-division time slots, S1, T1, S2, T2, S3, T3, S4, and T4 are sequentially transmitted and received between the master and slave transmission / reception devices as the signal SIG to be transmitted / received. The number of time division time slots can be increased or decreased as necessary. In that case, the counter may be changed according to the number of time-division time slots, and the reset signal may be changed so as to make one cycle every time the time-division time slot makes a round.

  In the master side transmission unit 120, analog transmission signals T1 to T4 (from the master side to the slave side) are input to the sample and hold circuits 122a to 122d, respectively. The input analog transmission signals T1 to T4 are sampled at the down edge timing of the clock signal CLK. The sampled transmission signals T1 to T4 are sent to the demultiplexer 123, and are sequentially extracted according to the states of the timing signals b1 and b2. That is, when both b1 and b2 are low, T1 is obtained. When b1 is high and b2 is low, T2 is obtained. When b1 is low and b2 is high, T3 is obtained. When both b1 and b2 are high, T4 is produced. Is taken out. The extracted sample values of T1 to T4 are converted by the analog PWM conversion circuit 125 into pulses having a pulse width corresponding to the sample value. Since the minimum value of the pulse width is 0 and the maximum value is the pulse width of each time slot, this maximum value is equal to the period of the clock signal CLK.

  As shown in FIG. 3, when the timing signal b0 is High, the converted pulse is output as a signal SIG to the signal transmission / reception line through the gate circuit 124 and is transmitted to the slave transmission / reception device. On the other hand, when the timing signal b0 is Low, the gate circuit 124 is closed and no pulse is transmitted to the signal transmission / reception line.

  On the other hand, the master side receiving unit 130 receives the SIG from the slave transmission / reception device via the signal transmission / reception line. As shown in FIG. 3, when the timing signal b0 is low, SIG is one of the reception signals S1 to S4 (received by the master side from the slave side), and this reception signal S1 to S4 is converted to b0 by the inverter 131. The signal is received through the gate circuit 132 controlled by the inverted signal. When the timing signal b0 is High, that is, when the output of the inverter 131 is Low, the gate circuit 132 is closed, and the gate circuit 132 outputs Low regardless of the input. Therefore, Low is sent to the multiplexer 133. The On the other hand, when the timing signal b0 is Low, that is, when the output of the inverter 131 is High, a pulse having a pulse width corresponding to any sample value of the reception signals S1 to S4 is sent to the multiplexer 133 via the gate circuit 132. The

  The multiplexer 133 distributes the received signals S1 to S4 received through the gate circuit 132 to the low-pass filters 134a to 134d according to the states of the timing signals b1 and b2. That is, when both b1 and b2 are low, S1 is 134a, when b1 is high and b2 is low, S2 is 134b, when b1 is low and b2 is high, S3 is 134c, and b1 and b2 are either In the case of High, S4 is assigned to 134d. The sorted reception signals S1 to S4 are demodulated into original analog signals by the low-pass filters 134a to 134d. Since the pulse widths of the received signals S1 to S4 are the same as those of T1 to T4 to be transmitted, the cutoff frequency of the low-pass filters 134a to 134d is 1 / t [Hz], where the maximum value of this pulse width is t [sec]. The following is desirable.

  On the other hand, the configuration on the slave side will be described.

  As shown in FIG. 2, the slave side of the signal transmission / reception apparatus receives a clock sent from the clock generator 100 and a reset signal sent from the reset generator 110 and is synchronized with the master side. A time-division time slot synchronization unit 140 for generating a slot and a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, and transmitting the pulse to a predetermined time slot among the time slots. A slave-side transmitter 150 for transmitting the pulses in synchronism with each other, and a configuration for receiving a signal having a pulse width corresponding to the sample value of the signal and demodulating the signal corresponding to the pulse width, Of these, a slave-side receiving unit 160 that receives the signal in synchronization with a predetermined time slot is included.

  The time division time slot synchronization unit 140 is composed of an octal counter similar to the octal counter 121 of the master side transmission unit 120, and receives the clock signal CLK generated from the master side as described above. As shown in FIG. 3, timing signals b0, b1, and b2 are generated by dividing the signal by 2, 4, and 8.

  Here, unlike the octal counter 121, the time division time slot synchronization unit (octal counter) 140 includes a counter value reset input RS. A reset signal RST generated from the master-side reset generation unit 110 is input to the reset input RS, and the count values are all reset to 0 at the up edge of the reset signal RST. That is, the octal counter 140 generates timing signals b0, b1, and b2 obtained by dividing the CLK of the master side clock generation unit 110 by 2, 4, and 8, respectively, but the reset signal RST generated from the master side reset generation unit 110. Since the timing at which the timing signals b0 to b2 become 0 is controlled by this, the timings indicating 0/1 of the master side timing signals b0 to b2 and the slave side timing signals b0 to b2 are synchronized. Therefore, the master side and slave side time-division time slots are synchronized only by transmitting the clock signal CLK and the reset signal RST without transmitting the three types of timing signals b0, b1, and b2 from the master side to the slave side. can do. The greater the number of time division time slots, that is, the greater the number of types of signals to be transmitted and received, the greater the effect.

  In the slave side transmission unit 120, analog transmission signals S1 to S4 (from the slave side to the master side) are input to the sample and hold circuits 151a to 151d, respectively. The input analog transmission signals S1 to S4 are sampled at the down edge timing of the clock signal CLK. The sampled transmission signals S1 to S4 are sent to the demultiplexer 152, and sequentially extracted according to the states of the timing signals b1 and b2. That is, when both b1 and b2 are low, S1 is obtained, when b1 is high and b2 is low, S2 is obtained, when b1 is low and b2 is high, S3 is obtained, and when both b1 and b2 are high, S4 is produced. Is taken out. The extracted sample values of S1 to S4 are converted into pulses having a pulse width corresponding to the sample value by the analog PWM conversion circuit 155. Since the minimum value of the pulse width is 0 and the maximum value is the pulse width of each time slot, this maximum value is equal to the period of the clock signal CLK.

  As shown in FIG. 3, when the timing signal b0 is low, that is, when the output of the inverter 153 is high, the converted pulse is sent to the master transmission / reception device as a signal SIG through the gate circuit 154 to the signal transmission / reception line. The On the other hand, when the timing signal b0 is High, that is, when the output of the inverter 153 is Low, the gate circuit 154 is closed, and no pulse is transmitted to the signal transmission / reception line.

  On the other hand, the slave side receiving unit 130 receives the signal SIG from the slave transmission / reception device via the signal transmission / reception line. As shown in FIG. 3, when the timing signal b0 is high, the signal SIG is one of the reception signals T1 to T4 (received from the slave side from the master side), and the reception signals T1 to T4 are the timing signal b0. Receive via controlled gate circuit 161. When the timing signal b0 is Low, the gate circuit 161 is closed, and the gate circuit 161 outputs Low regardless of the input, so Low is sent to the multiplexer 162. On the other hand, when the timing signal b 0 is High, a pulse having a pulse width corresponding to any sample value of the reception signals T 1 to T 4 is sent to the multiplexer 162 via the gate circuit 161.

  The multiplexer 162 distributes the received signals T1 to T4 received through the gate circuit 161 to the low-pass filters 163a to 163d according to the states of the timing signals b1 and b2. That is, when both b1 and b2 are low, T1 is 163a, when b1 is high and b2 is low, T2 is 163b, when b1 is low and b2 is high, T3 is 163c, and b1 and b2 are either In the case of High, T4 is assigned to 163d. The distributed reception signals T1 to T4 are demodulated into original analog signals by the low-pass filters 163a to 163d. Since the pulse widths of the received signals T1 to T4 are the same as those of the transmitted S1 to S4, the cut-off frequency of these low-pass filters is 1 / t [Hz] or less with the maximum value of the pulse width being t [sec]. Is desirable.

  According to the above configuration, the clock generation unit 100 and the reset generation unit 110 are provided on the master side, and the bit clock and the reset signal are placed on the transmission path between the master and the slave. A plurality of types of signals can be transmitted and received through a set of transmission paths.

  FIGS. 4 and 5 are transmission / reception configurations of a power supply type pulse width modulation system of 4 signals × 2 (T1 to T4 and S1 to S4) transmitted and received by 8 lines (4 pairs of twisted pairs) according to an embodiment of the third invention. FIG. 4 is the configuration on the master side of the signal transmission / reception device, and the configuration in FIG. 5 is the configuration on the slave side of the signal transmission / reception device.

  Unlike the first embodiment, the above-described embodiment is characterized in that the influence of noise can be canceled because the transmission path is composed of a twisted pair cable. That is, the clock, the reset signal, and the transfer transmission / reception signal are composed of a pair of signals having opposite logics, and are transmitted and received through a twisted pair path. The rest of the basic configuration is almost the same as that of the third embodiment, and a detailed description thereof will be omitted.

  However, the gate circuits 170a to 170c in FIG. 4 and the gate circuit 170d in FIG. 5 are different from the unbalanced signal (a signal is formed by a potential difference from the ground) and a balanced type (a signal is generated by a potential difference between two signal lines). A transceiver circuit that converts to When the balanced type is used, even when communication is performed over a long distance, even if the communication line picks up noise (the noise signal is superimposed on both +/- signal lines in the same phase), differential reception is possible during reception. In doing so, the superimposed noises cancel each other and have no effect.

  Similarly, the gate circuit 171a of FIG. 4 and the gate circuits 171b to 171d of FIG. 5 are transceiver circuits that receive the above balanced signal by a differential circuit and convert them to an unbalanced type. Since there is little noise from the outside inside the equipment, etc., an unbalanced type that is easy to handle is used. However, since the circuit behind this transceiver operates in an unbalanced type in this embodiment, the communication line (balanced type) and Is installed to take the interface between.

  In addition, any one of the power source, the ground and the clock (CLK +/−), the power source, the ground, and the reset (RST +/−) or the power source, the ground, and the signal (SIG +/−) in this embodiment is the same as that in the second embodiment. The method can be shared using the method, in which case the circuit can be composed of three twisted pairs.

  The signal transmitting / receiving apparatus according to the present invention is not limited to the illustrated examples described above, and it is needless to say that various changes can be made without departing from the gist of the present invention.

  The signal transmission / reception apparatus of the present invention can be applied to anything used for signal transfer. For example, as a configuration of a group learning apparatus that performs transmission / reception between one-to-many or many-to-many for music performance learning and language practice. It can also be used.

It is a block diagram which shows the structure by the side of the master of the signal transmission / reception apparatus which concerns on the Example of 1st invention. It is a block diagram which shows the structure by the side of the slave of the signal transmission / reception apparatus which concerns on the Example of 1st invention. It is waveform explanatory drawing which shows the transmission / reception timing in the case of the said Example 1. FIG. It is a block diagram which shows the structure by the side of the master of the signal transmission / reception apparatus which concerns on the Example of 2nd invention. It is a block diagram which shows the structure by the side of the slave of the signal transmission / reception apparatus which concerns on the Example of 2nd invention.

100 clock generation unit 110 reset generation unit 120 master side transmission unit 121 octal counters 122a to 122d, 124, 132, 154, 161 gate circuit 123, 152 demultiplexer 125, 155 analog PWM conversion circuit 130 master side reception units 131, 153 inverter 133, 162 Multiplexer 140 Time-division time slot synchronization unit 150 Slave side transmission units 151a to 151d Sample and hold circuit 160 Slave side reception unit

Claims (3)

A plurality of time-division time slots on the master side, a clock generating means for generating a clock signal that ticks one period for each time slot and sending the clock signal to the outside;
A reset generation means for generating a reset signal for engraving one period each time the time-division time slot makes a round, and sending the reset signal to the outside;
Signal transmitting means for generating and transmitting a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, the transmitting means transmitting the pulse in synchronization with a predetermined time slot among the time slots; ,
A signal receiving means for receiving a signal having a pulse width corresponding to a sample value of the signal and demodulating the signal corresponding to the pulse width, wherein the signal is synchronized with a predetermined time slot among the time slots; Receiving means for receiving,
On the slave side,
A time-division time slot synchronization means for generating a time-division time slot synchronized with the master side by receiving a reset signal sent from the clock and reset generation means sent by the clock generation means;
Signal transmitting means for generating and transmitting a pulse having a pulse width corresponding to a sample value of a signal to be transmitted, the transmitting means transmitting the pulse in synchronization with a predetermined time slot among the time slots; ,
A signal receiving means for receiving a signal having a pulse width corresponding to a sample value of the signal and demodulating the signal corresponding to the pulse width, wherein the signal is synchronized with a predetermined time slot among the time slots; A signal transmitting / receiving apparatus comprising: a receiving means for receiving. The time slot on the master side or the slave side is formed by a counter that counts the clock,
The signal transmitting / receiving apparatus according to claim 1, wherein the reset signal is formed when the counter counts a predetermined value.   3. The signal transmission / reception apparatus according to claim 1, wherein the clock, the reset signal, and the transfer transmission / reception signal are composed of a pair of signals having opposite logics, and are transmitted / received through a twisted pair path. .

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