JP2014013885A - Method of manufacturing circuit and circuit - Google Patents

Method of manufacturing circuit and circuit Download PDF

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JP2014013885A
JP2014013885A JP2013113020A JP2013113020A JP2014013885A JP 2014013885 A JP2014013885 A JP 2014013885A JP 2013113020 A JP2013113020 A JP 2013113020A JP 2013113020 A JP2013113020 A JP 2013113020A JP 2014013885 A JP2014013885 A JP 2014013885A
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semiconductor chip
circuit
manufacturing
liquid
adhesive layer
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JP6098371B2 (en
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Katsuhiko Hieda
克彦 稗田
Tomokazu Miyazaki
智和 宮崎
Katsumi Inomata
克巳 猪俣
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JSR Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80004—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H01L2224/95146—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a circuit capable of arranging a semiconductor chip with high precision and fixing the semiconductor chip to a substrate easily and reliably.SOLUTION: According to the invention, there is provided a method of manufacturing a circuit in which a semiconductor chip is arranged on a defining part of a substrate. The method comprises the steps of: forming a photosensitive adhesive layer on the substrate; forming the defining part by selectively exposing and developing the photosensitive adhesive layer; mounting a liquid on a surface of the defining part; mounting the semiconductor chip on the liquid; and temporarily adhering the semiconductor chip by removing the liquid. The photosensitive adhesive layer should preferably include a hydrophilic layer. The liquid should preferably include a flux component. The method should preferably further comprise a step of adhering the semiconductor chip to the defining part. The semiconductor chip should preferably include a hydrophilic surface. A manufacturing flow comprising the above-described steps should preferably be performed a plurality of times.

Description

本発明は、回路の製造方法及び回路に関する。   The present invention relates to a circuit manufacturing method and a circuit.

回路の製造方法として、自己組織化（セルフアセンブリ）機能を用いて半導体チップを基板上に高効率かつ高精度で配置する製造方法が提案されている（特開２０１０−２４５４５２号公報参照）。この製造方法は、基板上の半導体チップを配置する領域を親水性部位として形成し、この親水性部位に液滴を載置し、この液滴の表面に半導体チップを載置するものである。液滴上に載置された半導体チップは、液滴の表面張力によって自動的に規定の位置及び方向に整列する。   As a circuit manufacturing method, a manufacturing method has been proposed in which a semiconductor chip is arranged on a substrate with high efficiency and high accuracy using a self-organization (self-assembly) function (see Japanese Patent Application Laid-Open No. 2010-245552). In this manufacturing method, a region where a semiconductor chip is arranged on a substrate is formed as a hydrophilic portion, a droplet is placed on the hydrophilic portion, and a semiconductor chip is placed on the surface of the droplet. The semiconductor chip placed on the droplet is automatically aligned in a predetermined position and direction by the surface tension of the droplet.

上述の製造方法は、生産性に限界がある従来のロボットによる機械的な半導体チップの配置手法に比べ、大量の半導体チップを効率よく、かつ精度よく配置することができる。しかし、上記親水性部位を構成する樹脂膜をＣＶＤ（化学蒸着）によって形成しているため、半導体チップが配置される面の平坦性が低く、配置の水平精度が低下するおそれがある。また、基板と半導体チップとの固定が、上記液滴の蒸発のみによるものであるため、半導体チップの固着力が弱い。さらに、固着力を向上させるために、基板と半導体チップとの接合面に接着剤を塗布することも不可能である。   The above-described manufacturing method can efficiently and accurately arrange a large number of semiconductor chips as compared to a conventional mechanical semiconductor chip arrangement method using a robot with limited productivity. However, since the resin film constituting the hydrophilic portion is formed by CVD (chemical vapor deposition), the flatness of the surface on which the semiconductor chip is arranged is low, and the horizontal accuracy of the arrangement may be lowered. In addition, the fixing of the semiconductor chip is weak because the fixing of the substrate and the semiconductor chip is only by evaporation of the droplets. Furthermore, it is impossible to apply an adhesive to the bonding surface between the substrate and the semiconductor chip in order to improve the fixing force.

特開２０１０−２４５４５２号公報JP 2010-245452 A

本発明は、自己組織化機能を用いた回路の製造方法であって、上述のような事情に基づいてなされたものであり、半導体チップを効率よく高い精度で配置でき、かつ基板に容易かつ確実に固定することができる回路の製造方法及び回路を提供することを目的とする。   The present invention is a method of manufacturing a circuit using a self-organizing function, which has been made based on the above-described circumstances, and allows a semiconductor chip to be placed efficiently and accurately, and easily and reliably on a substrate. An object of the present invention is to provide a circuit manufacturing method and a circuit that can be fixed to the circuit.

上記課題を解決するためになされた発明は、
基板の画定部に半導体チップを配置してなる回路の製造方法であって、
基板に感光性接着層を形成する工程と、
上記感光性接着層の選択的露光及び現像により画定部を形成する工程と、
上記画定部の表面に液を載置する工程と、
上記液に上記半導体チップを載置する工程と、
上記液の除去により上記半導体チップを仮接着する工程と
を有することを特徴とする。 The invention made to solve the above problems is
A method of manufacturing a circuit comprising a semiconductor chip arranged on a demarcated portion of a substrate,
Forming a photosensitive adhesive layer on the substrate;
Forming a defining portion by selective exposure and development of the photosensitive adhesive layer;
Placing a liquid on the surface of the demarcating portion;
Placing the semiconductor chip in the liquid;
And a step of temporarily adhering the semiconductor chip by removing the liquid.

本発明の回路は、上記回路の製造方法で製造した回路である。   The circuit of the present invention is a circuit manufactured by the above-described circuit manufacturing method.

以上説明したように、本発明の回路の製造方法は、半導体チップを高い精度で配置でき、かつ基板に容易かつ確実に固定することができる。   As described above, according to the circuit manufacturing method of the present invention, a semiconductor chip can be placed with high accuracy and can be easily and reliably fixed to a substrate.

本発明の一実施形態に係る回路の製造方法を示す模式的説明図である。It is typical explanatory drawing which shows the manufacturing method of the circuit which concerns on one Embodiment of this invention. 図１とは異なる実施形態に係る回路の製造方法を示す模式的説明図である。It is typical explanatory drawing which shows the manufacturing method of the circuit which concerns on embodiment different from FIG.

以下、適宜図面を参照しつつ、当該回路の製造方法の実施形態を詳説する。   Hereinafter, an embodiment of a method for manufacturing the circuit will be described in detail with reference to the drawings as appropriate.

当該回路の製造方法は、基板の画定部に半導体チップを配置してなる回路の製造方法であり、以下の工程を有する。
（１）基板に感光性接着層を形成する接着層形成工程
（２）上記感光性接着層の選択的露光及び現像により画定部を形成する画定部形成工程
（３）上記画定部の表面に液を載置する液載置工程
（４）上記液に上記半導体チップを載置するチップ載置工程
（５）上記液の除去により上記半導体チップを仮接着するチップ仮接着工程 The circuit manufacturing method is a circuit manufacturing method in which a semiconductor chip is arranged on a demarcating portion of a substrate, and includes the following steps.
(1) Adhesive layer forming step for forming a photosensitive adhesive layer on a substrate (2) Defective portion forming step for forming a demarcating portion by selective exposure and development of the photosensitive adhesive layer (3) Liquid on the surface of the demarcating portion (4) Chip mounting step of mounting the semiconductor chip on the liquid (5) Chip temporary bonding step of temporarily bonding the semiconductor chip by removing the liquid

さらに、当該回路の製造方法は、以下の工程を有することが好ましい。
（６）上記画定部に半導体チップを接着するチップ本接着工程
（７）上記半導体チップと上記画定部とを、上記電気的接続手段により電気的接続する
電気的接続工程 Furthermore, the method for manufacturing the circuit preferably includes the following steps.
(6) Chip main adhering step of adhering a semiconductor chip to the demarcating portion (7) Electrical connection step of electrically connecting the semiconductor chip and the demarcating portion by the electric connecting means

当該回路の製造方法は、ＣＶＤを用いずに選択的露光及び現像により画定部を形成することから、化学蒸着などのドライプロセスを用いた方法に比べ、画定部に半導体チップを効率的に高い精度で配置できる。さらに、選択的露光及び現像により画定部を自由に形成できることから、２次元だけでなく、３次元にも半導体チップを配置することができる。また、感光性接着層から形成されてなる画定部は接着性を発現できることから、別のチップ固定方法を用いずにチップを固定することができる。   Since the manufacturing method of the circuit forms the demarcation portion by selective exposure and development without using CVD, the semiconductor chip is efficiently provided in the demarcation portion more efficiently than a method using a dry process such as chemical vapor deposition. Can be arranged. Furthermore, since the defining portion can be freely formed by selective exposure and development, the semiconductor chip can be arranged not only in two dimensions but also in three dimensions. Moreover, since the demarcation part formed from the photosensitive adhesive layer can exhibit adhesiveness, the chip can be fixed without using another chip fixing method.

図１に、当該回路の製造方法の各工程における回路の断面図を示す。   FIG. 1 is a cross-sectional view of a circuit in each step of the circuit manufacturing method.

＜基板＞
当該回路の製造方法で用いる基板１の材質としては、ガラス基板、樹脂基板、シリコンウエハ、半導体基板等を回路の種類に合わせて用いることができる。また、上記基板１は、１又は複数の配線層を有していてもよい。 <Board>
As a material of the substrate 1 used in the method for manufacturing the circuit, a glass substrate, a resin substrate, a silicon wafer, a semiconductor substrate, or the like can be used according to the type of the circuit. The substrate 1 may have one or a plurality of wiring layers.

＜半導体チップ＞
半導体チップ２としては、トランジスタ、発光素子、固体撮像素子、有機半導体、バイオチップ、表示素子、サイリスタ、ＳＯＩ、パワーＭＯＳＥＴ、整流ダイオードなどのパワー半導体素子等の半導体を用いた素子を有するチップがある。この半導体チップ２は、上記基板１に１又は２以上配設される。また、異なる素子を有するチップを基板１上に配設することで、集積回路を構成することができる。 <Semiconductor chip>
The semiconductor chip 2 includes a chip having an element using a semiconductor such as a power semiconductor element such as a transistor, a light emitting element, a solid-state imaging element, an organic semiconductor, a biochip, a display element, a thyristor, an SOI, a power MOSET, and a rectifier diode. . One or more semiconductor chips 2 are arranged on the substrate 1. In addition, an integrated circuit can be configured by disposing chips having different elements on the substrate 1.

半導体チップ２は、電気的接続手段を有してもよい。例えば、半導体チップ２が半田バンプ、画定部３が電極パッドを有する場合、半導体チップ２と基板１とのフリップチップ接続が可能となる。上記電気的接続手段としては、公知のものを適用でき、例えば、電気的接続手段として電極パッド及びワイヤボンディングを適用する手段や、電極パッドの代わりにＳｉ貫通電極を適用する手段がある。   The semiconductor chip 2 may have electrical connection means. For example, when the semiconductor chip 2 has solder bumps and the defining portion 3 has electrode pads, flip chip connection between the semiconductor chip 2 and the substrate 1 is possible. As the electrical connection means, known ones can be applied. For example, there are means for applying an electrode pad and wire bonding as the electrical connection means, and means for applying a Si through electrode instead of the electrode pad.

半導体チップ２のサイズは、用途にあわせて適宜設計することができ、例えば１辺の長さが１ｍｍ以上１００ｍｍ以下、厚みが０．１μｍ以上１００００μｍ以下、好ましくは２０μｍ以上１００μｍ以下とすることができる。   The size of the semiconductor chip 2 can be appropriately designed according to the application. For example, the length of one side is 1 mm to 100 mm and the thickness is 0.1 μm to 10000 μm, preferably 20 μm to 100 μm. .

また、半導体チップ２は親水性の面を有していることが好ましい。親水性を有していることで、半導体チップ２を容易かつ確実に画定部に載置することができる。例えば、公知の親水化処理剤（特開２０１２−０２５８２０号公報、特開２０１２−００７０５３号公報、特開２００９−１４４０８９号公報）により、半導体チップ２の面を親水性とすることができる。   The semiconductor chip 2 preferably has a hydrophilic surface. By having hydrophilicity, the semiconductor chip 2 can be easily and reliably placed on the defining portion. For example, the surface of the semiconductor chip 2 can be made hydrophilic by using a known hydrophilic treatment agent (Japanese Patent Application Laid-Open Nos. 2012-255820, 2012-007053, and 2009-144089).

＜（１）接着層形成工程＞
接着層形成工程においては、図１（ｂ）及び（ｃ）に示すように、上記基板１に感光性接着層４を形成する。この感光性接着層４は、基板１の表面に形成した接着層４ａと、この接着層４ａの表面に形成した親水層４ｂとで構成されている。例えば、接着層４ａは、感光性接着剤で形成し、親水層４ｂは、親水化処理剤で形成することができる。 <(1) Adhesive layer forming step>
In the adhesive layer forming step, a photosensitive adhesive layer 4 is formed on the substrate 1 as shown in FIGS. The photosensitive adhesive layer 4 is composed of an adhesive layer 4a formed on the surface of the substrate 1 and a hydrophilic layer 4b formed on the surface of the adhesive layer 4a. For example, the adhesive layer 4a can be formed of a photosensitive adhesive, and the hydrophilic layer 4b can be formed of a hydrophilic treatment agent.

上記感光性接着剤から形成する接着層４ａは、光を照射した部分が化学的に変化し、現像液に対して不溶化又は可溶化する感光性と、加熱や光により硬化又は軟化する接着性とを有する。上記感光性接着剤としては、例えばポリイミド樹脂前駆体（ポリアミック酸）等の公知の感光性接着剤や、特開２０１０−２５６５０８号公報に開示される樹脂組成物を挙げることができる。   The adhesive layer 4a formed from the photosensitive adhesive has a photosensitivity in which a portion irradiated with light is chemically changed to be insolubilized or solubilized in a developing solution, and an adhesive property that is cured or softened by heating or light. Have As said photosensitive adhesive, well-known photosensitive adhesives, such as a polyimide resin precursor (polyamic acid), and the resin composition disclosed by Unexamined-Japanese-Patent No. 2010-256508 can be mentioned, for example.

上記親水性処理剤から形成する親水層４ｂは、水などの極性を有する流動体に対して密着性（親和性）が高い、つまり、流動体に対する接触角が相対的に小さい。上記親水性処理剤は、例えば、公知の親水化処理剤（特開２０１２−０２５８２０号公報、特開２０１２−００７０５３号公報、特開２００９−１４４０８９号公報）や、酸化チタン等の光触媒を含有した樹脂組成物、水溶性の無機化合物、ポリマー親水性の化学結合又は残基を分子鎖又は側鎖に有する有機化合物、界面活性剤を挙げることができる。   The hydrophilic layer 4b formed from the hydrophilic treatment agent has high adhesion (affinity) to a fluid having polarity such as water, that is, the contact angle with respect to the fluid is relatively small. The hydrophilic treatment agent contains, for example, a known hydrophilic treatment agent (Japanese Patent Laid-Open Nos. 2012-255820, 2012-007053, and 2009-144089) and a photocatalyst such as titanium oxide. Examples thereof include a resin composition, a water-soluble inorganic compound, a polymer hydrophilic chemical bond or an organic compound having a residue in a molecular chain or a side chain, and a surfactant.

親水層４ｂの厚みは、１μｍ以下、好ましくは０．１μｍ以下がよい。親水性が発現できる限度まで厚みが薄い方が、上記チップ本接着工程において、半導体チップ２と画定部３とを良好に接着できることから好ましい。   The thickness of the hydrophilic layer 4b is 1 μm or less, preferably 0.1 μm or less. It is preferable that the thickness is as thin as possible to the extent that hydrophilicity can be expressed because the semiconductor chip 2 and the defining portion 3 can be favorably bonded in the main chip bonding step.

上記感光性接着剤及び上記親水化処理剤の塗布方法は、公知の方法（スピンコート法、スプレー法、スライドコート法、ディップ法、バーコート法、ロールコーター法、スクリーン印刷法、インクジェット法等）を用いることができる。これらの中でもコスト及び表面平坦性の観点から、スピンコート法が好ましい。   Application methods of the photosensitive adhesive and the hydrophilic treatment agent are known methods (spin coating method, spray method, slide coating method, dip method, bar coating method, roll coater method, screen printing method, ink jet method, etc.) Can be used. Among these, the spin coating method is preferable from the viewpoint of cost and surface flatness.

また、上記感光性接着剤又は親水化処理剤を塗布した後に加熱処理をしてもよい。この加熱処理の温度は、使用される感光性接着剤や親水化処理剤の種類等に応じて適宜調整されるが、通常３０℃〜２００℃程度、好ましくは５０℃〜１２０℃であり、加熱時間は、通常０．５分〜６０分程度、好ましくは１分〜１０分である。   Moreover, you may heat-process, after apply | coating the said photosensitive adhesive agent or a hydrophilic treatment agent. The temperature of this heat treatment is appropriately adjusted according to the type of photosensitive adhesive or hydrophilizing agent used, but is usually about 30 ° C to 200 ° C, preferably 50 ° C to 120 ° C. The time is usually about 0.5 to 60 minutes, preferably 1 to 10 minutes.

感光性接着層４の厚みとしては、０．１μｍ以上１，０００μｍ以下が好ましい。感光性接着層４の厚みが上記下限未満の場合、半導体チップ２と基板１との固着力が低下するおそれがある。一方で、感光性接着層４の厚みが上記上限を超える場合、露光が層全体に十分行われずに画定部３が確実に形成されないおそれがある。   The thickness of the photosensitive adhesive layer 4 is preferably 0.1 μm or more and 1,000 μm or less. When the thickness of the photosensitive adhesive layer 4 is less than the above lower limit, the fixing force between the semiconductor chip 2 and the substrate 1 may be reduced. On the other hand, when the thickness of the photosensitive adhesive layer 4 exceeds the above upper limit, the entire layer may not be sufficiently exposed, and the demarcating portion 3 may not be reliably formed.

＜（２）画定部形成工程＞
画定部形成工程は、図１（ｄ）及び（ｅ）に示すように、上記感光性接着層４に対し露光及び現像を行い、親水性の表面を有する画定部３を形成する。この画定部３は、基板１上の半導体チップ２が配置される領域である。各画定部３の上面の面積は、それぞれの画定部３上に配置される半導体チップ２の平面積に略等しい。 <(2) Definition part formation process>
In the defining part forming step, as shown in FIGS. 1D and 1E, the photosensitive adhesive layer 4 is exposed and developed to form the defining part 3 having a hydrophilic surface. The demarcating portion 3 is a region where the semiconductor chip 2 on the substrate 1 is disposed. The area of the upper surface of each defining portion 3 is substantially equal to the plane area of the semiconductor chip 2 disposed on each defining portion 3.

上記画定部形成工程は以下の工程を有する。
（Ａ）フォトマスク６を介して上記感光性接着層４を露光する露光工程
（Ｂ）上記露光された感光性接着層４の現像により画定部３を形成する現像工程 The demarcation portion forming step includes the following steps.
(A) Exposure step of exposing the photosensitive adhesive layer 4 through the photomask 6 (B) Development step of forming the demarcating portion 3 by developing the exposed photosensitive adhesive layer 4

＜（２−Ａ）露光工程＞
露光工程においては、図１（ｄ）に示すように、フォトマスク６を介し、コンタクトアライナー、ステッパー又はスキャナーを用いて、露光光を感光性接着層４に照射する。露光に用いられる露光光としては、感光性接着剤の種類及び／又は画定部３の面積に応じて、紫外線、可視光線等が挙げられ、通常、波長２００〜５００ｎｍの光（例えば、ｉ線（３６５ｎｍ））を用いる。活性光線の照射量は、感光性接着層４中の成分の種類、配合割合、層の厚みなどによって異なるが、露光光にｉ線を使用する場合、露光量は、通常１０〜１５００ｍＪ／ｃｍ２である。 <(2-A) Exposure step>
In the exposure step, as shown in FIG. 1D, exposure light is irradiated onto the photosensitive adhesive layer 4 through a photomask 6 using a contact aligner, a stepper, or a scanner. Examples of the exposure light used for the exposure include ultraviolet rays and visible rays according to the type of the photosensitive adhesive and / or the area of the defining portion 3. Usually, light having a wavelength of 200 to 500 nm (for example, i-line ( 365 nm)). The irradiation amount of actinic rays varies depending on the types of components in the photosensitive adhesive layer 4, the blending ratio, the thickness of the layer, etc., but when i rays are used for exposure light, the exposure amount is usually 10 to 1500 mJ / cm 2. is there.

＜（２−Ｂ）現像工程＞
現像工程では、図１（ｅ）に示すように、上記露光工程で露光された感光性接着層４を現像して画定部３を形成する。この工程で用いられる現像液は、使用される感光性接着層４の種類に応じて適宜選択される。現像液としては、例えばアルカリ性水溶液、有機溶剤を挙げることができる。これらのアルカリ性水溶液には、界面活性剤を添加することもできる。 <(2-B) Development step>
In the development process, as shown in FIG. 1E, the photosensitive adhesive layer 4 exposed in the exposure process is developed to form the demarcating portion 3. The developer used in this step is appropriately selected according to the type of the photosensitive adhesive layer 4 used. Examples of the developer include an alkaline aqueous solution and an organic solvent. A surfactant can be added to these alkaline aqueous solutions.

感光性接着層４を上記現像液で現像した後、必要に応じて、洗浄及び／又は乾燥することによって、画定部３を形成する。なお、図１では、露光により現像液に対して不溶化する感光性接着剤と、画定部３が露光されるフォトマスク６とを用いて画定部３を形成しているが、本発明はこれに限定されるものではなく、露光により可溶化する感光性接着剤と、画定部３以外の部分が露光されるフォトマスクとを用いて画定部３を形成してもよい。   After the photosensitive adhesive layer 4 is developed with the developer, the demarcating portion 3 is formed by washing and / or drying as necessary. In FIG. 1, the demarcating portion 3 is formed using a photosensitive adhesive that is insolubilized in the developer by exposure and a photomask 6 through which the demarcating portion 3 is exposed. The definition part 3 may be formed using a photosensitive adhesive that is solubilized by exposure and a photomask that is exposed to a part other than the definition part 3.

＜（３）液載置工程＞
液載置工程は、液５を上記画定部３の表面に載置する。この液５は図１（ｆ）に示すように液滴状にしてもよい。液５は、画定部３の表面以外の部分へ付着した液滴よりもその付着量が多く、画定部３の表面に載置されればよい。画定部３は、感光性接着層４から形成されており、画定部３の表面は画定部３の表面以外の部分に比べ突起しているため、画定部３の表面に選択的に液５を載置することができる。また、画定部３が親水層４ｂを有するため、より選択的に画定部３の表面に液５を載置することができる。 <(3) Liquid placement process>
In the liquid placing step, the liquid 5 is placed on the surface of the defining portion 3. The liquid 5 may be in the form of droplets as shown in FIG. The liquid 5 may be deposited on the surface of the demarcating unit 3 because the amount of the liquid 5 is larger than that of the liquid droplets adhering to portions other than the surface of the demarcating unit 3. The defining portion 3 is formed of a photosensitive adhesive layer 4, and the surface of the defining portion 3 protrudes as compared with a portion other than the surface of the defining portion 3, so that the liquid 5 is selectively applied to the surface of the defining portion 3. Can be placed. Moreover, since the demarcation part 3 has the hydrophilic layer 4b, the liquid 5 can be mounted on the surface of the demarcation part 3 more selectively.

上記液５は通常水を含む液を用いる。また、フラックス成分を含有している水溶液を用いることもできる。フラックス成分によって、後述の電気的接続工程において、電気的接続手段に用いられる金属の酸化を抑制し、金属の酸化膜を除去することができる。   The liquid 5 is usually a liquid containing water. An aqueous solution containing a flux component can also be used. The flux component can suppress the oxidation of the metal used for the electrical connection means and remove the metal oxide film in the electrical connection process described later.

上記液５の画定部３表面への載置方法としては、特に限定されるものではなく、例えば水溶液を貯留した槽に基板１を浸漬させて取り出す方法、基板１上に水溶液を噴霧する方法、各画定部３に水溶液を塗布する方法等を挙げることができる。いずれの方法を用いた場合も、感光性接着層４の選択的露光及び現像により均一な表面を有する画定部３を形成するため、画定部３の表面全体を均一に覆うように液５が形成された状態を得ることができる。   The mounting method of the liquid 5 on the surface of the demarcating portion 3 is not particularly limited. For example, a method of immersing the substrate 1 in a tank storing the aqueous solution and taking it out, a method of spraying the aqueous solution on the substrate 1, The method etc. which apply | coat aqueous solution to each demarcation part 3 can be mentioned. In any case, the liquid 5 is formed so as to uniformly cover the entire surface of the defining portion 3 in order to form the defining portion 3 having a uniform surface by selective exposure and development of the photosensitive adhesive layer 4. The obtained state can be obtained.

＜（４）チップ載置工程＞
チップ載置工程においては、図１（ｇ）に示すように、上記液載置工程で画定部３に載置された液５の表面に半導体チップ２を載置する。液５の表面に載置された半導体チップ２は、液５の表面張力によって、画定部３と重なるように整列する。 <(4) Chip placement process>
In the chip placement step, as shown in FIG. 1G, the semiconductor chip 2 is placed on the surface of the liquid 5 placed on the demarcating portion 3 in the liquid placement step. The semiconductor chip 2 placed on the surface of the liquid 5 is aligned so as to overlap the defining portion 3 due to the surface tension of the liquid 5.

半導体チップ２を液５の表面に載置する方法は、例えば各画定部３の上方の一定高度から半導体チップ２を落下させる方法、半導体チップ２を把持して液５に接触させた後に開放する方法等がある。また、半導体チップ２は、同時に複数載置してもよい。   The method of placing the semiconductor chip 2 on the surface of the liquid 5 is, for example, a method in which the semiconductor chip 2 is dropped from a certain height above each demarcating portion 3, or the semiconductor chip 2 is released after being held in contact with the liquid 5. There are methods. A plurality of semiconductor chips 2 may be placed simultaneously.

＜（５）チップ仮接着工程＞
チップ仮接着工程は、図１（ｈ）に示すように、上記液５を除去することで半導体チップ２を基板１に仮接着する。液５を除去する方法としては、例えば加熱することで気化する方法、減圧することで気化する方法及びその両方を用いる方法がある。本発明の回路の製造方法においては、画定部３の表面全体を均一に覆うように液５が形成できるため、効率よくかつ精度よく画定部３に半導体チップ２を仮接着することができる。 <(5) Chip temporary bonding process>
In the chip temporary bonding step, the semiconductor chip 2 is temporarily bonded to the substrate 1 by removing the liquid 5 as shown in FIG. As a method for removing the liquid 5, there are, for example, a method of vaporizing by heating, a method of vaporizing by reducing pressure, and a method of using both. In the circuit manufacturing method of the present invention, since the liquid 5 can be formed so as to uniformly cover the entire surface of the defining part 3, the semiconductor chip 2 can be temporarily bonded to the defining part 3 efficiently and accurately.

＜（６）チップ本接着工程＞
チップ本接着工程は、画定部３を加熱や紫外線などの光により硬化又は軟化することにより半導体チップ２を画定部３に接着させる。加熱温度は、通常１００℃〜３００℃程度であり、加熱時間は、通常０．５分〜４時間程度である。チップ本接着工程では、チップを加圧して圧着してもよい。加圧の条件は、通常、０．０５〜９ＭＰａの圧力を付加することにより行えばよい。 <(6) Chip main bonding process>
In the chip main bonding step, the semiconductor chip 2 is bonded to the demarcating portion 3 by curing or softening the demarcating portion 3 with light such as heating or ultraviolet rays. The heating temperature is usually about 100 ° C to 300 ° C, and the heating time is usually about 0.5 minutes to 4 hours. In the chip main bonding step, the chip may be pressed and pressure bonded. The pressurizing condition is usually performed by applying a pressure of 0.05 to 9 MPa.

＜（７）電気的接続工程＞
電気的接続工程は、半導体チップ２及び画定部３に電気的接続手段を有している場合、半導体チップ２と画定部３とを、上記電気的接続手段により電気的接続する工程である。半導体チップ２及び画定部３に用いる電気的接続手段としては、公知のものを適用でき、例えば電極パッド、ワイヤボンディング、Ｓｉ貫通電極、半田バンプ、半田ボール等がある。これらの電気的接続手段は、公知の方法、例えばフォトファブリケーションにより形成できる。 <(7) Electrical connection process>
The electrical connection step is a step of electrically connecting the semiconductor chip 2 and the defining portion 3 by the electrical connecting means when the semiconductor chip 2 and the defining portion 3 have electrical connecting means. As the electrical connection means used for the semiconductor chip 2 and the demarcating portion 3, known devices can be applied, and examples thereof include electrode pads, wire bonding, Si through electrodes, solder bumps, solder balls and the like. These electrical connection means can be formed by a known method, for example, photofabrication.

＜回路＞
当該製造方法で得られる回路は、上述のように、半導体チップ２が基板１上の所定の位置に精密に配置され、かつ接着剤により固着されるため、高い品質を有する。また、上記半導体チップ２の配置及び固定が容易に行えるため、当該製造方法で得られる回路は、生産コストを低く抑えることができる。 <Circuit>
As described above, the circuit obtained by the manufacturing method has high quality because the semiconductor chip 2 is precisely arranged at a predetermined position on the substrate 1 and fixed by an adhesive. Further, since the semiconductor chip 2 can be easily arranged and fixed, the circuit obtained by the manufacturing method can keep the production cost low.

＜多層回路＞
上記（１）接着層形成工程、（２）画定部形成工程、（３）液載置工程、（４）チップ載置工程、及び（５）チップ仮接着工程を少なくとも経た基板１に、再度これらの工程を繰り返す（これらの工程を含む製造フローを複数回行う）ことによって、半導体チップ２が三次元的に配置された多層回路を容易かつ確実に製造することができる。なお、上記工程に加えて（６）チップ本接着工程及び／又は（７）電気的接続工程を経た基板を上記基板１として、半導体チップ２が三次元的に配置された多層回路を形成してもよい。又は、基板１や半導体チップ２が有する素子等の劣化を防ぐために、全ての半導体チップ２の仮接着後に（６）チップ本接着工程及び／又は（７）電気的接続工程をまとめて実施してもよい。 <Multilayer circuit>
These are again applied to the substrate 1 that has undergone at least the (1) adhesive layer forming step, (2) defining portion forming step, (3) liquid placing step, (4) chip placing step, and (5) chip temporary bonding step. By repeating the above steps (a manufacturing flow including these steps is performed a plurality of times), a multilayer circuit in which the semiconductor chips 2 are three-dimensionally arranged can be easily and reliably manufactured. In addition to the above steps, a substrate that has undergone (6) chip main bonding step and / or (7) electrical connection step is used as substrate 1 to form a multilayer circuit in which semiconductor chips 2 are three-dimensionally arranged. Also good. Or, in order to prevent deterioration of the elements and the like of the substrate 1 and the semiconductor chip 2, (6) the chip main bonding process and / or (7) the electrical connection process are collectively performed after all the semiconductor chips 2 are temporarily bonded. Also good.

［その他の実施形態］
本発明の製造方法で得られる回路は、上述の実施形態に限定されるものではなく、以下のような実施形態とすることもできる。 [Other Embodiments]
The circuit obtained by the manufacturing method of the present invention is not limited to the above-described embodiment, and may be the following embodiment.

上記図１の実施形態では、感光性接着層４を感光性接着剤から形成される接着層４ａと親水化処理剤から形成される親水層４ｂとから構成したが、本発明はこれに限定されず、図２に示した回路の製造方法のように、接着層のみを有する単層構造の感光性接着層４を用いて回路を製造してもよい。つまり、図２の回路の製造方法では、接着層からなる感光性接着層４を基板１に積層後（図２（ａ）、（ｂ））、この感光性接着層４を選択的露光及び現象することで画定部３を形成する（図２（ｃ）、（ｄ））。次に、この画定部３の表面に液５を載置し（図２（ｅ））、さらにこの液５に半導体チップ２を載置する（図２（ｆ））。その後、液５を除去することで半導体チップ２を画定部３に仮接着する（図２（ｇ））。半導体チップ２の仮接着後、上記図１の実施形態と同様にチップ本接着工程及び電気的接続工程を行うことで回路を得ることができる。   In the embodiment of FIG. 1 described above, the photosensitive adhesive layer 4 is composed of an adhesive layer 4a formed from a photosensitive adhesive and a hydrophilic layer 4b formed from a hydrophilizing agent, but the present invention is not limited to this. Instead, the circuit may be manufactured using the photosensitive adhesive layer 4 having a single-layer structure having only the adhesive layer, as in the circuit manufacturing method shown in FIG. That is, in the circuit manufacturing method shown in FIG. 2, after the photosensitive adhesive layer 4 made of an adhesive layer is laminated on the substrate 1 (FIGS. 2A and 2B), the photosensitive adhesive layer 4 is selectively exposed and phenomenon. By doing so, the demarcating portion 3 is formed (FIGS. 2C and 2D). Next, the liquid 5 is placed on the surface of the defining portion 3 (FIG. 2E), and the semiconductor chip 2 is further placed on the liquid 5 (FIG. 2F). Thereafter, the semiconductor chip 2 is temporarily bonded to the demarcating portion 3 by removing the liquid 5 (FIG. 2G). After the semiconductor chip 2 is temporarily bonded, a circuit can be obtained by performing the chip main bonding process and the electrical connection process in the same manner as the embodiment of FIG.

以下、実施例を挙げて本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。   EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated more concretely, this invention is not limited to these.

［実施例１］
シリコンウェハ上に、樹脂組成物ＳＵ−８ ３０００（商品名、化薬マイクロケム株式会社製）をスピンコートし、感光性接着層を形成した。この感光性接着層を選択的露光及び現像し、高さ１０μｍ、縦１０００μｍ、横１０００μｍの立方体形状の画定部を形成した。この画定部表面に水を載置し、さらに、この水の上に半導体チップを載置した。次いで、水を除去することにより、画定部上に半導体チップを仮接着した。このとき、半導体チップは画定部上に高精度に配置できていた。次いで、画定部上に半導体チップを仮接着したシリコンウェハを加熱し、半導体チップをシリコンウェハに接着することで、実施例１の回路を得た。 [Example 1]
A resin composition SU-83000 (trade name, manufactured by Kayaku Microchem Co., Ltd.) was spin-coated on a silicon wafer to form a photosensitive adhesive layer. This photosensitive adhesive layer was selectively exposed and developed to form a cube-shaped demarcating portion having a height of 10 μm, a length of 1000 μm, and a width of 1000 μm. Water was placed on the surface of the defining portion, and a semiconductor chip was placed on the water. Next, the semiconductor chip was temporarily bonded onto the defining portion by removing water. At this time, the semiconductor chip could be arranged on the demarcating portion with high accuracy. Next, the circuit of Example 1 was obtained by heating the silicon wafer on which the semiconductor chip was temporarily bonded onto the defining portion, and bonding the semiconductor chip to the silicon wafer.

以上のように、本発明の回路の製造方法は、半導体チップを高い精度で配置でき、かつ基板に容易かつ確実に固定することができる。   As described above, according to the circuit manufacturing method of the present invention, the semiconductor chip can be arranged with high accuracy and can be easily and reliably fixed to the substrate.

１ 基板
２ 半導体チップ
３ 画定部
４ 感光性接着層
４ａ 接着層
４ｂ 親水層
５ 液
６ フォトマスク DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor chip 3 Definition part 4 Photosensitive adhesive layer 4a Adhesive layer 4b Hydrophilic layer 5 Liquid 6 Photomask

Claims (8)

基板の画定部に半導体チップを配置してなる回路の製造方法であって、
基板に感光性接着層を形成する工程と、
上記感光性接着層の選択的露光及び現像により画定部を形成する工程と、
上記画定部の表面に液を載置する工程と、
上記液に上記半導体チップを載置する工程と、
上記液の除去により上記半導体チップを仮接着する工程と
を有することを特徴とする回路の製造方法。 A method of manufacturing a circuit comprising a semiconductor chip arranged on a demarcated portion of a substrate,
Forming a photosensitive adhesive layer on the substrate;
Forming a defining portion by selective exposure and development of the photosensitive adhesive layer;
Placing a liquid on the surface of the demarcating portion;
Placing the semiconductor chip in the liquid;
And a step of temporarily adhering the semiconductor chip by removing the liquid. 上記感光性接着層が、親水性層を有する請求項１に記載の回路の製造方法。   The method for producing a circuit according to claim 1, wherein the photosensitive adhesive layer has a hydrophilic layer. 上記液がフラックス成分を含む請求項１又は請求項２に記載の回路の製造方法。   The circuit manufacturing method according to claim 1, wherein the liquid contains a flux component. 上記画定部に上記半導体チップを接着する工程をさらに有する請求項１、請求項２又は請求項３に記載の回路の製造方法。   The circuit manufacturing method according to claim 1, further comprising a step of bonding the semiconductor chip to the demarcating portion. 上記半導体チップ及び上記画定部が電気的接続手段を有し、
上記半導体チップと上記画定部とを、上記電気的接続手段により電気的に接続する工程
を有する請求項１から請求項４のいずれか１項に記載の回路の製造方法。 The semiconductor chip and the demarcating portion have electrical connection means;
The circuit manufacturing method according to claim 1, further comprising a step of electrically connecting the semiconductor chip and the demarcating portion by the electrical connecting means. 上記半導体チップが、親水性の面を有する請求項１から請求項５のいずれか１項に記載の回路の製造方法。   The circuit manufacturing method according to claim 1, wherein the semiconductor chip has a hydrophilic surface. 上記各工程を含む製造フローを複数回行う請求項１から請求項６のいずれか１項に記載の回路の製造方法。   The method for manufacturing a circuit according to claim 1, wherein a manufacturing flow including each of the steps is performed a plurality of times. 請求項１から請求項７のいずれか１項に記載の回路の製造方法で製造した回路。
A circuit manufactured by the circuit manufacturing method according to claim 1.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252543A (en) * 1999-02-25 2000-09-14 Matsushita Electric Ind Co Ltd Joint body and manufacture thereof
JP2003515456A (en) * 1999-12-03 2003-05-07 フライズ・メタルズ・インコーポレーテッド・ドゥーイング・ビジネス・アズ・アルファ・メタルズ・インコーポレーテッド Flux for soldering
JP2004327908A (en) * 2003-04-28 2004-11-18 Ricoh Co Ltd Method and structure for bonding electro-optical devices
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JP2009144089A (en) * 2007-12-17 2009-07-02 Nippon Paint Co Ltd Hydrophilized coating agent
JP2010245452A (en) * 2009-04-09 2010-10-28 Tokyo Electron Ltd Collectively holding tray and three-dimensionally integrated circuit manufacturing apparatus
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