JP2014011776A - Receiver unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver unit capable of suppressing a delay generated in a signal transmitted through a transmission line.SOLUTION: A first impedance control section 12, upon detecting that a waveform of a signal transmitted through a transmission line 2 has changed in a rise direction, increases an input impedance only for a prescribed period and then returns the impedance to an ordinary value. A second impedance control section 13, after the first impedance control section 12 comes into action, decreases an input impedance only for a prescribed period and then returns the impedance to an ordinary value.

Description

  The present invention relates to a receiving apparatus that performs control so as to change an input impedance of a receiving circuit that receives a signal transmitted via a transmission line.

  The transmission line used for communication has a longer line length, and the capacity increases as the number of communication nodes connected to the transmission line increases. And the waveform of the signal transmitted in the transmission line causes a delay in the rise time and the fall time when the capacity incidental to the transmission line increases. Therefore, in order to establish communication, it is necessary to limit the line length and the number of connection nodes, or to insert a repeater in the middle of the transmission line to suppress signal delay.

  However, if a repeater is introduced in the transmission line, the cost is increased accordingly. Therefore, it is desirable if some measures can be taken on the receiving node side instead. As a related technique, for example, Patent Document 1 discloses a receiving apparatus having a function of suppressing waveform distortion in accordance with a state in which a signal waveform actually changes on the receiving side.

JP 2009-232499 A

However, in Patent Document 1, the purpose is to suppress overshoot and undershoot of a signal waveform, that is, reflection of a signal exclusively, and to suppress a delay time that occurs at the rising and falling of a signal waveform is quite complete. Not paying attention.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a receiving apparatus capable of suppressing a delay generated for a signal transmitted in a transmission line.

  According to the receiving device of claim 1, when the first impedance control means detects that the waveform of the signal transmitted via the transmission line has changed in the rising direction, the first impedance control means increases the input impedance for a certain period. Return to normal value. By this action, the rising edge of the waveform of the received signal changes more rapidly. Then, after the first impedance control means operates, the second impedance control means decreases the input impedance for a certain period and then returns to the normal value. By this action, the change in the falling edge of the waveform of the received signal becomes steeper. Therefore, it is possible to suppress dullness of the signal waveform as a whole, and it is possible to stably perform communication performed via the transmission line without using a repeater or the like.

The figure which is a 1st Example and shows the structure of a receiving node about the principal part Flow chart showing reception processing The figure which shows the simulation result of the received signal waveform Diagram showing network configuration used for simulation (A) is a diagram corresponding to FIG. 1 showing the second embodiment, (b) is a diagram showing a state in which the resistance value of the resistance value switching circuit changes. 3A is a diagram corresponding to FIG. 3, and FIG. 3B is a diagram simulating a change in current flowing through the receiving node corresponding to FIG. FIG. 6 equivalent diagram when applied to a receiving node connected to a branch line of a transmission line FIG. 5A equivalent view showing the third embodiment. 6 equivalent diagram FIG. 8 equivalent view showing the fourth embodiment FIG. 8 equivalent view showing the fifth embodiment FIG. 8 equivalent view showing the sixth embodiment The figure which is a 7th Example and shows the application example using the auxiliary driver of 5th Example

(First embodiment)
A first embodiment in which the present invention is applied to a communication network that transmits a differential signal by a pair of signal lines will be described below. Here, as an example, application to a CAN (Controller Area Network) is assumed. In FIG. 4, a communication network 1 includes a plurality of communication nodes connected via a main line 3 and a branch line 4 that form a transmission line 2 composed of twisted pair lines. A transmission node 5 is connected to the left end of the main line 3 in the figure, a reception node 6 is connected to the right end, and a HUB 7 is inserted in the middle of the main line 3. The line length of the main line 3a connecting between the transmitting node 5 and the HUB 7 and the line length of the main line 3b connecting between the HUB 7 and the receiving node 6 are both 16.5 m.

  Further, 22 branch lines 4 are connected to the HUB 7, and a receiving node 8 is connected to one end of each, and the line length of each of the branch lines 4 is 2 m. And the waveform at the time of receiving the differential signal transmitted from the transmission node 5 with the reception node 6 (reception apparatus) was simulated on the conditions described below.

  In FIG. 1, a differential amplifier 11 constituting a part of a receiving circuit is connected between a pair of communication buses 3H (Bus_high) and 3L (Bus_low) on a main line 3b. A signal corresponding to the differential voltage of 3H and 3L is output to a circuit of the next stage (not shown). A first impedance control unit 12 (first impedance control unit) and a second impedance control unit 13 (second impedance control unit) are arranged on the input side of the differential amplifier 11 and connected between them. A terminating resistor 14 and a capacitor 15 are connected between the communication buses 3H and 3L. Here, the resistance value of the termination resistor 14 is, for example, 120Ω. The capacitor 15 simulates the capacitance (for example, 100 pF) that the receiving node 6 has.

  The first impedance control unit 12 includes a switch control unit (voltage detection unit) 16 connected between the communication buses 3H and 3L, and a resistance value switching unit 17 inserted on the communication bus 3H side. The resistance value switching unit 17 is a parallel circuit of a resistance element 17R and a normally closed switch circuit 17S, and ON / OFF control of the switch circuit 17S is performed by a control signal output from the switch control unit 16. The resistance value of the resistance element 17R is, for example, 1 kΩ.

  The second impedance control unit 13 includes a switch control unit 18 connected between the communication buses 3H and 3L and a resistance value switching unit 19. The resistance value switching unit 19 is a series circuit of a normally open type switch circuit 19S and a resistance element 19R, and ON / OFF control of the switch circuit 19S is performed by a control signal output from the switch control unit 18. Note that the switch control units 16 and 18 are composed of, for example, a combination of a differential amplifier circuit and a comparator. The switch control signal output from the switch control unit 16 is also input to the switch control unit 18.

  Next, the operation of this embodiment will be described. In FIG. 2, the switch control unit 16 of the first impedance control unit 12 monitors the state of signals (differential voltages) transmitted through the communication buses 3H and 3L (S1). Since the waveform of the received signal rises when transitioning from recessive in the non-drive state to dominant in the drive state, it is possible to detect that the waveform has started to change in the rise direction by monitoring the differential voltage. When the start of the rise is detected (S2: YES), the switch control unit 16 outputs a switch OFF signal (control signal) to the resistance value switching unit 17 (S3).

  Then, since the switch circuit 17S of the resistance value switching unit 17 is turned off, the input impedance of the reception node 6 increases by the resistance value of the resistance element 17R (S4; high impedance). Subsequently, the switch control unit 16 outputs a switch ON signal to the resistance value switching unit 17 when the received differential signal becomes equal to or higher than a threshold value (for example, 1.5 V) for determining the dominant level (S5: YES) ( S6). Then, since the switch circuit 17S is turned on and the resistance element 17R is short-circuited, the input impedance of the reception node 6 is reduced (S7).

  Next, the control content on the second impedance control unit 13 side is entered. Here, it is assumed that the switch control signal output from the switch control unit 16 turns off the switch circuit 17S when the switch control signal is at a high level, for example. At this time, by changing the switch circuit 17S from OFF → ON → OFF by the switch control signal, the falling edge of the switch control signal is given, so that the switch control unit 18 is enabled and starts the following operation. .

The switch control unit 18 observes the state of the reception differential signal at the dominant level (S8), and if it is equal to or greater than the same threshold value as step S5 at that time (S9: YES), it waits for the standby time to elapse (S10). . Here, the standby time is set to be 0 s or longer and within a 1-bit data transmission time (for example, 2 μs for 500 kbps) at the CAN signal transmission rate. If the standby time has elapsed (YES), a switch ON signal is output to the resistance value switching unit 19 (S11). Then, the resistance element 19R is connected between the communication buses 3H and 3L, and the input impedance of the reception node 6 is lowered (S12).
Even if the waiting time has not elapsed in step S10 (that is, the waiting time is 0 s), the received differential signal maintains the dominant level at least at the sampling point at which the receiving circuit determines the data value “1, 0”. There is no problem if you do.

  Here, even if the received differential signal still shows a dominant level and the input impedance is lowered before the signal waveform shows a fall, the received data is determined to be “1, 0” in step S10. Since the sampling point has passed, there is no effect on data reception. When the signal waveform actually changes so as to show a falling edge, the falling edge becomes steeper because the input impedance is lowered. Then, the switch control unit 18 outputs a switch OFF signal to the resistance value switching unit 19 when the received differential signal is equal to or lower than a threshold (for example, 0.5 V) for determining the recessive level (S13: YES) (S14). . Then, the resistance element 19R is disconnected and connected between the communication buses 3H and 3L, and the input impedance of the reception node 6 increases (S15).

  As shown in FIG. 3, as compared with the case where the first and second impedance control units 12 and 13 are not provided, both the rising and falling slopes of the received data waveform become steeper, resulting in a signal transmission time of about 200 ns. It has been shortened. In the figure, the processing timing in the flowchart of FIG. 2 and the OFF and ON timings of the switch circuits 17S and 19S are shown together.

  As described above, according to this embodiment, when the first impedance control unit 12 detects that the waveform of the signal transmitted via the transmission line 2 has changed in the rising direction, the first impedance control unit 12 increases the input impedance for a certain period. After that, the second impedance control unit 13 reduces the input impedance for a certain period after the first impedance control unit 12 is actuated, and then restores the normal value. Therefore, it is possible to suppress dullness of the signal waveform as a whole, and it is possible to stably perform communication performed via the transmission line without using a repeater or the like.

  The first impedance control unit 12 includes a resistance value switching unit 17 composed of a parallel circuit of a resistance element 17R and a normally closed switch circuit 17S, and the switch control unit 16 detects a differential voltage that is a received signal. When the differential voltage exceeds a predetermined threshold value, the switch circuit 17S is switched from on to off to increase the input impedance for a certain period. Therefore, with a simple configuration, the input impedance can be increased during the period when the received signal waveform rises.

  The second impedance control unit 13 includes a resistance value switching unit 19 that is a series circuit of a normally open switch circuit 19S and a resistance element 19R when connected in parallel to the differential amplifier 11, and includes an input impedance. When the first impedance control unit 12 operates, the switch circuit 19S is switched from OFF to ON within a period during which 1-bit data is transmitted. Therefore, with a simple configuration, the input impedance can be reduced during the period when the received signal waveform falls.

(Second embodiment)
The reception node 21 (reception device) illustrated in FIG. 5A is configured by adding a current detection unit 22 and a control logic unit 23 to the reception node 6. Further, the switch control unit 16 of the first embodiment is used as the voltage detection unit 24, and these constitute the switch control unit 25. The current detection unit 22 is inserted into the communication bus 3H, and is configured by, for example, a current transformer. When the current flowing through the communication bus 3H exceeds a predetermined threshold (for example, 0.3 A), the switch circuit 17S is connected to the control logic unit 23. The OFF signal is output. As shown in FIG. 5B, if the current flowing through the communication bus 3H is equal to or less than the threshold value, the resistance value of the resistance value switching circuit 17 is 1 mΩ corresponding to the on-resistance of the switch circuit 17S. When the current flowing through the communication bus 3H exceeds the threshold value, the switch circuit 17S is turned off, so that the resistance value becomes 1 kΩ.

  2 is performed by the voltage detection unit 24 as in the first embodiment. That is, the current detection unit 22 outputs a set signal for causing the control logic unit 23 to output an off signal of the switch circuit 17S, and outputs a reset signal to the voltage detection unit 24 control logic unit 23. The resistance value switching unit 17 and the switch control unit 25 constitute a first impedance control unit 26 (first impedance control means).

  FIG. 6 shows the result of simulating only the operation of the first impedance control unit 26. As shown in FIG. 6A, the rising of the received data waveform is compared with the case without the first impedance control unit 26 (broken line). The slope of is steep. FIG. 6B is a simulation of the current flowing through the reception node 21, and the current value is greatly reduced by providing the first impedance control unit 26. FIG. 7 shows a case where the present invention is applied to a reception node connected to the branch line 4 (the termination resistor 14 is not connected). Similarly, the rising slope of the reception data waveform is steep.

  As described above, according to the second embodiment, the first impedance control unit 26 includes the current detection unit 22 that detects the current flowing through the transmission line 2, and when the current exceeds a predetermined threshold, the input impedance is constant. In this case, the same effect as in the first embodiment can be obtained because the period is increased.

(Third embodiment)
The reception node 31 (reception device) shown in FIG. 8 is obtained by deleting the voltage detection unit 24 from the reception node 21 of the second embodiment and arranging a control logic unit 32 instead of the control logic unit 23. The control logic unit 32 includes, for example, a timer (which may be of either digital or analog configuration), and when the set signal is given from the current detection unit 22, the set signal is passed after a predetermined time (for example, 0.3 μs). Is configured to automatically reset. The current detection unit 22 and the control logic unit 32 constitute a switch control unit 33, and the resistance value switching unit 17 and the switch control unit 33 constitute a first impedance control unit 34. The waveform of the reception operation signal and the current flowing through the reception node 31 are as shown in FIG. 9, and the rising slope of the reception data waveform is steep. In the case of the third embodiment configured as described above, the same effect as that of the second embodiment can be obtained.

(Fourth embodiment)
The reception node (reception device) 41 shown in FIG. 10 deletes the resistance value switching unit 17 from the reception node 31 of the third embodiment, and between the communication bus 3H and the capacitor 15, a resistance element 42R and a normally closed type. A resistance value switching circuit 42 composed of a parallel circuit of the switch circuit 42S is connected. The switch control unit 33 controls on / off of the switch circuit 42S. In this case, the resistance value switching unit 42 and the switch control unit 33 constitute a first impedance control unit 43 (first impedance control means).

  Next, the operation of the fourth embodiment will be described. The switch control unit 33 operates in the same manner as in the third embodiment, and the switch circuit 42S of the resistance value switching circuit 42 is turned off only during a period when a high level control signal is applied. Therefore, during this period, the resistance element 42R is connected in series with the capacitor 15, and the input impedance of the reception node 41 temporarily increases, so that the rising of the reception signal waveform is steep. In the case of the fourth embodiment configured as described above, the same effect as that of the third embodiment can be obtained.

(5th Example)
In the first to fourth embodiments, the termination circuit is shown by the termination resistor 14 alone. However, in the reception node 44 shown in FIG. 11, the series circuit of the termination resistors 14a and 14b, their bases, and the ground are more practical. And a capacitor 14c connected between them. The series resistance value of the termination resistors 14a and 14b is 120Ω. The resistance value switching circuit 42 of the fourth embodiment is connected in series with the termination circuit 14, and these constitute a first impedance control unit 45.

  Also in the case of the fifth embodiment, the switch control unit 33 operates in the same manner as in the third and fourth embodiments, and the switch circuit 42S of the resistance value switching circuit 42 is only in a period during which a high level control signal is given. Turn off. During this period, the termination resistance value including the termination circuit 14 increases by the amount of the resistance element 42R, so that the input impedance of the reception node 44 temporarily increases, and the rising of the reception signal waveform acts steeply. . In the case of the fifth embodiment configured as described above, the same effect as in the third and fourth embodiments can be obtained.

(Sixth embodiment)
The receiving node 51 shown in FIG. 12 is obtained by deleting the resistance value switching unit 17 from the receiving node 6 of the first embodiment and connecting an auxiliary driver 52 (auxiliary driving circuit) between the communication buses 3H and 3L. The switch control unit 16 is an auxiliary driver control unit 53 (auxiliary drive circuit) having the same function but different name. The auxiliary driver 52 has the same function as the driver provided in the transmission node, drives the communication buses 3H and 3L, and outputs a differential signal. The auxiliary driver control unit 53 outputs a trigger signal (in the first embodiment). When the same control signal output to the switch circuit 17S is applied, the communication buses 3H and 3L are driven to the dominant level.

  That is, the auxiliary driver 52 itself outputs a dominant level signal at the timing when another transmission node (not shown) tries to drive the communication buses 3H and 3L to the dominant level. As a result, the ability to drive the communication buses 3H and 3L is assisted, so that the rising of the received signal waveform can be made steep.

(Seventh embodiment)
The auxiliary driver 52 and the auxiliary driver control unit 53 of the sixth embodiment do not necessarily have to be individually incorporated in each reception node. For example, as shown in FIG. 13, for example, one transmission node 62 is provided in a common transmission line 61. And a plurality of receiving nodes 63a, 63b,... Are connected. At this time, only one auxiliary driver node 64 including the auxiliary driver 52 and the auxiliary driver control unit 53 may be connected to the transmission line 61.

  And each receiving node 63a, 63b, ... incorporates the 2nd impedance control part 13 separately. In this case, the timing at which the second impedance control unit 13 performs the impedance control for the falling edge of the received signal waveform is, for example, according to the output period of 1-bit data using the output signal of the differential amplifier 11 as a trigger (dominant level). The drive period) is configured to be determined autonomously. A communication system can also be configured in this way.

The present invention is not limited to the above-described embodiments, and the following modifications or expansions are possible.
A differential amplifier constituting a receiving circuit may be used as the voltage detection unit. Then, the function of the switch control unit 18 may be provided in a part that performs bit determination of received data in the receiving circuit.
You may comprise the switch control part of a 1st, 2nd impedance control part as an integral control part.
The timing at which the second impedance control unit performs impedance control for the falling edge of the received signal waveform may be changed as appropriate within a range that is less than the output period of 1-bit data.
You may apply to communication protocols other than CAN. Further, the present invention is not limited to transmitting differential signals, and may be applied to a receiving device connected to a single-ended transmission line.

  In the drawing, 2 is a transmission line, 3H and 3L are communication buses (transmission lines), 6 is a receiving node (receiving device), 11 is a differential amplifier (receiving circuit), and 12 is a first impedance control unit (first impedance control). Means), 13 is a second impedance control section (second impedance control means), 14 is a termination resistor, 16 is a switch control section (voltage detection section), 17R is a resistance element, 17S is a switch circuit, 18 is a switch control section, Reference numeral 19S denotes a switch circuit, and 19R denotes a resistance element.

Claims (9)

A receiving circuit (11) for receiving a signal which is transmitted through a transmission line (2, 3H, 3L) and changes to a binary level of high and low;
When detecting that the waveform of the signal has changed in the rising direction, first impedance control means (12, 26, 43, 45) for increasing the input impedance for a certain period and then returning it to a normal value;
A receiving apparatus comprising: second impedance control means (13) for reducing the input impedance for a certain period after the first impedance control means is actuated and then returning the input impedance to the normal value.   The second impedance control means includes a series circuit of a resistance element (19R) connected in parallel to the receiving circuit and a normally open switch circuit (19S), and when the input impedance is reduced, The receiving device according to claim 1, wherein the switch circuit is switched from off to on.   The first impedance control means (12) includes a voltage detection unit (16) for detecting the voltage of the signal, and increases the input impedance for a certain period when the voltage exceeds a predetermined threshold. The receiving device according to claim 1 or 2.   The first impedance control means (26) includes a current detection unit (22) for detecting a current flowing through the transmission line, and increases the input impedance for a certain period when the current exceeds a predetermined threshold. The receiving apparatus according to claim 1 or 2, characterized in that:   The first impedance control means (12, 26) includes a parallel circuit of a resistance element (17R) inserted into the transmission line (3H) and a normally closed switch circuit (17S) to increase the input impedance. 5. The receiving device according to claim 1, wherein when the switching is performed, the switch circuit is switched from on to off. 6.   The first impedance control means (43) is a parallel circuit of a resistance element (42R) and a normally closed switch circuit (42S) connected in series to a capacitance component (15) built in the receiving circuit. 42. The receiving apparatus according to claim 1, wherein the switch circuit is switched from on to off when the input impedance is increased. The receiving circuit is a node located at the end of the transmission line;
The first impedance control means (45) is a parallel circuit of a resistance element (42R) and a normally closed switch circuit (42S) connected in series to a termination circuit (14) connected to the receiving circuit. 42. The receiving apparatus according to claim 1, wherein the switch circuit is switched from on to off when the input impedance is increased.   The said 2nd impedance control means reduces the said input impedance within the period when 1 bit data are transmitted after a 1st impedance control means act | operates, The one of Claim 1 thru | or 7 characterized by the above-mentioned. Receiver. A receiving circuit (11) for receiving a signal transmitted through a transmission line (2) and changing to a binary level of high and low;
An auxiliary drive circuit (52) for transmitting a signal when connected to the transmission line and detecting that the waveform of the signal has changed in a rising direction;
A receiving apparatus comprising: impedance control means (13) for reducing the input impedance for a predetermined period after the auxiliary driving circuit transmits the signal and then returning the input impedance to the normal value.

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