JP2014007518A - Noise reduction system of analog-digital converter and noise reduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog-digital converter capable of achieving satisfactory S/N.SOLUTION: The noise reduction system comprises: an analog-digital converter ADC1 of an oversampling type having a feedback circuit 13; a dither generation circuit 17 that gives a dither signal to the analog-digital converter ADC1; and a dither setting section 25 that obtains frequency information of an operation clock CLK2 in a noise source circuit 20 to set a dither signal in a dither generation circuit 17 according to the frequency information. The dither generation circuit 17 can change the frequency of tone generated by the analog-digital converter ADC1 by adjusting the setting of the dither signal.

Description

  The present invention relates to an oversampling analog-digital converter noise reduction system and a noise reduction method.

  In a general oversampling analog-to-digital converter, when the analog input signal is non-input or weak input, the ratio of the output signal of the quantizer between “H” and “L” is 1: 1, and alternately It becomes the state of the continuous pattern that appears in. When a minute DC component ΔV or the like is superimposed on the analog input signal of this analog-to-digital converter, the above one-to-one continuous pattern breaks down and tone noise (hereinafter referred to as a tone) is output to the quantizer. There is a problem that the S / N (Signal / Noise) of the digital output signal of the analog-to-digital converter is remarkably deteriorated.

  In a conventional noise reduction system for an analog-digital converter, a dither signal is used in order to prevent the S / N deterioration. For example, by adding the dither signal to the analog input signal, the tone frequency appearing at the output of the quantizer can be out of the signal band. The S / N of the digital output signal of the analog-to-digital converter can be improved by attenuating the tone outside the signal band with a digital filter. Here, for example, a DC offset or a clock pulse with a small amplitude is used as the dither signal.

  Further, in order to prevent the saturation of the modulator at the time of strong input when a dither signal is applied, according to countermeasures for inputting the dither signal to the reference voltage side of the quantizer (see Patent Document 1) and the output of the quantizer Therefore, a countermeasure for changing the intensity of the dither signal that is a clock pulse (see Patent Document 2) has been implemented.

Japanese Patent No. 4648996 Japanese Patent No. 4644289

  In recent years, integration of LSI functions has progressed, and a plurality of analog-digital converters and digital-analog converters tend to be built into LSIs. When each analog-digital converter (digital-analog converter) uses a clock having a different frequency, a plurality of clock components exist in a single LSI, and periodic noise (hereinafter referred to as CLK noise). To be described). Further, in order to reduce the number of LSI terminals and the area, the power supply terminals and the ground terminals in a plurality of circuits are often shared, and the reference voltage is often shared. Further, for example, in order to improve the accuracy of the circuit, the current of the circuit may be increased or the frequency of the clock used for the circuit may be increased.

  As a result, for each component of the analog-digital converter, the CLK noise generated in other circuits affects the digital output signal of the analog-digital converter via the power supply, ground, and reference voltage. Wrap around with sufficient strength. For this reason, for example, when an analog-digital converter is used for audio signal processing, there is a problem that noise noise is generated due to CLK noise.

  In the conventional noise reduction system, a good S / N is ensured for a tone caused by a minute DC component ΔV and the like, but the S / N may be deteriorated for the CLK noise as described above. is there.

  In view of the above points, an object of the present invention is to provide a noise reduction system and a noise reduction method for an analog-to-digital converter that can obtain a good S / N even when receiving external CLK noise. To do.

  In the first aspect of the present invention, the noise reduction system of the analog-to-digital converter is an oversampling type, an analog-to-digital converter having a feedback circuit, and a dither signal to the analog-to-digital converter. And a dither generation circuit configured to be able to adjust the setting of the dither signal so as to change the frequency of a tone generated in the analog-to-digital converter, and noise that gives periodic noise to the analog-to-digital converter A dither setting unit that obtains frequency information about the frequency of the operation clock of the source circuit and sets the dither signal in the dither generation circuit according to the frequency information;

  According to the first aspect, the dither setting unit sets the dither signal in the dither generation circuit according to the frequency information of the operation clock of the noise source circuit. The dither generation circuit receives the setting from the dither setting unit and supplies the adjusted dither signal to the analog-digital converter. As a result, the frequency of the tone is changed, and the frequency of the modulation signal generated from the tone and the periodic noise is changed. Then, for example, by setting the dither signal in the dither generation circuit so that the frequency of the modulation signal generated from the tone and the periodic noise deviates from the signal band according to the frequency information, the S / N of the analog-digital converter is set. Can be avoided. That is, good S / N can be obtained.

  In a second aspect of the present invention, an analog-to-digital converter noise reduction system includes an oversampling analog-to-digital converter and an operation clock of a noise source circuit that applies periodic noise to the analog-to-digital converter. And a sampling clock setting unit for setting the frequency of the sampling clock of the analog-to-digital converter in accordance with the frequency information.

  According to the second aspect, the sampling clock setting unit sets (adjusts) the frequency of the sampling clock of the analog-digital converter according to the frequency information of the operation clock of the noise source circuit. As a result, the frequency of the alias signal generated from the sampling clock and the periodic noise changes. Then, for example, by setting the frequency of the sampling clock so that the frequency of the alias signal deviates from the signal band according to the frequency information, it is possible to avoid the deterioration of the S / N of the analog-digital converter. That is, good S / N can be obtained.

  In a third aspect of the present invention, the noise reduction system for an analog-digital converter is an oversampling type, and includes an analog-digital converter having a feedback circuit, and is periodic with respect to the analog-digital converter. The frequency of the tone generated by the analog-to-digital converter is controlled in accordance with the frequency of the operation clock of the noise source circuit that gives noise.

  According to the third aspect, the frequency of the modulation signal generated from the tone and the periodic noise is changed by controlling the frequency of the tone generated by the analog-digital converter in accordance with the frequency of the operation clock. Thereby, the deterioration of the S / N of the analog-digital converter can be avoided. That is, good S / N can be obtained.

  According to a fourth aspect of the present invention, there is provided an oversampling type analog-to-digital converter noise reduction method comprising: a noise source circuit that applies periodic noise to the analog-to-digital converter; The frequency setting related to the frequency of the clock is obtained, and in accordance with the frequency information, the dither signal is set so as to change the frequency of the tone generated in the analog-digital converter, and the signal setting step is set. And a signal applying step for supplying the dither signal to the analog-to-digital converter.

  According to the fourth aspect, the dither signal corresponding to the frequency information of the operation clock of the noise source circuit obtained in the signal setting step is set and supplied to the analog-digital converter. Thereby, since the frequency of the modulation signal generated from the tone and the periodic noise changes, it is possible to avoid the deterioration of the S / N of the analog-digital converter. That is, good S / N can be obtained.

  According to the present invention, a good S / N can be obtained in an analog-to-digital converter by switching the sampling clock frequency and the dither signal setting in accordance with the frequency of the external CLK noise.

It is a figure which shows the structural example of the noise reduction system of the analog-digital converter which concerns on 1st Embodiment. In FIG. 1, it is a figure which shows an example of the spectrum of the signal before and after switching of a sampling frequency. In FIG. 1, it is a figure which shows the other example of the spectrum of the signal before and behind switching of a sampling frequency. It is a figure which shows the structural example of the noise reduction system of the analog-digital converter which concerns on 2nd Embodiment. In FIG. 4, it is a figure which shows an example of the spectrum of the signal before and after the change of the setting of a dither signal. It is a figure which shows the example of a setting of a dither signal. It is a figure which shows the structural example of a frequency calculator and a switching controller. It is a figure which shows the structural example of the noise reduction system of an analog / digital converter in the case of implement | achieving a frequency calculator and a switching controller with software. It is a flowchart which shows an example of the process by a frequency calculator and a switching controller. It is a flowchart which shows an example of the process by a frequency calculator and a switching controller. It is a figure which shows the structural example of the noise reduction system of the analog-digital converter which concerns on 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a noise reduction system for an analog-digital converter according to the first embodiment. In FIG. 1, the analog-digital converter ADC1 includes an adder / subtractor 10, an integrator 11, a quantizer 12, a feedback circuit 13, and a digital filter 14.

  The adder / subtracter 10 subtracts an output signal of a feedback circuit 13 described later from the analog input signal AIN. The integrator 11 integrates the output signal of the adder / subtracter 10.

  The quantizer 12 receives the signal integrated by the integrator 11, performs sampling with the sampling clock CLK1 output from the first PLL 15, and quantizes the sampled data. The digital signal output from the quantizer 12 is input to the feedback circuit 13 and the digital filter 14.

  The feedback circuit 13 multiplies (modulates) the output signal of the quantizer 12 and the reference voltage output from the reference voltage source circuit 16 to convert it into an analog signal and outputs it. The digital filter 14 attenuates a frequency component equal to or higher than the signal band of the analog input signal AIN to generate a digital output signal DOUT.

  Here, it is assumed that the CLK noise is generated from the noise source circuit 20, and the noise source circuit 20 is operated by the operation clock CLK2 (frequency is fn) output from the second PLL 21 as the PLL. To do. For example, when the noise source circuit 20 is an analog-digital converter or a digital-analog converter, CLK2 is the sampling clock.

  In some cases, the frequency fn of the operation clock CLK2 of the noise source circuit 20 is changed, that is, the frequency fn of the operation clock CLK2 output from the second PLL 21 is changed. In this case, the frequency of the CLK noise generated from the noise source circuit 20 varies. For example, when the noise source circuit 20 is a video signal processing circuit, the frequency fn of the operation clock CLK2 may be changed according to the video format.

  The sampling clock setting unit 24 includes a frequency calculator 22 and a switching controller 23.

  The frequency calculator 22 receives the frequency setting information from the second PLL 21 or the operation clock CLK2, and calculates the frequency fn of the operation clock CLK2 of the noise source circuit 20.

  The switching controller 23 controls the first PLL 15 so that the sampling frequency of the sampling clock CLK1 is switched according to the frequency fn of the operation clock CLK2 calculated by the frequency calculator 22.

[Operation of noise reduction system (1)]
FIG. 2 is a diagram illustrating an example of a signal spectrum before and after switching of the sampling frequency in FIG. Here, the sampling frequency of the sampling clock CLK1 is fsa and fsb, and the frequency of the CLK noise, that is, the frequency of the operation clock CLK2 is fn. The signal band of the analog input signal AIN is assumed to be fbw.

  2, (a), (b), and (c) are states in which the frequency fn of the operation clock CLK2 is within the frequency range of (multiple of the sampling frequency fsa of the sampling clock CLK1) ± (signal band fbw). (D), (e), and (f) show the spectrum of the signal after switching the sampling frequency of the sampling clock CLK1 from fsa to fsb. Show.

  (A) and (d) are the spectrum of the input signal of the quantizer 12, (b) and (e) are the spectrum of the output signal of the quantizer 12, and (c) and (f) are the digital output signal DOUT. The spectrum of is shown.

  As shown in FIG. 2A, it is assumed that CLK noise propagated via the power supply or the reference voltage Vb is superimposed on the input signal of the quantizer 12. In the quantizer 12, when such a signal on which CLK noise is superimposed is sampled by the sampling clock CLK1, an alias signal folded back to a frequency of fsa / 2 or less is generated. Assuming that the frequency of the alias signal is fpa, fpa has a value represented by the following (Equation 1).

  Here, m is an integer closest to fn / fsa. | A | means the absolute value of A.

  When the frequency fn and the frequency of (fsa × m) are close, as shown in FIG. 2B, the frequency fpa of the alias signal and the signal band fbw may have the following relationship (Equation 2).

  At this time, as shown in FIG. 2C, the alias signal of the digital output signal DOUT after passing through the digital filter 14 is not attenuated, and as a result, the S / N deteriorates.

  In order to prevent this S / N deterioration, the sampling frequency fsa is switched to the sampling frequency fsb when there is a relationship of (Expression 2) between the frequency fpa of the alias signal and the signal band fbw. Specifically, when the frequency fn of the operation clock CLK2 satisfies the following (Equation 3), the sampling frequency fsa is switched to the sampling frequency fsb.

  At this time, the sampling frequency fsb after switching is set to satisfy one of the following (Equation 4).

  Here, mb is an integer closest to fn / fsb. Note that mb may be the same as m.

  When (Expression 4) is converted into an expression having fsb as the left side, the following (Expression 5) is obtained.

  2D, 2E, and 2F show the spectrum of the signal after the sampling frequency of the sampling clock CLK1 is switched from fsa to fsb that satisfies the above (Equation 5). As shown in FIG. 2E, the frequency fpb (= | fsb × m−fn |) of the alias signal after switching the sampling frequency is higher than the signal band fbw. That is, the frequency fpb of the alias signal is out of the signal band fbw. Thereby, as shown in FIG. 2 (f), in the digital output signal DOUT after passing through the digital filter 14, the signal component of the frequency fpb is sufficiently attenuated, and as a result, the S / N does not deteriorate.

  In the above [Noise reduction system operation (1)], an oversampling analog-digital converter having a feedback circuit has been described. However, an oversampling analog-digital converter having no feedback circuit (not shown). The same effect can be obtained in.

[Operation of noise reduction system (2)]
FIG. 3 is a diagram showing another example of the spectrum of the signal before and after the switching of the sampling frequency in FIG. Here, fsa, fsb, fn, and fbw are the same as those in FIG. Further, let fta and ftb be frequencies of tones generated at the output of the quantizer 12, that is, fsa / 2 or less generated in the analog-to-digital converter ADC1.

  3, (a) to (d) show that the frequency fn of the operation clock CLK2 is (integer multiple of the sampling frequency fsa of the sampling clock CLK1) + (the frequency fta of the tone generated from the quantizer 12) ± (signal band fbw) ) Shows the spectrum of the signal in the frequency range, and (e) to (h) show the spectrum of the signal after switching the sampling frequency of the sampling clock CLK1 from fsa to fsb.

  Further, (a) and (e) are spectra of the reference voltage Vb input from the reference voltage source circuit 16 to the feedback circuit 13, and (b), (c), (f) and (g) are those of the quantizer 12. Output spectra, (d) and (h), show the spectrum of the digital output signal DOUT. In addition, about each of (a)-(h), the spectrum of the voltage and signal similar to FIG. 3 shall be shown also in FIG.

  As shown in FIG. 3A, it is assumed that CLK noise is superimposed on the reference voltage Vb. Further, as shown in FIG. 3B, it is assumed that a tone of fsa / 2 or less is generated at the output of the quantizer 12. Therefore, the output where the tone is generated is input to the feedback circuit 13.

  In the feedback circuit 13, the operation clock CLK 2 superimposed on the reference voltage output from the reference voltage source circuit 16 and the tone generated at the output of the quantizer 12 are modulated. In the quantizer 12, since this modulated signal is fed back and sampled by the sampling clock CLK1, a modulated signal of fsa / 2 or less is generated at the output (FIG. 3 (c)).

  When the frequency of this modulation signal is fma, the frequency fma is expressed by the following (formula 6).

  Here, n is an integer, and fma is set to a value that satisfies the condition of 0 ≦ fma <fsa / 2.

  When the frequency of (fn−fta) is close to the frequency of (fsa × n), the frequency fma of the modulation signal and the signal band fbw may have the following relationship (Equation 7).

  At this time, as shown in FIG. 3D, the modulation signal of the digital output signal DOUT after passing through the digital filter 14 is not attenuated, and as a result, the S / N deteriorates.

  In order to prevent this S / N deterioration, the sampling frequency fsa is switched to the sampling frequency fsb when there is a relationship of (Equation 7) between the frequency fma of the modulation signal and the signal band fbw. Specifically, when the frequency fn of the operation clock CLK2 satisfies the following (Equation 8), the sampling frequency fsa is switched to the sampling frequency fsb.

  At this time, the sampling frequency fsb after switching is set to satisfy one of the following (Equation 9).

  Here, nb is an integer, and is set to a value such that the frequency fmb of the modulation signal after switching the sampling frequency satisfies 0 ≦ fmb <fsb / 2. Note that nb may be the same value as n. Further, since the tone frequency changes at the same ratio when the sampling frequency of the sampling clock CLK1 changes, it is assumed here to be ftb.

  FIGS. 3E to 3H show the spectrum of the signal after the sampling frequency of the sampling clock CLK1 is switched from fsa to fsb satisfying the above (Equation 9). As shown in FIG. 3G, the frequency fmb (= | fn−ftb−fsb × nb |) of the modulation signal is higher than the signal band fbw. That is, the frequency fmb of the modulation signal is out of the signal band fbw. As a result, as shown in FIG. 3H, in the digital output signal DOUT after passing through the digital filter 14, the frequency fmb component of the modulation signal is sufficiently attenuated, and as a result, the S / N does not deteriorate.

  As described above, when the sampling frequency of the sampling clock and the frequency of the operation clock are in the state as shown in FIG. 2A or FIG. 3A, the sampling frequency is switched, while FIG. In a state such as 3 (e), deterioration of the S / N can be avoided by maintaining the current sampling frequency.

  According to this embodiment, since the sampling frequency is moved instead of reducing the signal strength of the alias signal or modulation signal in the signal band, the alias signal is within the signal band even if the strength of the CLK noise increases. No modulation signal is generated and S / N is not deteriorated. Therefore, the noise source circuit 20, the power supply terminal, the ground terminal, and the reference voltage can be shared, and the cost of the LSI can be reduced.

  In the present embodiment, only one tone of fsa / 2 or less is described, but there may actually be a plurality of tones. In this case, for example, the same effect can be obtained by switching the sampling frequency for the tones having a predetermined intensity or higher so that the modulation signals resulting from those tones do not enter the signal band. In addition, the sampling frequency may be switched so that those modulated signals do not enter the signal band for all tones.

(Second Embodiment)
In the first embodiment, an example in which the sampling frequency of the sampling clock CLK1 is switched has been described. However, for example, when the clock of the first PLL 15 that supplies the sampling clock CLK1 is used in another circuit, it may be difficult to switch the sampling frequency of the sampling clock CLK1. In the second embodiment, an example in which good S / N is obtained without switching the frequency of the sampling clock will be described.

  FIG. 4 is a diagram illustrating a configuration example of a noise reduction system for an analog-digital converter according to the second embodiment. 4, the same reference numerals are given to the same components as those in FIG. 1, and detailed description thereof is omitted here.

  Compared with FIG. 1, the difference is that a dither generation circuit 17 that supplies a dither signal to the adder / subtractor 10 is provided, and a dither setting unit 25 is provided instead of the sampling clock setting unit 24. Here, the dither setting unit 25 includes a frequency calculator 22 and a switching controller 23. In FIG. 4, the switching controller 23 sets the dither signal in the dither generation circuit 17 according to the frequency fn of the operation clock CLK2 calculated by the frequency calculator 22. The adder / subtracter 10 subtracts the output signal of the feedback circuit 13 from the analog input signal AIN and adds the dither signal.

  The dither generation circuit 17 switches the setting of the dither signal based on the setting signal from the switching controller 23. For example, the dither generation circuit 17 has a plurality of settable dither signals, and selects and outputs a dither signal based on the set signal. The tone generated at the output of the quantizer 12 is determined according to the transfer function of the analog-digital converter ADC1 and the set dither signal.

  Although the dither generation circuit 17 has a plurality of settable dither signals and selects a dither signal based on the setting signal, the present invention is not limited to this. For example, the dither generation circuit 17 may perform calculation based on the setting signal and output a dither signal adjusted based on the calculation. Depending on the dither signal setting, multiple tones may occur.

[Operation of noise reduction system]
FIG. 5 is a diagram illustrating an example of a spectrum of a signal before and after switching of dither signal settings in FIG. Here, fsa, fn, fbw, fta, ftb, and n are the same as those in FIG.

  5A to 5D, the frequency fn of the operation clock CLK2 is (integer multiple of the sampling frequency fsa of the sampling clock CLK1) + (the frequency fta of the tone generated from the quantizer 12) ± (signal band fbw) ) Shows the spectrum of the signal in the frequency range, and (e) to (h) show the spectrum of the signal after switching the setting of the dither signal and switching the frequency of the tone from fta to ftb. .

  In FIG. 5 (a), as in FIG. 3 (a), it is assumed that the CLK noise propagated via the power supply or the reference voltage Vb is superimposed on the input signal of the quantizer 12. Similarly to FIG. 3B, it is assumed that a tone of fsa / 2 or less is generated at the output of the quantizer 12, and the signal is input to the feedback circuit 13 (FIG. 5B). .

  Then, the quantizer 12 generates the modulation signal having the frequency fma shown in (Equation 6) as in FIG. 3C (FIG. 5C).

  When the frequencies of (fn−fta) and (fsa × m) are close, that is, when the frequency fma of the modulation signal and the signal band fbw satisfy the relationship of (Equation 7), as shown in FIG. Even in the digital output signal DOUT after passing through the digital filter 14, the modulation signal is not attenuated, and as a result, the S / N deteriorates.

  In order to prevent the deterioration of the S / N, when there is a relationship of (Expression 7) between the frequency fma of the modulation signal and the signal band fbw, the setting of the dither signal is switched to change the tone frequency from fta to ftb. Move. Specifically, when the frequency fn of the operation clock CLK2 satisfies (Equation 8), the setting of the dither signal is switched to move the tone frequency from fta to ftb.

  At this time, the frequency ftb of the tone after switching the setting of the dither signal satisfies either one of the following (Equation 10).

  Here, nb is an integer, and is set to a value such that the frequency fmb of the modulation signal after switching the sampling frequency satisfies 0 ≦ fmb <fsa / 2. Note that nb may be the same value as n.

  FIGS. 5E to 5H show the spectrum of the signal after the tone frequency is switched from fta to ftb satisfying (Equation 10). As shown in FIG. 5G, the frequency fmb (= | fn−ftb−fsa × nb |) of the modulation signal is higher than the signal band fbw. That is, the frequency fmb of the modulation signal is out of the signal band fbw. As a result, as shown in FIG. 5H, in the digital output signal DOUT after passing through the digital filter 14, the component of the frequency fmb of the modulation signal is sufficiently attenuated, and as a result, the S / N does not deteriorate.

  In FIG. 4, a buffer is provided between the reference voltage source circuit 16 and the feedback circuit 13, and it is also conceivable that CLK noise wraps around from the power source and ground of this buffer. Even in such a case, a good S / N can be obtained by the noise reduction system of the present embodiment.

[Dither signal setting]
FIG. 6 is a diagram showing an example of setting the dither signal. FIG. 6A shows an example in which the dither signal is a minute DC voltage, and the voltage value is switched when the setting of the dither signal is switched. Specifically, the voltage value of the dither signal (DC voltage) is increased or decreased according to the moving direction of the tone frequency (high frequency side or low frequency side). FIGS. 6B, 6C, and 6D show examples in which the dither signal is a clock signal with a minute amplitude. In FIG. 6B, when switching the setting of the dither signal, the amplitude is switched. Specifically, the amplitude of the dither signal (clock signal) is increased or decreased according to the moving direction of the tone frequency. In FIG. 6C, when switching the setting of the dither signal, the frequency is switched. Specifically, the frequency of the dither signal (clock signal) is increased or decreased according to the moving direction of the tone frequency. In FIG. 6D, the duty is switched when the setting of the dither signal is switched. Specifically, the duty ratio of the dither signal (clock signal) is increased or decreased according to the moving direction of the tone frequency. In addition, you may set combining FIG.6 (b)-(d). By setting such a dither signal, the tone frequency can be changed.

  In FIG. 4, the dither signal is added by the first stage input of the analog-to-digital converter ADC1, that is, the adder / subtractor 10. However, it may be added to the input of the quantizer 12, the reference voltage side of the quantizer 12, or the like. Absent. In the case of a high-order analog-digital converter, a dither signal may be added to the input of the second-stage integrator.

  Also, the setting of the dither signal for switching the tone frequency varies depending on the order of the analog-digital converter and the specific circuit configuration. Therefore, the setting of the dither signal is not limited to the example of FIG. 6, and other modes may be used as long as the tone frequency can be switched by the setting of the dither signal.

  The frequency calculator 22 and the switching controller 23 in FIGS. 1 and 4 can be realized by either hardware or software. Below, the example is shown.

[Frequency calculator and switching controller (hardware)]
FIG. 7 is a diagram showing an example in which the frequency calculator 22 and the switching controller 23 in FIG. 4 are all realized by hardware. By mounting this hardware on the same LSI as the analog-digital converter ADC1 and the noise source circuit 20, the dither signal is automatically set according to the frequency information, and the frequency of the modulation signal generated from the tone and the periodic noise Can be changed.

  In FIG. 7, the frequency calculator 22 includes a remainder calculator 30, a tone calculator 31, and a subtracter 32. Further, the switching controller 23 includes a signal band discriminator 33 and a dither switch 34.

  The remainder calculator 30 receives the sampling clock CLK1 (frequency is fs) and the operation clock CLK2, calculates a remainder value of (fn ÷ fs), and outputs it.

  The subtractor 32 obtains the difference between the remainder value (fn ÷ fs) that is the output of the remainder calculator 30 and the tone frequency ft indicated by the tone calculator 31 described later. This obtained difference corresponds to the frequency fma of the modulation signal shown in (Equation 6).

  The signal band discriminator 33 discriminates whether or not the output frequency of the subtracter 32 is within the signal band fbw. The dither switch 34 receives the discrimination result from the signal band discriminator 33. When the output frequency of the subtracter 32 is within the signal band, the dither switch 34 switches the setting of the dither signal of the dither generation circuit 17, while when the output frequency of the subtractor 32 is outside the signal band, the dither switch The unit 34 maintains the setting of the dither signal of the dither generation circuit 17.

  The tone calculator 31 receives the setting result of the dither signal from the dither switch 34 and outputs a fixed value corresponding to the setting result from the fixed values indicating the tone frequency ft held in advance to the subtractor 32. .

[Frequency calculator and switching controller (software)]
FIG. 8 is a conceptual diagram of hardware and software configurations including the analog-digital converter ADC1 and the noise source circuit 20 when the frequency calculator 22 and the switching controller 23 in FIG. 4 are realized by software.

  The software can read the setting information of the second PLL 21 necessary for obtaining the frequency fn of the operation clock CLK2 and the current setting of the dither signal in the dither generation circuit 17 from the register. In addition, the optimum setting value of the dither signal in the dither generation circuit 17 of the analog-digital converter ADC1 can be written in the register of the dither generation circuit 17. It is assumed that the setting information of the first PLL 15 is held in advance by software. However, the setting information of the first PLL 15 may be stored in a register in hardware, and the register may be read from software. Note that the register is assumed to be held by each circuit, but the present invention is not limited to this. For example, the register may be shared with another circuit.

  FIG. 9 and FIG. 10 are flowcharts showing processes performed by the frequency calculator 22 and the switching controller 23. FIG. 9 is an overall flowchart, and FIG. 10 is a flowchart showing details of step S5 in FIG.

  In step S1, it is determined whether or not to enable switching of dither signal settings. When switching is enabled, the process proceeds to step S2, while when switching is disabled, the process ends. For example, when the analog-digital converter ADC1 and the noise source circuit 20 are not operating, the switching is invalidated.

  In step S2, information on the operation clock CLK2 of the second PLL 21 is read from the register. The information is, for example, a frequency division ratio of the second PLL 21.

  In step S3, the frequency fn of the operation clock CLK2 is calculated from the information of the operation clock CLK2 read in step S2.

  In step S4, the current setting of the dither signal in the dither generation circuit 17 is read from the register, and the current tone frequency ft is confirmed. Specifically, for example, since the tone frequency in each setting of the dither signal can be known in advance at the time of design, the tone frequency ft can be confirmed from the current setting of the dither signal.

  In step S5, it is determined whether or not interference occurs from the frequency fn of the operation clock CLK2 calculated in step S3 and the tone frequency ft confirmed in step S4. If “interfering”, the process proceeds to step S6. If “not interfering”, the process ends and the current setting of the dither signal is maintained.

  Details of the determination as to whether or not interference occurs in step S5 of FIG. 9 will be described with reference to FIG. Here, it is assumed that the order of the operation clock CLK2 is N and the order is taken into account up to Nmax which is the maximum value of the order.

  In step S51, N = 1 is set.

  In step S52, a frequency fn2 obtained by converting the frequency fn of the operation clock CLK2 to a frequency equal to or less than fs / 2 is calculated. Specifically, it is calculated using the following (Formula 11).

  Here, (A mod B) in (Equation 11) represents a remainder value of (A ÷ B).

  In step S53, it is determined whether or not the frequency fn2 falls within the frequency range of (tone frequency ft) ± (signal band fbw). When the frequency fn2 is in the frequency range of (ft−fbw) to (ft + fbw), it is determined that “interfere”. On the other hand, if the frequency fn2 is outside the frequency range of (ft−fbw) to (ft + fbw), the number of N is incremented by “+1” in step S54, and N> Nmax is determined in step S55. If N ≦ Nmax, the process returns to step S52, and the determination in step S53 is performed again. The above flow is repeated until N = Nmax. When N> Nmax is satisfied in step S55, it is determined that “no interference”.

  When there are a plurality of tones, it is determined in step S53 whether or not the frequency fn2 is within the frequency range of (ft−fbw) to (ft + fbw) for all the frequencies ft of all tones. If it is, it is determined that “interfere”.

  In step S6, the setting of the dither signal is changed from the current state, and the process ends. Here, the frequency of the tone that does not interfere is estimated from the frequency fn of the operation clock CLK2 and the frequency ft of the tone, and the dither signal is set so as to be the frequency of the estimated tone. Specifically, the frequency ft of the tone estimated in step S6 satisfies either one of the following (formula 12) in all N.

  Here, when (Expression 12) is converted using (Expression 11), the following (Expression 13) and (Expression 14) are obtained.

  For example, when there are a plurality of noise source circuits 20, in steps S2 and S3, all the frequencies fn of the operation clock CLK2 that becomes a noise source are calculated. At this time, in the determination of whether or not to “interfer” in step S5, the operation is repeatedly performed from the primary component (N = 1) to the harmonic (N = Nmax) of all the operation clocks CLK2, and when all do not interfere, It is determined that there is no interference. Then, the estimation of the frequency ft of the non-interfering tone in step S6 is set to a frequency ft that satisfies N = 1 to N = Nmax of all the frequencies fn.

  9 and 10 are executed at an event when the frequency fn of the operation clock CLK2 is changed, for example, at the time of start-up and when the format of the analog input signal AIN is switched. For example, when there is a possibility that the frequency fn of the operation clock CLK2 may change at any time, the flows of FIGS. 9 and 10 may be executed at regular intervals, such as every 100 ms.

  1, FIG. 4 and FIG. 8, the operation clock CLK2 uses the output from the second PLL 21, but the clock of an oscillator such as a crystal oscillator or the output clock from another LSI can also be used. Good.

  Further, when the frequency calculator 22 is realized by hardware, it is not limited to the frequency calculation using the operation clock CLK2 itself as shown in the example of FIG. For example, a method of using a PLL frequency division ratio as described in the implementation example of the software in FIG. 8 may be used. When the generation source of the operation clock CLK2 is a voltage controlled oscillator, the frequency fn is calculated from the voltage or the like. Is possible. Further, a noise frequency detection circuit may be provided in the power supply or the reference voltage, and the frequency fn may be calculated from the output.

  The noise source circuit 20 is mainly assumed to be an analog-digital converter or a digital-analog converter. In particular, when the input / output of a set device is close, such as an analog / digital converter for audio and an analog / digital converter for video, it tends to be placed close to the LSI, and shares the power supply, ground terminal, and reference voltage. This can reduce the cost of the LSI. However, when this sharing is performed, the clock component of the noise source circuit 20 is easily superimposed on the power supply, ground, and reference voltage of the analog-digital converter ADC1. In such a case, changing the frequency of the tone, that is, the frequency of the modulation signal by switching the sampling frequency or dither signal in the first and second embodiments is more effective.

  For example, when the noise source circuit 20 is a video analog-digital converter, the sampling frequency of the video analog-digital converter is determined by the video format detected by the input video signal and the identification signal and the frequency of the horizontal synchronization signal. The frequency division ratio of the second PLL 21 is determined based on the determined sampling frequency. That is, the frequency calculator 22 and the switching controller 23 can switch the setting of the dither signal by calculating the sampling frequency of the video analog-digital converter by reading the setting information of the second PLL 21 as the frequency information. . Note that the dither signal setting may be switched according to the detected video format.

  In the first and second embodiments, the delta-sigma modulation type analog-digital converter has been described. However, the analog-digital converter is not limited to the delta-sigma modulation type, and other analog-digital converters are the same. It is. For example, even in a delta modulation type analog-digital converter having a feedback circuit, there is a circuit that feeds back the output of the quantizer and adds it to the input of the analog-digital converter. The feedback circuit (DAC) uses the tone and the reference voltage. The CLK noise superimposed on is easily modulated. Therefore, also in the delta modulation type analog-digital converter, the frequency of the modulation signal can be out of the signal band by moving the tone frequency by switching the sampling frequency and the dither signal.

(Third embodiment)
FIG. 11 is a diagram illustrating a configuration example of a noise reduction system for an analog-digital converter according to the third embodiment. In FIG. 11, the same components as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  As compared with FIG. 4, the difference is that an output level adjustment circuit 18 is provided between the analog-digital converter ADC1 and the digital output signal DOUT.

  The output level adjustment circuit 18 receives the output of the digital filter 14 of the analog-to-digital converter ADC1, adjusts the level of this output based on the setting of the dither signal from the switching controller 23, and outputs it as a digital output signal DOUT. For example, when the dither signal is switched in the form as shown in FIGS. 6A to 6D, switching noise may occur in the output of the analog-digital converter ADC1. Specifically, for example, when the analog input signal AIN is an audio signal, when the DC voltage is switched as shown in FIG. 6A, the DC offset voltage, which is the voltage difference before and after switching, is output. May be heard as sound. Therefore, at the time of such switching, the output level adjusting circuit 18 can prevent the sound due to the switching noise from being output by reducing or turning off the output level of the digital filter 14. For example, the output level adjustment circuit 18 controls the level of the output of the digital filter 14 for a period of several μsec to several msec at the time of switching. In other periods, the output level adjustment circuit 18 outputs the output of the digital filter 14 as the digital output signal DOUT without controlling the output level.

  In the present embodiment, an example in which the analog input signal is an audio signal has been described. However, the present invention is not limited to this, and another analog input signal may be used.

  In this embodiment, the example in which the output level adjustment circuit 18 is applied to the noise reduction system of FIG. 4 has been described. However, the same effect can be obtained even if the output level adjustment circuit 18 is applied to the noise reduction system of FIG. .

  Further, the embodiments can be used in combination. For example, the sampling frequency switching in the first embodiment and the dither signal setting switching in the second embodiment may be used in combination.

  In each of the above embodiments, the example in which the frequency of the alias signal or the frequency of the modulation signal of the external CLK noise and the tone is moved out of the signal band has been described, but the present invention is not limited to the movement out of the signal band. Even within the signal band, for example, the alias signal and the modulation signal may be moved to a frequency near the boundary inside and outside the signal band to attenuate the frequency component near the boundary. Also, for example, when there are frequency components with a small amount of information contained in the signal band or frequency components with low importance as a signal, the above alias signal or modulation signal is moved to a frequency near these frequency components. Then, the shifted frequency component may be attenuated by a band pass filter or the like to attenuate the alias signal and the modulation signal.

  In each of the above embodiments, the example in which the reference voltage is shared has been described. However, the present invention is not limited to this. For example, even when at least one of the power supply and the ground is shared, the same effect can be obtained according to the aspect of each embodiment. Even when the reference voltage, power supply, and ground are not shared, it is strong enough to affect the digital output signal of the analog-to-digital converter in the reference voltage, power supply, ground, and each signal path due to the effects of crosstalk, etc. It is conceivable that noise wraps around with intensity. Even in such a case, the same effect can be obtained by implementing the aspect of each embodiment based on the operation clock of the noise source circuit that causes the crosstalk.

  In the present invention, a good S / N can be obtained for an analog-digital converter on an LSI having a plurality of clocks. Therefore, for example, it is useful for a delta modulation type analog-digital converter and a delta-sigma modulation type analog-digital converter that are used by being incorporated in a circuit for processing voice or sound in a mobile phone or an audio device.

ADC 1 Analog to digital converter 13 Feedback circuit 17 Dither generation circuit 18 Output level adjustment circuit 20 Noise source circuit 21 Second PLL (PLL)
24 Sampling clock setting unit 25 Dither setting unit 30 Additional counter 32 Subtractor CLK1 Sampling clock CLK2 Operation clock AIN Analog input signals fs, fsa, fsb Sampling clock frequency fn Operation clock frequency ft, fta, ftb Tone frequency fpa, fpb frequency of alias signal fma, fmb frequency of modulated signal fbw signal band

Claims (19)

An oversampling type analog-digital converter having a feedback circuit;
A dither generation circuit configured to give a dither signal to the analog-to-digital converter and to be able to adjust the setting of the dither signal so as to change the frequency of a tone generated in the analog-to-digital converter;
A dither that obtains frequency information related to a frequency of an operation clock of a noise source circuit that applies periodic noise to the analog-to-digital converter and sets the dither signal in the dither generation circuit according to the frequency information A noise reduction system for an analog-to-digital converter, comprising a setting unit. In the noise reduction system of the analog-digital converter of Claim 1,
The dither setting unit performs setting of the dither signal in the dither generation circuit so that a frequency of a modulation signal generated from the tone and the periodic noise is out of a signal band according to the frequency information. A noise reduction system for analog-to-digital converters. In the noise reduction system of the analog-digital converter of Claim 1,
The dither setting unit obtains the frequency information from a PLL that supplies the operation clock, and a noise reduction system for an analog-to-digital converter. In the noise reduction system of the analog-digital converter of Claim 3,
The dither setting unit
Receiving a sampling clock of the analog-digital converter and the operation clock, calculating a remainder of the frequency of the sampling clock and the operation clock and outputting the remainder;
A subtractor that calculates and outputs a frequency difference between the frequency of the remainder calculated by the remainder calculator and the frequency of the tone;
A noise reduction system for an analog-to-digital converter, wherein the dither signal is set in the dither generation circuit so that a frequency difference calculated by the subtracter deviates from a signal band. In the noise reduction system of the analog-digital converter of Claim 1,
The dither generation circuit adds the dither signal to an analog input signal of the analog-to-digital converter. In the noise reduction system of the analog-digital converter of Claim 1,
The dither signal is a DC voltage signal;
The noise reduction system for an analog-digital converter, wherein the dither generation circuit changes the frequency of the tone by changing a DC voltage value of the dither signal. In the noise reduction system of the analog-digital converter of Claim 1,
The dither signal is a signal having a frequency lower than the sampling clock of the analog-digital converter,
The noise reduction system for an analog-to-digital converter, wherein the dither generation circuit changes the frequency of the tone by changing the amplitude of the dither signal. In the noise reduction system of the analog-digital converter of Claim 1,
The dither signal is a signal having a frequency lower than the sampling clock of the analog-digital converter,
The noise reduction system for an analog-to-digital converter, wherein the dither generation circuit changes the frequency of the tone by changing the frequency of the dither signal. In the noise reduction system of the analog-digital converter of Claim 1,
The dither signal is a signal having a frequency lower than the sampling clock of the analog-digital converter,
The noise reduction system for an analog-to-digital converter, wherein the dither generation circuit changes the frequency of the tone by changing a duty ratio of the dither signal. In the noise reduction system of the analog-digital converter of Claim 1,
An analog / digital converter noise reduction system, further comprising: an output level adjustment circuit that reduces a level of an output signal of the analog / digital converter for a predetermined period when the dither generation circuit switches the setting of the dither signal. . In the noise reduction system of the analog-digital converter of Claim 1,
The noise source circuit is a video signal processing circuit in which a frequency of the operation clock is determined by a video format;
The dither setting unit obtains the video format as the frequency information, and sets the dither signal in the dither generation circuit according to the video format. An oversampling analog-digital converter,
Obtaining frequency information about the frequency of the operation clock of the noise source circuit that gives periodic noise to the analog-digital converter, and setting the frequency of the sampling clock of the analog-digital converter according to the frequency information A noise reduction system for an analog-to-digital converter, comprising: a sampling clock setting unit for performing the operation. The noise reduction system for an analog-digital converter according to claim 12,
The sampling clock setting unit sets the frequency of the sampling clock so that the frequency of the alias signal generated from the sampling clock and the periodic noise is out of a signal band. Reduction system. The noise reduction system for an analog-digital converter according to claim 12,
The analog-digital converter has a feedback circuit,
The sampling clock setting unit sets the frequency of the sampling clock so that a difference between a frequency of the periodic noise and a frequency of a tone generated by the analog-digital converter is out of a signal band. Noise reduction system for digital converter. The noise reduction system for an analog-digital converter according to claim 1 or 12,
The noise reduction system for an analog-to-digital converter, wherein the noise source circuit and the analog-to-digital converter share at least one of a power supply, a ground, and a reference voltage. It is an oversampling type, equipped with an analog-digital converter with a feedback circuit,
An analog-to-digital converter characterized by controlling the frequency of a tone generated by the analog-to-digital converter in accordance with the frequency of an operation clock of a noise source circuit that applies periodic noise to the analog-to-digital converter. Noise reduction system. An oversampling method, a noise reduction method for an analog-digital converter having a feedback circuit,
Obtaining frequency information related to the frequency of an operation clock of a noise source circuit that applies periodic noise to the analog-to-digital converter, and changing the frequency of a tone generated in the analog-to-digital converter according to the frequency information. A signal setting step for adjusting the dither signal setting,
And a signal applying step of applying the dither signal set in the signal setting step to the analog-to-digital converter. The noise reduction method for an analog-digital converter according to claim 17,
In the signal setting step, the dither signal is set according to the frequency information so that a frequency of a modulation signal generated from a tone generated in the analog-digital converter and the periodic noise is out of a signal band. A method for reducing noise of an analog-digital converter as a feature. The noise reduction method for an analog-digital converter according to claim 17,
The signal setting step includes:
A frequency detection step of detecting a frequency of an operation clock of the noise source circuit;
A frequency calculating step of calculating a frequency of a tone generated in the analog-digital converter based on the frequency of the operation clock detected in the frequency detecting step;
The dither signal is set so that a difference between the frequency of the periodic noise detected in the frequency detection step and the frequency of the tone calculated in the frequency calculation step is out of a signal band. Noise reduction method for digital converter.

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