JP2014006949A - Semiconductor device, method of testing semiconductor device, method of manufacturing semiconductor device including test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device facilitating an input/output test that compares data read from a memory cell with expected data of the read data.SOLUTION: A semiconductor device includes: a serial-parallel conversion circuit that converts serial write data which is a plurality of serial bits being input from a data input/output terminal, into parallel write data which is a plurality of parallel bits; and a read data comparison circuit that generates a verification result signal for parallel read data by comparing the parallel read data which is a plurality of parallel bits being read from the memory cell with each of the bits of the parallel write data.

Description

  The present invention relates to a semiconductor device, a semiconductor device test method, and a semiconductor device manufacturing method including the test method. In particular, the present invention relates to a semiconductor device including a serial / parallel conversion circuit, a test method for the semiconductor device, and a method for manufacturing the semiconductor device including the test method.

  A semiconductor device such as a DRAM (Dynamic Random Access Memory) includes a memory cell therein and stores data in the memory cell. Therefore, it is necessary to determine whether the memory cell is good or bad in the manufacturing process of the semiconductor device. Specifically, the quality of the memory cell is determined by reading data from the memory cell and comparing the read data read with the expected value data corresponding to the read data.

  Patent Document 1 discloses a configuration of a semiconductor device having a system in which serial data is input to a data input / output terminal, and the input serial data is converted into parallel data and then written into a memory cell. Note that the semiconductor device disclosed in Patent Document 1 converts parallel data into serial data when outputting read data to the outside.

JP 2011-034645 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  The present inventors examined the application of an input / output test of a semiconductor device that compares data read from a memory cell with expected value data of the read data for a semiconductor device including a serial / parallel conversion circuit. As a result of the examination, it has been found that there is room for improvement in the operation margin of the circuit for verifying the read data. That is, when the frequency of the operation clock of the semiconductor device is increased, the period for sampling the read data and the expected value data is shortened, making it difficult to perform the input / output test in the semiconductor device operating at high speed. Details of the circuit for verifying the read data and the problem will be described later.

  According to a first aspect of the present invention, a serial-parallel conversion circuit that converts serial write data that is a plurality of serial bits input from a data input / output terminal into parallel write data that is a plurality of parallel bits, and a memory cell There is provided a semiconductor device comprising: a read data comparison circuit that generates a verification result signal for the parallel read data by comparing parallel read data that is a plurality of parallel read bits and each bit of the parallel write data. The

  According to a second aspect of the present invention, a first step of issuing a read command accompanied by an address signal of a memory cell whose read data is desired to be verified, and after a predetermined time has elapsed since the issue of the read command, Second step of inputting serial write data that is serial multiple bits, which is expected value data for read data output from the memory cell, and converting the serial write data into parallel multiple bits of parallel multiple bits A fourth step of comparing each bit of the parallel read data and the parallel write data, which is read data corresponding to the read command and is a plurality of parallel bits, and the fourth step Outputting a comparison result in the process as a verification result of the parallel read data. Test method of the apparatus is provided.

  According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method including the semiconductor device test method.

  According to each aspect of the present invention, a semiconductor device that facilitates an input / output test for comparing data read from a memory cell and expected data of the read data, a test method for the semiconductor device, and the A method for manufacturing a semiconductor device including a test method is provided.

It is a figure for demonstrating the outline | summary of one Embodiment. 1 is a diagram illustrating an example of a block diagram of an entire semiconductor device 1. FIG. 2 is a diagram showing an example of an internal configuration of an input / output circuit 80. FIG. It is a flowchart which shows an example of a read data verification test procedure. 2 is a diagram illustrating an example of an internal configuration of an input / output circuit 80a of the semiconductor device 2 according to the first embodiment. FIG. 4 is a timing chart showing an example of various signals during a read data verification test in the semiconductor device 2; It is a timing chart which shows an example of various signals at the time of reading verification result output signal TRCCRES from the outside.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to the outline are attached to the respective elements for convenience as an example for facilitating understanding, and the description of the outline is not intended to be any limitation.

  As described above, a semiconductor device that facilitates an input / output test for comparing data read from a memory cell with expected value data of the read data is desired.

  Therefore, as an example, the semiconductor device 100 illustrated in FIG. 1 is provided. The semiconductor device 100 includes a serial / parallel conversion circuit 101 that converts serial write data that is a plurality of serial bits input from a data input / output terminal into parallel write data that is a plurality of parallel bits, and a plurality of parallel parallel data read from memory cells. A read data comparison circuit that generates a verification result signal for the parallel read data by comparing each bit of the parallel read data and the parallel write data.

  The read data comparison circuit 102 receives read data (parallel data) read from the memory cell. Further, the read data comparison circuit 102 receives write data input from the outside and converted into parallel data by the serial / parallel conversion circuit 101. The read data comparison circuit 102 uses the received write data as expected value data for the read data read from the memory cell, and compares it with the read data expanded in parallel. As a result, the operation margin is improved as compared with the case where the read data converted into serial data is compared with the expected value data. That is, when the operating clock of the semiconductor device 100 is increased, the skew of the operating clock is strongly influenced, and it is necessary to compare the read data with the expected value data with high accuracy. However, since the verification is performed in a state where these data are expanded in parallel, the influence of the skew of the operation clock is alleviated and the read data can be easily verified even when the semiconductor device 100 is operating at high speed. it can.

  Next, the semiconductor device 1 capable of performing an input / output test for comparing the data read from the memory cell with the expected value data of the read data will be described. The semiconductor device 1 is a semiconductor device studied by the present inventors. The semiconductor device 1 includes a serial-parallel conversion circuit and a parallel-serial conversion circuit, and enables the above input / output test to be performed. In the following description, an input / output test for comparing read data read from a memory cell with expected value data for the read data is referred to as a read data verification test.

  FIG. 2 is a block diagram illustrating an example of the entire semiconductor device 1.

  The semiconductor device 1 is a DDR2 SDRAM (Double Data Rate 2 Synchronous DRAM). The prefetch number of the semiconductor device 1 is 4 bits. Therefore, 4-bit data can be input / output simultaneously to / from the memory cell array. The semiconductor device 1 includes eight data input / output terminals. Therefore, a total of 32 (= 4 × 8) bits of data can be input / output simultaneously to the memory cell array.

  The semiconductor device 1 includes at least a clock terminal 11, a command terminal 12, an address terminal 13, a data input / output terminal 14, and a data strobe terminal 15 as external terminals.

  The clock terminal 11 is a terminal to which a clock signal CLK that is a synchronization signal is supplied. The clock signal CLK is supplied to the internal clock generation circuit 21 via the clock terminal 11. The internal clock generation circuit 21 generates an internal clock ICLK, and the generated clock is supplied to various internal circuits including the DLL circuit 22.

  The DLL circuit 22 is a circuit that receives the internal clock ICLK and generates an output clock LCLK. The output clock LCLK is supplied to an input / output circuit 80 described later.

  The command terminal 12 is a terminal to which command signals such as a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and a chip select signal CS are supplied. These command signals are supplied to the command decoder 31.

  The command decoder 31 generates various internal commands ICMD by holding, decoding and counting command signals in synchronization with the internal clock ICLK. Further, the command decoder 31 receives a test command from the outside and enables execution of a read data verification test in the semiconductor device 1. Further, the command decoder 31 outputs various control signals to the input / output circuit 80. These control signals include control signals used in the read data verification test. The control signals output from the command decoder 31 will be described sequentially.

  The address terminal 13 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the address latch circuit 41 via the address terminal 13. The data input / output terminal 14 and the data strobe terminal 15 are terminals used for data input / output.

  Address latch circuit 41 latches address signal ADD in synchronization with internal clock ICLK. Of the address signal ADD latched by the address latch circuit 41, the row address XA is supplied to the row decoder 51, and the column address YA is supplied to the column decoder 52. The row decoder 51 is a circuit that selects any word line WL included in the memory cell array 60 based on the row address XA.

  In the memory cell array 60, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. In FIG. 2, only one word line WL, one bit line BL, and one memory cell MC are shown.

  The bit line BL is connected to the corresponding sense amplifier SA in the sense amplifier array 53. The column decoder 52 selects the sense amplifier SA included in the sense amplifier array 53 based on the column address YA. The selected sense amplifier SA is connected to the main amplifier 70 via the main I / O wiring MIO.

  As described above, in the semiconductor device 1, 32-bit data is input / output simultaneously from the memory cell array 60. Therefore, the main I / O wiring MIO is wired for at least 32 bits. The main amplifier 70 amplifies the read data read from the memory cell via the main I / O wiring MIO and outputs it to the read / write bus RWBUS. Further, the main amplifier 70 supplies write data to the memory cell supplied via the read / write bus RWBUS to the main I / O wiring MIO. The read / write bus RWBUS is connected to the input / output circuit 80.

  The input / output circuit 80 includes a serial / parallel conversion circuit and a parallel / serial conversion circuit. The input / output circuit 80 outputs the read data read as parallel plural bits (parallel data) via the read / write bus RWBUS as serial plural bits (serial data). The input / output circuit 80 supplies the write data input as serial data via the data input / output terminal 14 to the read / write bus RWBUS as parallel data. Specifically, the read operation is described as an example. Read data supplied in parallel via 32 read / write buses RWBUS is serially converted into 4 bits for each data input / output terminal, and 4 bits of read data is output. The data is output from the data input / output terminal 14 in synchronization with the clock LCLK.

  Next, the input / output circuit 80 will be described.

  FIG. 3 is a diagram illustrating an example of the internal configuration of the input / output circuit 80.

  The input / output circuit 80 includes a read data latch circuit 81, a parallel / serial conversion circuit 82, a data output circuit 83, a data input circuit 84, a serial / parallel conversion circuit 85, and a write data latch circuit 86. .

  In the following description, the read data supplied to the read / write bus RWBUS is referred to as parallel read data P_RD, and the write data supplied to the read / write bus RWBUS is referred to as parallel write data P_WD. In the following drawings, only one data input / output terminal 14 is shown. That is, the description will be made assuming that the bus width of the read / write bus RWBUS is 4 bits. However, the bus width is actually equal to the number of data input / output terminals 14.

  The read data latch circuit 81 is a circuit that latches the parallel read data P_RD supplied from the read / write bus RWBUS. Latching is performed based on the read data latch signal RDLAT. Data latched by the read data latch circuit 81 is referred to as parallel read data PL_RD.

  The parallel / serial conversion circuit 82 converts the parallel read data PL_RD into serial data and outputs the serial data to the data output circuit 83. The parallel-serial conversion circuit 82 converts parallel data into serial data in accordance with the activation of the parallel-serial conversion permission signal CFIFO. The serial data converted by the parallel-serial conversion circuit 82 is expressed as serial read data S_RD.

  The data output circuit 83 receives serial read data S_RD, an output clock LCLK, various control signals (TRCCEN, TRCCOUT, TRCCRST) used for a read data verification test, and an expected value data signal TDCMP. The data output circuit 83 outputs the serial read data S_RD to the outside via the data input / output terminal 14 when the verification test enable signal TRCCEN is at L level (deactivation level).

  The data output circuit 83 performs a read data verification test. More specifically, the data output circuit 83 outputs a comparison result between the serial read data S_RD and the expected value data signal TDCMP as a test result. The expected value data signal TDCMP is a signal that represents a value expected for read data read from the memory cell. For example, if it is expected that “1” is read from the memory cell to be tested, the value of the expected value data signal TDCMP corresponding to the serial read data S_RD read from the memory cell is “1”. The read data verification test using the data output circuit 83 will be described later.

  The data input circuit 84 receives write data through the data input / output terminal 14. The data input circuit 84 receives the data input enable signal DINEN and the verification test enable signal TRCCEN. The data input circuit 84 outputs the data received from the data input / output terminal 14 to the serial / parallel conversion circuit 85 when the data input enable signal DINEN is at the H level (activation level). A signal output from the data input circuit 84 to the serial / parallel conversion circuit 85 is expressed as serial write data S_WD.

  When verification test enable signal TRCCEN is at the H level (activation level), data received from data input / output terminal 14 is output to data output circuit 83 as expected value data signal TDCMP. Note that the command decoder 31 does not activate both the data input enable signal DINEN and the verification test enable signal TRCCEN.

  The serial / parallel conversion circuit 85 receives the serial write data S_WD, converts it into parallel data, and outputs it to the write data latch circuit 86. The parallel data output from the serial / parallel conversion circuit 85 is represented as parallel write data P_WD.

  The write data latch circuit 86 latches the parallel write data P_WD and supplies it to the read / write bus RWBUS. Latching in the write data latch circuit 86 is performed based on the write data latch signal WDLAT. The data latched by the write data latch circuit 86 is expressed as parallel write data PL_WD.

  Next, the implementation of the read data verification test in the data output circuit 83 will be described.

  FIG. 4 is a flowchart illustrating an example of a read data verification test procedure in the semiconductor device 1.

  In step S01, a command for switching the semiconductor device 1 to a test mode for executing a read data verification test is supplied from the outside of the semiconductor device 1 (for example, a memory controller). Receiving the command for transition to the test mode, the command decoder 31 sets the verification test enable signal TRCCEN to the H level. When the verification test enable signal TRCCEN becomes H level, the data output circuit 83 switches from an operation of outputting normal read data to an operation of executing a read data verification test. That is, when the verification test enable signal TRCCEN is set to H level, the data output circuit 83 stops the operation of outputting normal read data.

  After the verification test enable signal TRCCEN is set to the H level, the verification test reset signal TRCCRST is set to the H level, and the verification result is initialized.

  In step S02, a read command accompanied by an address signal ADD of a memory cell whose read data is desired to be verified is issued from outside the semiconductor device 1.

  In step S03, expected value data corresponding to read data (serial read data S_RD) read from the memory cell is input from outside the semiconductor device 1. At this time, since the verification test enable signal TRCCEN is at the H level, the data input circuit 84 outputs the expected value data signal TDCMP to the data output circuit 83.

  In step S04, the data output circuit 83 verifies the read data. Specifically, the serial read data S_RD and the expected value data signal TDCMP are compared bit by bit, and the comparison result is held (latched) as a verification result signal.

  In step S05, a command with an instruction to output the verification result signal held by the data output circuit 83 to the outside is supplied from the outside of the semiconductor device 1. Upon receiving this command, the command decoder 31 sets the verification test enable signal TRCCEN to the L level, and sets the verification test output instruction signal TRCCOUT to the H level (activation level). When the verification test output instruction signal TRCCOUT is set to the H level, the data output circuit 83 outputs the verification result signal held therein to the outside via the data input / output terminal 14. That is, the data output circuit 83 outputs a verification result signal from the data input / output terminal 14 instead of the serial read data S_RD corresponding to the read command.

  As described above, the semiconductor device 1 verifies the read data by comparing the serial read data S_RD output from the parallel-serial conversion circuit 82 with the expected value data (expected value data signal TDCMP) input from the outside.

  However, verification of such read data becomes difficult as the frequency of the output clock LCLK increases. That is, the period (data window) in which the read data and the expected value data can be sampled effectively becomes shorter as the frequency of the clock signal CLK increases, and the operation margin of the read data verification test in the data output circuit 83 decreases.

[First Embodiment]
The first embodiment will be described in more detail with reference to the drawings.

  The overall configuration of the semiconductor device 2 according to the present embodiment does not differ from the semiconductor device 1, so the description corresponding to FIG. 2 is omitted. FIG. 5 is a diagram illustrating an example of an internal configuration of the input / output circuit 80a of the semiconductor device 2 according to the present embodiment. In FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted. The difference between the input / output circuits 80 and 80a is that a read data comparison circuit 87 is provided. The command decoder 31 outputs a verification test result latch signal TRCCLAT in addition to the various control signals described above (not shown in FIG. 2).

  The read data comparison circuit 87 receives parallel write data PL_WD latched by the write data latch circuit 86 and parallel read data PL_RD latched by the read data latch circuit 81. Further, the read data comparison circuit 87 receives a verification test enable signal TRCCEN, a verification test result latch signal TRCCLAT, and a verification test reset signal TRCCRST.

  The read data comparison circuit 87 verifies the read data using the parallel write data PL_WD latched by the write data latch circuit 86 as expected value data. Since the semiconductor device 2 is capable of prefetching 4 bits, it simultaneously verifies the read data of 4 bits per data input / output terminal 14. More specifically, it is determined whether or not the values of the 4-bit parallel read data PL_RD and the 4-bit expected value data (parallel write data PL_WD) match each other in bit units. The read data comparison circuit 87 outputs the verification result of the read data as a verification result output signal TRCCRES.

  Further, the read data comparison circuit 87 performs an AND operation on each determination result for 4 bits, and generates an H-level verification result signal if all bits match. If the verification result signal is at the H level, the read data is as expected, so it can be determined that the verification result is normal. On the other hand, if even one bit does not match, the verification result signal becomes L level, so that the verification result can be determined to be abnormal. The generated verification result signal is output as the verification result output signal TRCCRES when the verification test result latch signal TRCCLAT at the H level (activation level) is received. Of course, even if the prefetch is not 4 bits, the read data comparison circuit 87 can be appropriately changed according to the number of prefetch bits.

  Next, an operation during a read data verification test in the semiconductor device 2 will be described. The read data verification test procedure in the semiconductor device 2 will be described using a timing chart including differences from the procedure using FIG.

  FIG. 6 is a timing chart showing an example of various signals during a read data verification test in the semiconductor device 2.

  At time t01, the command decoder 31 initializes the verification result output signal TRCCRES by setting the verification test reset signal TRCCRST to the H level while setting the verification test enable signal TRCCEN to the H level. Note that the function related to the read data verification test of the read data comparison circuit 87 and the data input circuit 84 is activated when the verification test enable signal TRCCEN becomes H level.

  On the other hand, when the verification test enable signal TRCCEN is at the H level, the data output circuit 83 stops its operation. As a result, read data is not output from the data output circuit 83 to the data input / output terminal 14.

  At time t02, verification test reset signal TRCCRST is set to L level, and the reset state of read data comparison circuit 87 is released.

  At time t03, a read command is issued from outside the semiconductor device 2. Thereafter, in the period from time t04 to t05, expected value data is input from the outside via the data input / output terminal 14. At this time, the expected value data is input in synchronization with the rise and fall of the data strobe signal DQS.

  The data input circuit 84 outputs the expected value data input from the data input / output terminal 14 to the serial / parallel conversion circuit 85 as serial write data S_WD sequentially as soon as the expected value data is received. The serial / parallel conversion circuit 85 converts the received serial write data S_WD (expected value data) into parallel write data P_WD and outputs it to the write data latch circuit 86.

  At time t06, command decoder 31 sets write data latch signal WDLAT to the H level. As a result, the write data latch circuit 86 outputs the parallel write data PL_WD to the read data comparison circuit 87.

  On the other hand, the read data corresponding to the read command issued at time t03 is supplied to the read / write bus RWBUS (time t07; where the read latency is 8). At time t07, when the read data latch signal RDLAT is set to H level, the parallel read data P_RD is latched and the parallel read data PL_RD is output to the read data comparison circuit 87.

  Thus, at the timing of time t07, the parallel write data PL_WD supplied from the write data latch circuit 86 and the parallel read data PL_RD supplied from the read data latch circuit 81 are simultaneously input to the read data comparison circuit 87. It will be in the state. The read data comparison circuit 87 compares both input data in units of bits and generates a verification result signal.

  Further, at time t07, the verification test result latch signal TRCCLAT is set to the H level, so that the read data comparison circuit 87 latches the verification result signal. The verification result signal is output as the verification result output signal TRCCRES after time t07.

  In the semiconductor device 2, expected value data can be input from the data input / output terminal 14 by setting the verification test enable signal TRCCEN to the H level. Further, in response to the issue of the read command, the expected value data is input from the outside in accordance with the timing at which the read data read from the memory cell is supplied to the read / write bus RWBUS. For example, when the read latency of the semiconductor device 2 is 8, when the supply of the expected value data is started at the time t04, the read data and the expected value data are simultaneously supplied to the read data comparison circuit 87.

  The read data comparison circuit 87 verifies the read data and outputs the verification result as a verification result output signal TRCCRES. The verification test result latch signal TRCCLAT is output only when the verification test enable signal TRCCEN is at H level. The above description is the verification of the read data using the read data comparison circuit 87.

  Next, the reading operation of the verification result output signal TRCCRES will be described.

  FIG. 7 is a timing chart showing an example of various signals when the verification result output signal TRCCRES is read from the outside.

  When reading the verification result output signal TRCCRES from the outside, the verification test enable signal TRCCEN is set to L level and the verification test output instruction signal TRCCOUT is set to H level. As a result, the parallel-serial conversion circuit 82 outputs a verification result output signal TRCCRES to the data output circuit 83 instead of the read data read from the memory cell in response to a read command (time t11) issued from the outside.

  Thereafter, the data output circuit 83 outputs the verification result output signal TRCCRES from the data input / output terminal 14 (time t12).

  As described above, the expected value data used for the read data verification test is input as serial data from the data input / output terminal 14 in the same manner as the normal write operation. Thereafter, the data is supplied as parallel data to the read data comparison circuit 87 by the serial / parallel conversion circuit 85. In addition, a signal output from the read data latch circuit 81 (a signal before parallel / serial conversion) is also supplied to the read data comparison circuit 87. The read data comparison circuit 87 verifies the read data using the expected value data expanded in parallel and the read data before being converted into serial data.

  Thus, since the read data comparison circuit 87 compares the respective bits of the parallel data, operation at a low speed is allowed. That is, the operation margin in the read data verification test is expanded. That is, the read data verification test in the semiconductor device 2 can be easily performed.

  Further, when a plurality of semiconductor devices 2 are housed in the same package and the data input / output terminals are common on the package (or common on the test board), read data is supplied to the plurality of semiconductor devices 2. Verification tests can be performed in parallel. That is, the read data verification test is executed in parallel in the plurality of semiconductor devices 2, and the verification result is read and confirmed independently from each semiconductor device 2. As a result, it is not necessary to individually set expected value data for a plurality of semiconductor devices 2, and the test time can be shortened. The effect related to the reduction in the test time can be similarly expected in the read data verification test in the semiconductor device 1.

  The semiconductor device manufacturing process includes a plurality of test processes, and the semiconductor device manufacturing process can be configured including the read data verification test described in the first embodiment.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 2, 100 Semiconductor device 11 Clock terminal 12 Command terminal 13 Address terminal 14 Data input / output terminal 15 Data strobe terminal 21 Internal clock generation circuit 22 DLL circuit 31 Command decoder 41 Address latch circuit 51 Row decoder 52 Column decoder 53 Sense amplifier array 60 memory cell array 70 main amplifiers 80, 80a input / output circuit 81 read data latch circuit 82 parallel serial conversion circuit 83 data output circuit 84 data input circuit 85, 101 serial parallel conversion circuit 86 write data latch circuit 87, 102 read data comparison circuit

Claims (10)

A serial-parallel conversion circuit for converting serial write data, which is a plurality of serial bits input from a data input / output terminal, into parallel write data, which is a plurality of parallel bits;
A read data comparison circuit that generates a verification result signal for the parallel read data by comparing parallel read data that is a plurality of parallel bits read from the memory cell and each bit of the parallel write data;
A semiconductor device comprising: A control circuit that accepts a test command for transitioning to a read data verification test for verifying read data read from a memory cell,
The control circuit activates the first control signal when the test command is received,
The semiconductor device according to claim 1, wherein the read data comparison circuit compares the parallel read data and the parallel write data when the first control signal is activated. A parallel-serial conversion circuit that converts the parallel read data into serial read data that is a plurality of serial bits,
3. The semiconductor device according to claim 2, wherein the parallel-serial conversion circuit does not perform conversion into the serial read data when the first control signal is at an activation level. The control circuit activates a second control signal after a predetermined period of time has elapsed since the reception of the read command when the first control signal is at an activation level and receives a read command from the outside.
4. The semiconductor device according to claim 2, wherein the read data comparison circuit latches the verification result signal and outputs it as a verification result output signal in response to the activation of the second control signal. The control circuit activates a third control signal when receiving a command to output the verification result signal from the outside when the first control signal is at an inactivation level,
5. The semiconductor device according to claim 4, wherein the parallel-serial conversion circuit outputs the verification result output signal to the outside via the data input / output terminal when the third control signal is at an activation level. A write data latch circuit that latches the parallel write data according to a fourth control signal and outputs the latched parallel write data to the read data comparison circuit;
A read data latch circuit that latches the parallel read data in accordance with a fifth control signal and outputs the latched parallel read data to the read data comparison circuit;
The semiconductor device as described in any one of Claims 1 thru | or 5 provided with these.   The parallel-serial conversion circuit outputs the parallel read data latched by the read data latch circuit to the outside via the data input / output terminal when the third control signal is at an inactive level. 6. Semiconductor device of 6. The read data comparison circuit includes:
8. The semiconductor device according to claim 1, wherein a result obtained by performing an AND operation on a comparison result for each bit of the parallel read data and the parallel write data is generated as the verification result signal. 9. A first step of issuing a read command accompanied by an address signal of a memory cell for which verification of read data is desired;
A second step of inputting serial write data, which is expected value data for read data output from the memory cell after a predetermined time has elapsed from the issue of the read command, and is a plurality of serial bits;
A third step of converting the serial write data into parallel multi-bit parallel write data;
A fourth step of comparing the read data corresponding to the read command, each of the parallel read data and the parallel write data being a plurality of parallel bits;
Outputting a comparison result in the fourth step as a verification result of the parallel read data;
A method for testing a semiconductor device, comprising:   A method for manufacturing a semiconductor device, comprising the method for testing a semiconductor device according to claim 9.

Images