JP2014003319A - Sos substrate with low surface defect density - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SOS substrate with low surface defect density.SOLUTION: A method for manufacturing a pasted SOS substrate 8 having a semiconductor thin film 4 on a surface of a sapphire substrate 3, comprises: a step for providing the sapphire substrate 3 and a semiconductor substrate 1; a step for forming an ion implantation layer 2 by implanting ions from the surface of the semiconductor substrate 1; a step for performing surface activation processing on at least one of a surface of the sapphire substrate 3 and the ion-implanted surface of the semiconductor substrate 1; a step for sticking the surface of the semiconductor substrate 1 and the surface of the sapphire substrate 3 at a temperature of 50°C to 350°C; a step for obtaining a joint body 6 by performing thermal processing on the pasted substrates at a maximum temperature of 200 to 350°C; and a step for bringing the joint body 6 to a state of a temperature higher than the pasting temperature, irradiating the ion implantation layer 2 of the semiconductor substrate 1 with visible light from the sapphire substrate 3 side or the semiconductor substrate 1 side to make the interface of the ion implantation layer 2 fragile, and transferring the semiconductor thin film 4.

Description

  The present invention relates to an SOS substrate having a low surface defect density.

  Conventionally, a silicon on sapphire (SOS) substrate using sapphire having a high insulating property, low dielectric loss, and high thermal conductivity as a handle substrate has been put into practical use since the 1960s and has been used up to now. The SOS substrate is the oldest silicon on insulator (SOI) substrate, and the SOI structure is realized by heteroepitaxially growing silicon on the R surface (1012) of sapphire.

  However, in recent years, SOI using a SIMOX method or a bonding method has become the mainstream, and the SOS substrate is used only for a high frequency device that requires a low dielectric loss, for example, an SOI that cannot be handled by an SOI in which the sapphire substrate is silicon. Yes. Heteroepi SOS is known to cause many defects due to lattice size mismatch because silicon is heteroepitaxially grown on sapphire having a lattice constant different by 12% (see, for example, Non-Patent Document 1).

  In recent years, the demand for high-frequency devices has increased due to the widespread use of mobile communications such as mobile phones, but the use of SOS is considered in this field. However, in the heteroepi SOS, the defect density is high, and the actual use is limited to small individual parts (switches and the like).

The surface defect density of the heteroepi SOS is determined by the Secco defect detection method (K ₂ Cr ₂ O ₇ or a mixed solution of Cr ₂ O ₃ and HF) or the selective etching defect detection method (mixture of HF, KI, I, and CH ₃ OH). In the case of (solution), etc., it is reported that it is about 10 ⁹ pieces / cm ² (for example, see Non-Patent Document 1).

  In order to reduce the defects of this hetero epi SOS, high concentration Si is ion-implanted in the vicinity of the interface between the Si film and the sapphire substrate, the Si surface is left to change to amorphous, and annealing is performed near 600 ° C. from the surface side with few defects. A method of gradually recrystallizing an amorphous layer has been proposed and is called single solid phase growth. In addition, a method (double solid phase growth method) in which this process is repeated twice to try further defect reduction has been proposed (for example, see Non-Patent Document 1).

However, even if the double solid phase growth method is used, the defect density is about 10 ⁶ to 10 ⁷ pieces / cm ² , and it is difficult to make a leading-edge device that has been miniaturized in recent years. It is also difficult to produce a relatively large device such as a system chip that incorporates many functions. This can be said to be rooted in the essential problem of heteroepi growth (epi growth of materials having different lattice constants).

Yoshii et al. Japan Journal of Applied Physics, Vol. 21 (1982) Supplement 21-1, pp. 175-179 Realize "Science of SOI" Chapter 2 Section 2 Section 2

  In view of the above situation, the present invention has an object to provide an SOS substrate having a low defect density by overcoming the problem of an increase in defect density due to mismatch of lattice constants between silicon and sapphire.

The present inventor has devised the following production method in order to solve the above-described problems.
That is, the present invention is a method for manufacturing an SOS substrate by forming a single crystal silicon layer on the surface of a sapphire substrate (handle), and implanting ions into a silicon substrate or a silicon substrate with an oxide film to form an ion implantation layer. Forming a surface, applying a surface activation process to at least one of the surface of the sapphire substrate and the surface of the silicon substrate or oxide-coated silicon substrate into which the ions have been implanted, with the silicon substrate or the oxide film After bonding the silicon substrate and the sapphire substrate, a heat treatment is performed at 200 ° C. or more and 350 ° C. or less to obtain a bonded body, and ions of the silicon substrate or the silicon substrate with oxide film from the sapphire substrate side of the bonded body Irradiation of visible light toward the implantation layer embrittles the interface of the ion implantation layer, and The step of transferring the down thin film on sapphire substrate is a manufacturing method of the SOS substrate including in that order.

The present invention, SOI equivalent bonding defect density (10 ⁴ / cm ² about: see Non-Patent Document 2), and the integrated device can be realized.

It is a schematic diagram which shows the one aspect | mode of the manufacturing process of the bonding SOS of this invention. It is the (a) whole top view of the bonding SOS of this invention, and the (b) enlarged plan view of the outer peripheral part. It is a graph which shows the defect density measured by changing the defect detection location (wafer outer peripheral part / wafer center part) and the defect detection method (Seco / selective etching) of the bonding SOS of the present invention. It is sectional drawing in (a) wafer center part of the bonding SOS of this invention, and (b) wafer outer peripheral part.

The SOS substrate according to the present invention includes a single crystal silicon thin film on a sapphire substrate, and the surface defect density of the single crystal silicon thin film measured by the Secco defect detection method and the selective etching defect detection method is 10 ^4. / Cm ² or less.
The Secco defect detection method and the selective etching defect detection method are detection techniques known to those skilled in the art, and will not be described here. These detection methods are generally performed after the single crystal silicon thin film is made to have a predetermined thickness by CMP polishing.

  In the SOS substrate according to the present invention, the thickness of the single crystal silicon thin film can be a value exceeding 100 nm. By setting the thickness within the above range, the defect density in the bulk portion is not so high as compared to the vicinity of the interface between the silicon thin film and the sapphire substrate, and there is an advantage that the defect is not easily affected by defects near the interface. In addition, when the silicon thin film is thick, there is an advantage that it is easy to handle because the electrical characteristics are relatively insensitive to the thickness variation. As an upper limit of thickness, it can be 500 nm, for example.

In the SOS substrate according to the present invention, the thickness variation of the single crystal silicon thin film can be 20 nm or less. When the silicon thin film is thick, there is an advantage that the electrical characteristics are relatively insensitive to the thickness variation, so that it is easy to handle, but the SOS substrate according to the present invention further improves the electrical properties by the small thickness variation. Can do. According to the method for manufacturing an SOS substrate according to the present invention, which will be described later, since peeling / transfer is defined at the ion implantation interface, it becomes easy to make the film thickness variation after transfer within the above range.
The film thickness of the single crystal silicon thin film is a value measured by an optical interference film thickness meter and averaged within a diameter of about 1 mm which is the spot diameter of the measurement beam light. The thickness variation is a value defined by the square root of the square sum of the film thickness displacement from the average value by providing 361 measurement points radially.

  The SOS substrate according to the present invention preferably has a silicon oxide film sandwiched between the single crystal silicon thin film and the sapphire substrate. This is because an effect of suppressing channeling of implanted ions can be obtained. Such an SOS substrate can be obtained, for example, by forming an insulating film such as a silicon oxide film on the surface of a silicon wafer prior to the ion implantation step in the bonding method described later.

The SOS substrate according to the present invention can be particularly suitably used for manufacturing various devices in which the SOI layer is allowed to function as partial depletion.
Such semiconductor devices include, for example, CPUs and system chips incorporating many arithmetic processing functions; high-frequency devices such as microwave devices and millimeter-wave devices that are required to have low dielectric loss; and electrical engineering equipment such as liquid crystal devices. Examples include substrates.

  The SOS substrate according to the present invention has a defect density within the above range even if the diameter is 100 mm or more. If a diameter is in the said range, an upper limit can be 300 mm, for example.

  The SOS substrate is preferably manufactured by a bonding method. By adopting the bonding method, there is an advantage that the correlation between the defect density in the vicinity of the sapphire / silicon interface and the defect density in the bulk portion can be reduced as compared with the epi growth method.

As the bonding method, for example, the bonded body is heat-treated at about 500 ° C. in an inert gas atmosphere, and thermal peeling is performed by the effect of crystal rearrangement and the aggregation effect of injected hydrogen bubbles; A method of peeling at the hydrogen ion implantation interface or the like by applying a temperature difference between them may be employed, but it is preferable to employ the method for manufacturing the SOS substrate according to the present invention.
Hereinafter, the manufacturing method of the SOS substrate concerning this invention is demonstrated in detail based on FIG.
First, as a semiconductor substrate, for example, an ion implantation layer 2 is formed by implanting ions into a silicon substrate or a silicon substrate 1 with an oxide film (hereinafter simply referred to as a silicon wafer unless otherwise distinguished).
The ion implantation layer 2 is formed in a silicon wafer. At this time, a predetermined dose of hydrogen ions (H ⁺ ) or hydrogen molecular ions (H ₂ ⁺ ) is implanted with an implantation energy that can form an ion implantation layer at a desired depth from the surface. As a condition at this time, for example, the implantation energy can be set to 30 to 100 keV.

The dose of hydrogen ions (H ⁺ ) implanted into the silicon wafer is preferably 1.0 × 10 ¹⁶ atoms / cm ^{2 to} 1.0 × 10 ¹⁷ atoms / cm ² . If it is less than 1.0 × 10 ¹⁶ atom / cm ² , the interface may not be embrittled. If it exceeds 1.0 × 10 ¹⁷ atom / cm ² , bubbles are transferred during heat treatment after bonding. It may become defective. A more preferable dose amount is 6.0 × 10 ¹⁶ atoms / cm ² .
When hydrogen molecular ions (H ₂ ⁺ ) are used as implanted ions, the dose is preferably 5.0 × 10 ¹⁵ atoms / cm ^{2 to} 5.0 × 10 ¹⁶ atoms / cm ² . If it is less than 5.0 × 10 ¹⁵ atoms / cm ² , the interface may not be embrittled. If it exceeds 5.0 × 10 ¹⁶ atoms / cm ² , bubbles are transferred during heat treatment after bonding. It may become defective. A more preferable dose amount is 2.5 × 10 ¹⁶ atoms / cm ² .
Also, if an insulating film such as a silicon oxide film of about several nm to 500 nm is formed on the surface of the silicon wafer in advance and hydrogen ions or hydrogen molecular ions are implanted therethrough, the effect of suppressing channeling of the implanted ions can be obtained. can get.

Next, the surface of the silicon wafer 1 and / or the surface of the sapphire substrate 3 is activated. Examples of the surface activation treatment include plasma treatment, ozone water treatment, UV ozone treatment, and ion beam treatment.
When processing with plasma, a silicon wafer and / or a sapphire substrate cleaned by RCA cleaning or the like is placed in a vacuum chamber, a plasma gas is introduced under reduced pressure, and then a high-frequency plasma of about 100 W is applied to a high-frequency plasma of about 5-10. The surface is exposed to plasma for about 2 seconds. As a plasma gas, when processing a silicon wafer, when oxidizing the surface, plasma of oxygen gas, when not oxidizing, hydrogen gas, argon gas, or a mixed gas thereof or a mixed gas of hydrogen gas and helium gas Can be used. When processing a sapphire substrate, any gas may be used.
By treating with plasma, organic substances on the surface of the silicon wafer and / or sapphire substrate are oxidized and removed, and OH groups on the surface are increased and activated. The treatment is more preferably performed on both the ion-implanted surface of the silicon wafer and the bonding surface of the sapphire substrate, but only one of them may be performed.
When processing with ozone, it is a method characterized by introducing ozone gas into pure water and activating the wafer surface with active ozone.
When performing UV ozone treatment, the surface is activated by applying short-wave UV light (at a wavelength of about 195 nm) to the atmosphere or oxygen gas to generate active ozone.
When ion beam processing is performed, surface activation is performed by exposing an ion beam such as Ar to the wafer surface in a high vacuum (<1 × 10 ⁻⁶ Torr) to expose a dangling bond having high activity.

The surface of the silicon wafer that is subjected to the surface activation treatment is preferably an ion-implanted surface.
In the present invention, the thickness of the silicon wafer is not particularly limited, but a silicon wafer in the vicinity of a normal SEMI / JEIDA standard is easy to handle because of handling.
It is desirable that the sapphire substrate has a low energy loss until it reaches the ion implantation layer of the silicon wafer to which the light in the visible light region (wavelength 400 nm to 700 nm) is bonded, and the transmittance in the visible light region is high. Although it will not specifically limit if it is a board | substrate of 70% or more, In particular, it is preferable that it is either quartz, glass, or sapphire at the point which is excellent in insulation and transparency.
In the present invention, the thickness of the sapphire substrate is not particularly limited, but a substrate in the vicinity of a normal SEMI / JEIDA standard is easy to handle because of handling.

  Next, the surface of the silicon wafer 1 and the surface of the sapphire substrate 3 treated with plasma and / or ozone are bonded together as a bonding surface.

Next, the bonded substrate 6 is subjected to heat treatment at a maximum temperature of 200 ° C. or higher and 350 ° C. or lower to obtain a bonded body 6. The reason for performing the heat treatment is to prevent the introduction of crystal defects due to a shift in the bonding interface 9 due to a rapid temperature rise when the bonding interface 9 becomes high temperature by irradiation with visible light in a subsequent process. The reason why the maximum temperature is 200 ° C. or higher and 350 ° C. or lower is that the bonding strength does not increase when the temperature is lower than 200 ° C., and the bonded substrate may be damaged when the temperature exceeds 350 ° C.
The heat treatment time is preferably 12 hours to 72 hours depending on the temperature to some extent.

  Next, prior to visible light irradiation, a mechanical impact may be applied to the vicinity of the bonding interface 9 at the end portion of the bonded body 6. By applying a mechanical impact in the vicinity of the bonding interface, there is an advantage that the peeling start point becomes one place when irradiated with visible light, and the peeling spreads over the entire surface of the wafer, so that the thin film is easily transferred.

Subsequently, the substrate is cooled to room temperature as desired, and visible light is irradiated from the sapphire substrate 3 side or the semiconductor substrate 1 side of the bonded body 6 toward the ion implantation layer 2 of the silicon wafer 5 to perform annealing.
In this specification, “visible light” refers to light having a maximum wavelength in the range of 400 to 700 nm. Visible light may be either coherent light or incoherent light.

The temperature of the joined body 6 at the time of visible light irradiation is preferably 30 ° C. to 100 ° C. higher than the temperature at the time of bonding.
The reason why it is desirable to perform light irradiation at a high temperature is not intended to limit the technical scope of the present invention, but can be explained as follows. That is, when a substrate bonded at a high temperature is heated and returned to room temperature after sufficient bonding strength is obtained, the substrate warps due to the difference in expansion coefficient between the two substrates. When this substrate is irradiated with light, the stress is suddenly released during thin film transfer, so that the substrate returns to a flat state, and defects are introduced into the transferred semiconductor thin film. This is because it has been found by experiments of the present inventors that the material may be damaged.
Such substrate damage can be avoided by performing light irradiation at a high temperature.
In order to irradiate the substrate with light in a flat state, it is desirable to heat the substrate to a temperature close to that at the time of bonding. The important point is that the wafer is heated during irradiation.

As an example of visible light, when annealing is performed using laser light, since the laser light passes through the sapphire substrate 3 and is hardly absorbed, it reaches the silicon substrate 1 without heating the sapphire substrate 3. The laser beam that has reached is selectively heated only in the vicinity of the silicon bonding interface 9 (including the bonding interface), in particular, the portion that has been made amorphous by hydrogen ion implantation, and promotes embrittlement at the ion implantation site.
Further, when a very small part of the silicon substrate 1 (only silicon in the vicinity of the bonding interface 9) is instantaneously heated, the substrate is not cracked or warped after cooling.

The wavelength of the laser used here is a wavelength that is relatively easily absorbed by silicon (700 nm or less), and amorphous silicon so that the portion that has been made amorphous by hydrogen ion implantation can be selectively heated. It is desirable that the wavelength be absorbed by the single crystal silicon portion and hardly be absorbed by the single crystal silicon portion. A suitable wavelength region is about 400 nm to 700 nm, preferably 500 nm to 600 nm. Examples of lasers matching this wavelength range include Nd: YAG laser second harmonic (wavelength λ = 532 nm), YVO ₄ laser second harmonic (wavelength λ = 532 nm), and the like, but are limited. It is not a thing.

It should be noted here that if the ion-implanted portion 2 is heated too much by laser irradiation, thermal delamination occurs partially and blister defects called blisters occur. This is visually observed from the sapphire substrate side of the bonded SOS substrate. Once peeling is started by this blister, stress is localized in the bonded SOS substrate, and the bonded SOS substrate is destroyed. Therefore, it is important to irradiate the laser to such an extent that thermal peeling does not occur, and then perform mechanical peeling. Alternatively, prior to laser irradiation, a mechanical shock is applied to the edge of the bonded SOS substrate and the vicinity of the bonding interface 9 so that the heat shock caused by the laser irradiation is bonded from the mechanical shock starting point of the edge. It is important to cause destruction of the ion implantation interface over the entire surface of the SOS substrate.
The irradiation conditions of the laser, the oscillation frequency output 50W~100W case of using those 25 mJ @ 3 kHz, the irradiation energy per area, it is desirable that the empirically ^{5J / cm 2 ~30J / cm 2} . If it is less than 5 J / cm ² , embrittlement at the ion implantation interface may not occur, and if it exceeds 30 J / cm ² , embrittlement is too strong and the substrate may be damaged. Irradiation scans a spot-like laser beam on the wafer, so it is difficult to define the time, but it is desirable that the irradiation energy after the treatment falls within the above range.

  Further, RTA (Rapid Thermal Annealing) including spike annealing may be performed instead of the laser annealing as described above. RTA is a device that uses a halogen lamp as a light source and can heat a target wafer by reaching a target temperature at a very high speed of 30 ° C./second to 200 ° C./second. The wavelength emitted by the halogen lamp at this time follows black body radiation and has a high emission intensity in the visible light region. Spike annealing is not particularly drawn, and RTA has a particularly high rate of temperature rise (for example, 100 ° C./second or more). Since sapphire is heated at a very high speed and sapphire is not heated in this wavelength band (by radiation), silicon is heated earlier than sapphire, which is suitable for embrittlement of the ion implantation interface. In the case of RTA, the process is completed when sufficient heat is transferred to the sapphire.

Furthermore, it is possible to perform flash lamp annealing instead of laser annealing as described above. As the wavelength of the flash lamp used here, it is inevitable that there is a certain wavelength range as long as it is a lamp, but the peak intensity is in a wavelength range of 400 nm to 700 nm (a wavelength range that is efficiently absorbed by silicon). It is desirable to have it. This is because even if it is less than 400 nm, even single crystal silicon has a high absorption coefficient, and if it exceeds 700 nm, the absorption coefficient is low even for amorphous silicon. A suitable wavelength region is about 400 nm to 700 nm. As a lamp light source that matches this wavelength range, heating by a xenon lamp is generally used. The peak intensity (at 700 nm or less) of the xenon lamp is around 500 nm, which meets the object of the present invention.
In addition, when using xenon lamp light, you may irradiate through the wavelength filter which cuts the light outside a visible light range. In addition, a filter having a high absorption coefficient in single crystal silicon and blocking visible light of 450 nm or less is also effective for process stabilization. In order to suppress the occurrence of the aforementioned blisters, it is desirable to perform batch irradiation on the entire surface of the SOS substrate bonded with the xenon lamp light. By batch irradiation, it becomes easy to prevent stress localization of the bonded SOS substrate and to prevent the bonded SOS substrate from being destroyed. Therefore, it is important to irradiate the xenon lamp light so as not to cause thermal peeling, and then perform mechanical peeling. Alternatively, prior to the irradiation of the xenon lamp light, a mechanical shock is applied to the edge of the bonded SOS substrate and the vicinity of the bonded surface, and the thermal shock caused by the irradiation of the xenon lamp light starts from the mechanical shock starting point of the edge. It is important to cause destruction at the ion implantation interface over the entire surface of the bonded SOS substrate.

If the transfer of the silicon thin film to the sapphire substrate cannot be confirmed after laser light irradiation, RTA or flash lamp irradiation, it is peeled along the interface by applying a mechanical impact to the interface of the ion implanted layer. Transfer thin film to sapphire substrate.
In order to give a mechanical impact to the interface of the ion-implanted layer, for example, a jet of a fluid such as a gas or a liquid may be sprayed continuously or intermittently from the side surface of the wafer. However, mechanical peeling occurs due to the impact. The method is not particularly limited.
By the peeling process, the SOS substrate 8 of the present invention in which the single crystal silicon thin film 4 is formed on the sapphire substrate 3 is obtained.

Since a damaged layer of about 150 nm remains on the surface of the single crystal silicon thin film immediately after the peeling, it is preferable to perform CMP polishing. Removing all damaged layers by polishing increases the film thickness variation, so in the actual process, most of them are removed by chemical etching, and then the surface is mirror-finished by mirror finish polishing. The method is reasonable.
The etching solution used for the chemical etching is preferably one or a combination of two or more selected from the group consisting of ammonia peroxide, ammonia, KOH, NaOH, CsOH, TMAH, EDP, and hydrazine. In general, an organic solvent has a slower etching rate than an alkaline solution, and is therefore suitable when precise etching amount control is required.
Since CMP polishing is performed in order to make the surface a mirror surface, polishing of 30 nm or more is generally performed.
After the CMP polishing and mirror finish polishing, cleaning by a wet process such as RCA cleaning or spin cleaning; and / or cleaning by a dry process such as UV / ozone cleaning or HF vapor cleaning may be performed.

A silicon substrate (thickness: 625 um) having an oxide film grown in advance with a thickness of 200 nm is implanted with hydrogen ions at 57 keV and a dose of 6.0 × 10 ¹⁶ atoms / cm ² , and ion beam activation is performed on both surfaces of the sapphire substrate. The film was processed at 150 ° C. The substrate was heat-treated at 225 ° C. for 24 hours for temporary bonding, and then irradiated with a green laser having a wavelength of 532 nm from the sapphire substrate side at 200 ° C. The laser condition at this time is 20 J / cm ² . After irradiating the entire surface of the substrate, the silicon thin film was transferred to sapphire by applying mechanical impact to the bonding interface and peeling off. The transfer of the silicon thin film to the entire surface of the substrate was confirmed. The silicon layer of this substrate was subjected to CMP polishing to a thickness of 200 nm, and the number of defects was counted by the Seco defect detection method / selective etching method at the center and outer periphery of the substrate. The number of pits confirmed by an optical microscope was 3 × 10 ³ / It was about from cm ² to 5 × 10 ³ pieces / cm ² . An appearance photograph of the bonded SOS produced by this method is shown in FIG. Moreover, since peeling / transfer is defined at the ion implantation interface, the film thickness variation after transfer is suppressed, and it is 5 nm or less. The film thickness variation after mirror finishing (CMP) was 20 nm or less.

A silicon substrate (thickness: 625 um) having a diameter of 150 mm on which an oxide film has been grown in advance is implanted with hydrogen ions at 57 keV and a dose of 6.0 × 10 ¹⁶ atoms / cm ² to activate plasma on both surfaces of the sapphire substrate. It processed and bonded together at 200 degreeC. The substrate was heat-treated at 225 ° C. for 24 hours for temporary bonding, and then irradiated with a xenon flash lamp from the sapphire substrate side at 250 ° C. After irradiating the entire surface of the substrate, the silicon thin film was transferred to sapphire by applying mechanical impact to the bonding interface and peeling off. The transfer of the silicon thin film to the entire surface of the substrate was confirmed. When the silicon layer of this substrate was etched (ammonia peraqueous solution) and CMP polishing to a thickness of 200 nm, and the number of defects was counted by the Seco defect detection method / selective etching method at the center and outer periphery of the substrate, 4 × 10 ³ / cm It was about ² to 8 × 10 ³ pieces / cm ² . Together with the results of Example 1, the defect density is summarized in Table 1 and FIG.

  Further, since peeling and transfer are defined at the ion implantation interface for all samples, the film thickness variation after transfer was suppressed and was 5 nm or less. The film thickness variation after mirror finishing (CMP) was 20 nm or less.

A silicon substrate (thickness: 625 um) having a diameter of 150 mm on which an oxide film has been grown in advance is implanted with hydrogen ions at 57 keV and a dose of 6.0 × 10 ¹⁶ atoms / cm ² , and UV ozone activity is applied to both surfaces of the sapphire substrate. The paste was treated at 100 ° C. The substrate was heat-treated at 225 ° C. for 24 hours for temporary bonding, and then irradiated with a xenon flash lamp from the sapphire substrate side at 175 ° C. After irradiating the entire surface of the substrate, the silicon thin film was transferred to sapphire by applying mechanical impact to the bonding interface and peeling off. EDP and CMP polishing were performed to make the film thickness about 250 nm. Since peeling and transfer are defined at the ion implantation interface, the film thickness variation after the transfer was suppressed, and it was 5 nm or less. The film thickness variation after mirror finishing (CMP) was 20 nm or less. A cross-sectional TEM (transmission electron microscope) photograph of this substrate was taken at two locations, the center and the outer periphery. No defects were observed in the narrow field of view at the TEM level. This photograph is shown in FIG.

A silicon substrate (thickness: 625 um) having a diameter of 150 mm on which an oxide film has been grown in advance is implanted with hydrogen ions at 57 keV and a dose of 6.0 × 10 ¹⁶ atoms / cm ² , and UV ozone activity is applied to both surfaces of the sapphire substrate. The paste was treated at 100 ° C. The substrate was heat-treated at 225 ° C. for 24 hours to perform temporary bonding, and then subjected to RTA treatment from the sapphire substrate side at 175 ° C. The temperature rising rate was 50 ° C./second, and the temperature was lowered when the silicon layer reached 800 ° C. The silicon thin film was transferred to sapphire by applying mechanical impact to the bonding interface and peeling off. EDP and CMP polishing were performed to make the film thickness about 250 nm. Since peeling and transfer are defined at the ion implantation interface, the film thickness variation after the transfer was suppressed, and it was 5 nm or less. The film thickness variation after mirror finishing (CMP) was 20 nm or less.

A silicon substrate (thickness: 625 um) having a diameter of 150 mm on which an oxide film has been grown in advance is implanted with hydrogen ions at 57 keV and a dose of 6.0 × 10 ¹⁶ atoms / cm ² , and UV ozone activity is applied to both surfaces of the sapphire substrate. The paste was processed and pasted. The substrate was heat-treated at 225 ° C. for 24 hours for temporary bonding, and then irradiated with a halogen lamp from the sapphire substrate side and spike annealed at 100 ° C./second. After irradiating the entire surface of the substrate, the silicon thin film was transferred to sapphire by applying mechanical impact to the bonding interface and peeling off. CMP polishing was performed to a film thickness of about 250 nm. Since peeling and transfer are defined at the ion implantation interface, the film thickness variation after the transfer was suppressed, and it was 5 nm or less. The film thickness variation after mirror finish (CMP) was 20 nm or less.

The claims of the original application of the original application (Japanese Patent Application No. 2009-130969) are as follows.
[Claim 1] A single crystal silicon thin film is provided on a sapphire substrate, and the defect density on the surface of the single crystal silicon thin film measured by the Secco defect detection method and the selective etching defect detection method is 10 ⁴ / cm 2. A silicon-on-sapphire (SOS) substrate that is ² or less.
[2] The SOS substrate according to [1], wherein the thickness of the single crystal silicon thin film exceeds 100 nm.
[3] The SOS substrate according to [1] or [2], wherein a silicon oxide film is sandwiched between the single crystal silicon thin film and the sapphire substrate.
[4] The SOS substrate according to any one of [1] to [3], wherein the single crystal silicon thin film has a thickness variation of 20 nm or less.
[5] The SOS substrate according to any one of [1] to [4], which is obtained by a bonding method.
[Claim 6] A bonded SOS substrate having a semiconductor thin film on the surface of a sapphire substrate,
Providing the sapphire substrate and the semiconductor substrate;
A step of implanting ions from the surface of the semiconductor substrate to form an ion implantation layer;
Applying a surface activation treatment to the surface of the sapphire substrate and at least one of the surfaces of the semiconductor substrate implanted with the ions;
Bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at 50 ° C. or higher and 350 ° C. or lower;
A step of applying a heat treatment of 200 ° C. or higher and 350 ° C. or lower as a maximum temperature to the bonded substrates to obtain a bonded body;
The bonded body is placed at a temperature higher than the bonding temperature, and the interface of the ion implantation layer is made brittle by irradiating visible light toward the ion implantation layer of the semiconductor substrate from the sapphire substrate side or the semiconductor substrate side, A bonded SOS substrate obtained by a process of transferring a semiconductor thin film.
[7] The surface activation treatment is performed by any one of ozone water treatment, UV ozone treatment, ion beam treatment, plasma treatment, or a combination of two or more of these. A bonded SOS substrate as described in 1.
[8] The bonded SOS substrate according to [6] or [7], wherein the substrate temperature at the time of irradiation with visible light is 30 to 100 ° C. higher than the temperature at the time of bonding.
[9] The method according to any one of [6] to [8], further comprising the step of applying a mechanical impact to the interface of the ion implantation layer after the irradiation with visible light and peeling the substrate bonded along the interface. A bonded SOS substrate according to any one of the above.
[10] The bonding according to any one of [6] to [9], further including a step of applying a mechanical impact in the vicinity of the bonding interface of the terminal portion of the joined body prior to the irradiation with visible light. SOS substrate.
[11] The bonded SOS substrate according to any one of [6] to [10], wherein the semiconductor substrate is single crystal silicon or silicon on which an oxide film is grown.
[12] The bonded SOS substrate according to any one of [6] to [11], wherein the visible light is laser light.
[13] The bonded SOS substrate according to any one of [6] to [11], wherein the visible light is RTA (Rapid Thermal Anneal) including spike annealing.
[14] The bonded SOS substrate according to any one of [6] to [11], wherein the visible light is flash lamp light.
[Claim 15] The implanted ions are hydrogen atom ions (H ⁺ ), and the dose is 1 × 10 ¹⁶ atoms / cm ² or more and 1 × 10 ¹⁷ atoms / cm ² or less. The bonded SOS substrate according to any one of 6 to 14.
[Claim 16] The implanted ions are hydrogen precursor molecular ions (H ₂ ⁺ ), and a dose amount is 5 × 10 ¹⁵ atoms / cm ² or more and 5 × 10 ¹⁶ atoms / cm ² or less. The bonded SOS substrate according to claim 6.
[17] The bonded SOS substrate according to any one of [6] to [16] obtained after the step of transferring, further by a step of chemical etching and / or polishing of the semiconductor thin film.
[18] A semiconductor device comprising the SOS substrate according to any one of [1] to [17].

1 Semiconductor substrate (silicon wafer)
2 Ion implantation layer 3 Sapphire substrate 4 Thin film layer 5 Silicon wafer 6 Bonded body 7 Oxide film 8 Bonded SOS substrate 9 Bonded interface

Claims (11)

A method for manufacturing a bonded SOS substrate comprising a semiconductor thin film on the surface of a sapphire substrate,
Providing the sapphire substrate and the semiconductor substrate;
A step of implanting ions from the surface of the semiconductor substrate to form an ion implantation layer;
Applying a surface activation treatment to the surface of the sapphire substrate and at least one of the surfaces of the semiconductor substrate implanted with the ions;
Bonding the surface of the semiconductor substrate and the surface of the sapphire substrate at 50 ° C. or higher and 350 ° C. or lower;
Adding a heat treatment of 200 ° C. or more and 350 ° C. or less as a maximum temperature to the bonded substrates, and obtaining a joined body;
The bonded body is placed at a temperature higher than the bonding temperature, and the interface of the ion implantation layer is made brittle by irradiating visible light toward the ion implantation layer of the semiconductor substrate from the sapphire substrate side or the semiconductor substrate side, A method for producing a bonded SOS substrate, comprising: transferring a semiconductor thin film, wherein the substrate temperature during irradiation with visible light is 30 ° C. to 100 ° C. higher than the temperature during bonding.   The bonding according to claim 1, wherein the surface activation treatment is performed by any one of ozone water treatment, UV ozone treatment, ion beam treatment, plasma treatment, or a combination of two or more thereof. A method for manufacturing an SOS substrate.   3. The attachment according to claim 1, further comprising a step of applying a mechanical impact to the interface of the ion implantation layer after the visible light irradiation and peeling the substrate bonded along the interface. A method for manufacturing a laminated SOS substrate.   The method for producing a bonded SOS substrate according to any one of claims 1 to 3, further comprising a step of applying a mechanical impact in the vicinity of a bonding interface of a terminal portion of the bonded body prior to the irradiation with visible light. .   The method for producing a bonded SOS substrate according to claim 1, wherein the semiconductor substrate is single crystal silicon or silicon on which an oxide film is grown.   The method for producing a bonded SOS substrate according to claim 1, wherein the visible light is laser light.   The method of manufacturing a bonded SOS substrate according to claim 1, wherein the visible light is RTA (Rapid Thermal Anneal) including spike annealing.   The method for producing a bonded SOS substrate according to claim 1, wherein the visible light is flash lamp light. 9. The method according to claim 1, wherein the implanted ions are hydrogen atom ions (H ⁺ ), and a dose is 1 × 10 ¹⁶ atoms / cm ² or more and 1 × 10 ¹⁷ atoms / cm ² or less. A method for producing a bonded SOS substrate according to claim 1. 10. The implanted ions are hydrogen primary molecular ions (H ₂ ⁺ ), and a dose amount is 5 × 10 ¹⁵ atoms / cm ² or more and 5 × 10 ¹⁶ atoms / cm ² or less. The manufacturing method of the bonding SOS board | substrate in any one of.   The method for manufacturing a bonded SOS substrate according to any one of claims 1 to 10, which is obtained by a step of performing chemical etching and / or polishing of the semiconductor thin film after the transferring step.