JP2014003158A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve safety of operation of a semiconductor integrated circuit device.SOLUTION: A semiconductor integrated circuit device comprises first and second external terminals to which the same power supply voltage is supplied, and a disconnection detection circuit. When the disconnection detection circuit detects that supply of the power supply voltage from the first external terminal is interrupted in a state where supply of the power supply voltage from the second external terminal is continued, control is made to stop an operation of the semiconductor integrated circuit device. Accordingly, the operation of the semiconductor integrated circuit device is secured by higher level safety.

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to an effective technique relating to a circuit for detecting disconnection of a power supply line for supplying power supply voltage.

  Regarding a semiconductor integrated circuit device, a technique for detecting disconnection of a power supply line for supplying power supply voltage is disclosed in Patent Document 1 below. This patent document 1 discloses a technique for monitoring a power supply voltage and detecting when the monitored power supply voltage exceeds an upper limit or a lower limit as a disconnection of a power supply line for power supply voltage supply.

JP-A-6-208693

  The technique described in Patent Document 1 has a problem in that it cannot be detected in the first place when a power supply voltage supply interruption to a disconnection detection circuit for detecting a disconnection of a power supply line for power supply voltage supply is caused. This problem can occur with high probability because the power supply line for power supply voltage supply for the disconnection detection circuit is disconnected, and the power supply to the disconnection detection circuit is stopped.

  The present inventor first provides two or more terminals provided outside the semiconductor integrated circuit device for supplying power supply voltage, and even if supply of power supply voltage from one terminal is interrupted due to disconnection, We thought to ensure the safety of the operation of the semiconductor integrated circuit device by supplying the power supply voltage from the terminal. However, even in such a system, the safety of the operation of the semiconductor integrated circuit device cannot be sufficiently ensured.

  The semiconductor integrated circuit device according to the first embodiment has first and second external terminals that receive the same power supply voltage and a disconnection detection circuit. The disconnection detection circuit receives a power supply voltage from the first and second external terminals. When the disconnection detection circuit detects that the supply of the power supply voltage from the first external terminal is interrupted while the supply of the power supply voltage from the second external terminal is continued, the operation of the semiconductor integrated circuit device is stopped. Are controlled in the same way.

  The operation of the semiconductor integrated circuit device can be ensured with a higher level of safety.

1 is a diagram illustrating a semiconductor integrated circuit device according to a first embodiment. 3 is a diagram for explaining an input voltage comparison circuit and a disconnection detection register according to the first embodiment; FIG. FIG. 4 is a diagram illustrating an operation of the semiconductor integrated circuit device according to the first embodiment. FIG. 3 is a diagram showing a processing flow when a step line state is detected in an electronic system including the semiconductor integrated circuit device according to the first embodiment. FIG. 10 is a diagram showing a processing flow when a step line state is detected in an electronic system including the semiconductor integrated circuit device of the second embodiment. FIG. 6 is a configuration diagram of a semiconductor integrated circuit device according to a third embodiment. FIG. 10 is a diagram illustrating the operation of the semiconductor integrated circuit device according to the third embodiment. FIG. 6 is a configuration diagram of a semiconductor integrated circuit device according to a fourth embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation, timing chart, element step, operation step, etc.) are specifically indicated unless otherwise specified and considered to be clearly essential in principle. Not necessarily essential. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Note that portions or members having the same function are denoted by the same or related reference numerals throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
FIG. 1 is a diagram illustrating a semiconductor integrated circuit device according to the first embodiment.

  The microcomputer MCU has an internal circuit IN-C having a central processing unit CPU, a random access memory RAM, a nonvolatile memory ROM, a logic circuit Logic, and an analog circuit Analog. The microcomputer MCU is a semiconductor integrated circuit device IC formed on one semiconductor substrate.

  The central processing unit CPU controls the entire microcomputer MCU. The random access memory RAM is used as a work area for the central processing unit CPU and is used for storing various temporary data. The nonvolatile memory ROM stores programs and various control data used by the central processing unit CPU. The logic circuit Logic is a circuit for controlling the microcomputer MCU based on an instruction from the central processing unit CPU. The analog circuit Analog is a circuit that processes an analog signal based on an instruction from the central processing unit CPU.

  The logic circuit Logic includes an input voltage comparison circuit IPSCC described later and a disconnection detection circuit BDC having a disconnection detection register BDRES.

  FIG. 2 is a diagram for explaining the input voltage comparison circuit and the disconnection detection register of the first embodiment.

  The semiconductor integrated circuit device IC includes an A power supply terminal PST-A indicated by hatched hatching, a B power supply terminal PST-B indicated by hatched hatching, a power supply ring PSR indicated by hatched hatching, and an internal circuit IN-C.

  The power supply voltage VDD is supplied from the external power supply line E-PL of the semiconductor integrated circuit device IC to the A power supply terminal PST-A and the B power supply terminal PST-B as external power supply terminals of the semiconductor integrated circuit device IC. The power supply voltage VDD is supplied from the A power supply terminal PST-A to the power supply ring PSR through the A power supply line A-PL. The power supply voltage VDD is supplied from the B power supply terminal PST-B to the power supply ring PSR via the B power supply line B-PL. The power supply ring PSR has a ring shape surrounding the internal circuit IN-C, and supplies the power supply voltage VDD to the internal circuit IN-C. Therefore, the central processing unit CPU, random access memory RAM, nonvolatile memory ROM, logic circuit Logic, analog circuit Analog, and disconnection detection circuit BDC are connected from the A power supply terminal PST-A and B power supply terminal PST-B through the power supply ring PSR. The power supply voltage VDD is supplied. For ease of description, there are an input voltage comparison circuit IPSCC and a disconnection detection register BDRES surrounded by an alternate long and short dash line outside the internal circuit IN-C. However, these input voltage comparison circuit IPSCC and disconnection detection register BDRES are internal. It is actually arranged in the circuit IN-C. The disconnection detection circuit BDC is formed by the input voltage comparison circuit IPSCC and the disconnection detection register BDRES.

  The input voltage comparison circuit IPSCC has a control logic EOR, a noise filter NF, and a latch circuit LT.

  The control logic EOR receives the power supply voltage VDD from the point A of the A power supply line A-PL and the power supply voltage VDD from the point B of the B power supply line B-PL. Here, a line from the point A to the control logic EOR is a line L1, and a line from the point B to the control logic EOR is a line L2. The control logic EOR is configured by exclusive OR, and the output signal is output to the point C. The noise filter NF receives the output signal from the point C and outputs the output signal to the point D. The latch circuit LT receives the output signal from the point D at the clock input terminal. The power supply voltage VDD is supplied to the signal input terminal of the latch circuit LT. When even one pulse of the clock is input to the clock input terminal of the latch circuit LT, the output signal of the latch circuit LT is at a high level. To be. The disconnection detection register BDRES receives the output signal from the latch circuit LT, and stores the disconnection detection result. If the level is high, it indicates that the path from the ED point to the point A of the external power supply line E-PL or the path from the ED point to the point B is broken. It is shown that there was no disconnection in the route up to and the route from the ED point to the B point. Here, the route A is a route from the ED point to the A point, and the route B is a route from the ED point to the B point.

  The noise filter NF includes a resistor R, a capacitor C, and a hysteresis comparator HC. One end of the resistor R is connected to the point C, and the other end of the resistor R is connected to one end of the capacitor C. The other end of the capacitor C is grounded and supplied with the ground voltage GND. The other end of the resistor R is connected to the input of the hysteresis comparator HC. The output of the hysteresis comparator HC is connected to point D.

  FIG. 3 is a diagram illustrating the operation of the semiconductor integrated circuit device according to the first embodiment. The left graph in FIG. 3 represents the operating state (voltage state) of points A, B, C, and D when there is no disconnection, and the right graph in FIG. 3 shows the point A when the path A is disconnected. , B, C, and D points.

  As shown below, the disconnection detection circuit BDC compares the waveforms at the points A and B when the power supply of the semiconductor integrated circuit device IC is started up, so that the disconnection occurs when the waveform difference between the points A and B is large. It is judged.

  When the power supply of the semiconductor integrated circuit device IC rises when there is no disconnection, a power-on reset signal POR is input to the latch circuit LT, so that a signal indicating a non-disconnection state (low level) is output from the latch circuit LT, and disconnection detection is performed. A low level is output to the register BDRES, and information indicating a non-disconnection state is stored. The power-on reset signal POR is also supplied to the other internal circuit IN-C, and resets the entire semiconductor integrated circuit device IC. Next, as shown in the figure, the power supply voltage VDD at point A and the power supply voltage VDD at point B rise. Since it is not disconnected, point A receives power supply voltage VDD mainly from A power supply terminal PST-A, and point B receives power supply voltage VDD mainly from B power supply terminal PST-B. This rise becomes a waveform as shown in the waveform of point A or point B in the figure depending on the parasitic capacitance or parasitic resistance. The rising waveform at point A and the rising waveform at point B are almost the same. Therefore, since the rising waveform at point A and the rising waveform at point B overlap in almost the same shape, the output of the control logic EOR becomes almost low level, and the output waveform at point C becomes like the waveform at point C. Here, the threshold voltage Vth is a threshold voltage of the control logic EOR. As for the output from the point C, the signal at the point C which is at the high level for a short period of time by the filtering of the noise filter NF is also set to the low level, and the waveform at the point D which is the output of the noise filter NF is kept at the low level. This slight period is narrower than the filter width of the noise filter. Therefore, the disconnection detection register BDRES still stores information indicating the non-disconnection state. Thus, when the waveform difference between point A and point B is small, it is determined that there is no disconnection.

  When the power supply of the semiconductor integrated circuit device IC rises when the path A is disconnected, a power-on reset signal POR is input to the latch circuit LT, so that a signal indicating a non-disconnected state (low level) is generated in the latch circuit LT. Is output to the disconnection detection register BDRES, and information indicating a non-disconnection state is stored. The power-on reset signal POR is also supplied to the other internal circuit IN-C, and resets the entire semiconductor integrated circuit device IC. Next, as shown in the figure, the power supply voltage VDD at point A and the power supply voltage VDD at point B rise. Since the path A is disconnected, the point A mainly receives the power supply voltage VDD from the B power supply terminal PST-B, and the point B also receives the power supply voltage VDD mainly from the B power supply terminal PST-B. This rise becomes a waveform as shown in the waveform of point A or point B in the figure depending on the parasitic capacitance or parasitic resistance. The rising waveform at point B has a form that rises quickly to some extent because the power supply voltage VDD is supplied from point ED through path B. On the other hand, the rising waveform at point A passes from path ED through path B and further through power supply ring PSR. Since the power supply voltage VDD is supplied, the rise is considerably slow. This is because the parasitic capacitance and parasitic resistance of the path where the power supply voltage is supplied to the point A pass through the power supply ring PSR, compared to the values of the parasitic capacitance and parasitic resistance of the path where the power supply voltage VDD is supplied to the point B. Because. Therefore, since the rising waveform at point B exceeds the threshold voltage Vth earlier than the rising waveform at point A, the output of the control logic EOR is at a high level for a certain period, and the output waveform at point C is C point. It looks like a waveform. Even if the output from the point C passes through the noise filter NF, the high level is maintained for a certain period, and the waveform at the point D which is the output of the noise filter NF is in a high level state for a certain period. This certain period is wider than the filter width of the noise filter. Therefore, a high level is output to the disconnection detection register BDRES, and information indicating the disconnection state is stored. This stored information is read out by the central processing unit CPU. Thus, it is determined that there is a disconnection when the waveform difference between point A and point B is large.

  When the power supply of the semiconductor integrated circuit device IC rises when there is a break in the path B, the waveform states at the points A, B, C, and D are as follows. The state of the waveforms at points A, B, C, and D of the IC is such that the waveforms at points A and B are interchanged, and the other points C and D have the same waveform state. Become. The rising waveform at point A is supplied to the power supply voltage VDD from the ED point through the path A, so that it rises to a certain degree, while the rising waveform at the point B passes from the ED point through the path A and further through the power supply ring PSR. Since the power supply voltage VDD is supplied, the rise is considerably slow. This is because the parasitic capacitance and parasitic resistance of the path where the power supply voltage is supplied to the point B pass through the power supply ring PSR, compared to the values of the parasitic capacity and parasitic resistance of the path where the power supply voltage VDD is supplied to the point A. Because.

  FIG. 4 is a diagram showing a processing flow when a stepped line state is detected in the electronic system including the semiconductor integrated circuit device of the first embodiment.

  The electronic system ES1 includes a semiconductor integrated circuit device IC, a device D1, and a device D2. The semiconductor integrated circuit device IC controls the entire electronic system ES1 by exchanging signals with the devices D1 and D2.

  In step S0, the power-on operation of the semiconductor integrated circuit device IC is started. After the start-up operation is started, a power-on reset signal is input to the internal circuit IN-C. Thereafter, in step S1, a high level is output to the disconnection detection register BDRES in the form described with reference to FIG. 3, information indicating the disconnection state is stored, and this stored information is read out to the central processing unit CPU. Thus, it is detected that the supply of the power supply voltage VDD from the A power supply terminal or the B power supply terminal is stopped. When this detection occurs, the supply of the power supply voltage VDD from the A power supply terminal or the B power supply terminal is stopped, while the supply of the power supply voltage VDD from the remaining power supply terminal B power supply terminal or A power supply terminal is continued. It becomes a state. Although the semiconductor integrated circuit device IC is in an operable state, since the supply of the power supply voltage VDD from the A power supply terminal or the B power supply terminal is stopped, the operational safety (reliability) is reduced. It has become. Therefore, it is necessary to safely stop the operation of the electronic system. Further, it is better to notify the outside that a disconnection has occurred in the semiconductor integrated circuit device IC together with a safe operation stop. The information transmitted to the outside is preferably between step S2 and step S3 described below.

  After step S1, the power-on operation of the semiconductor integrated circuit device IC is completed. Thereafter, in step S2, the semiconductor integrated circuit device IC stores various information that needs to be left in the electronic system ES1 (for example, a non-volatile memory ROM, and the non-volatile memory ROM at this time can be rewritten to a flash memory or the like). Evacuated).

  After step S2, as step S3, the semiconductor integrated circuit device IC safely stops the operation of the electronic system ES1. A typical example of the electronic system ES1 in this case is an automobile. When this operation is stopped, the semiconductor integrated circuit device IC is still operating, but the devices D1 and D2, which are other components of the electronic system ES1, are stopped.

  After step S3, after confirming that the operation of the electronic system ES1 has been safely stopped in step S4, the semiconductor integrated circuit device IC stops its operation. Therefore, the electronic system ES1 is completely stopped.

  In the description of FIG. 4, the operation of the electronic system ES1 has been described. However, it can be changed to the following form. Replace electronic system ES1 with semiconductor integrated circuit device IC. Replace device D1 and device D2 with analog circuit Analog or logic circuit Logic (may be replaced with random access memory RAM or nonvolatile memory ROM). The semiconductor integrated circuit device IC is replaced with a central processing unit CPU. Thus, when the electronic system ES1 is the semiconductor integrated circuit device IC itself, the central processing unit CPU plays the role of the semiconductor integrated circuit device IC in FIG.

  The route A and the route B are branched from a common ED point, but may be formed as follows. A first sub external power supply line is provided on the path from the ED point on the external power supply line E-PL to the A power supply terminal PST-A, and B is located from a point different from the ED point on the external power supply line E-PL. A configuration may be employed in which a second sub external power supply line in the path to the power supply terminal PST-B is provided.

  The present embodiment has the following operational effects.

  The semiconductor integrated circuit device IC includes A power supply terminals PST-A and B power supply terminals PST-B that receive the same power supply voltage VDD, and a disconnection detection circuit BDC. The disconnection detection circuit BDC receives the power supply voltage VDD from the A power supply terminal PST-A and the B power supply terminal PST-B. When the disconnection detection circuit BDC detects that the supply of the power supply voltage VDD to the A power supply terminal PST-A is stopped while the supply of the power supply voltage VDD from the B power supply terminal PST-B is continued, the semiconductor integrated circuit Control is performed to stop the operation of the circuit device IC.

  Two or more power supply terminals (A power supply terminal PST-A and B power supply terminal PST-B) provided as external power supply terminals of the semiconductor integrated circuit device IC are provided, and supply of the power supply voltage VDD from one terminal is disconnected. Even if it is interrupted, the supply of the power supply voltage VDD from the other terminal ensures the operation safety of the semiconductor integrated circuit device IC. In order to ensure the operation of the semiconductor integrated circuit device IC at a higher level, it is detected that the supply of the power supply voltage VDD from one terminal is interrupted due to disconnection, and the operation of the semiconductor integrated circuit device IC is stopped. It is a mode to control. As a typical example of this control, when it is detected that supply of the power supply voltage VDD from one terminal has been interrupted (step S1), necessary information is saved (step S2), and the semiconductor integrated circuit device IC This is a fail-safe control operation (step S4) such as stopping the operation of the electronic system ES1 controlled by (step S3) and finally determining the operation of the semiconductor integrated circuit device IC. In order to perform the fail-safe control operation as described above, two or more external terminals (A power supply terminal PST-A and B power supply terminal PST-B) for supplying the power supply voltage VDD are provided. In addition, the semiconductor integrated circuit device IC needs a disconnection detection circuit BDC that detects that the supply of the power supply voltage VDD from one terminal is interrupted due to disconnection and holds this detection state.

  The disconnection detection circuit BDC compares the waveforms at points A and B when the power supply of the semiconductor integrated circuit device IC is started up, so that it is determined that there is a disconnection when the waveform difference between the points A and B is large. It has become.

  By detecting the disconnection at an early stage after the start-up process of the power supply is started, it is possible to perform control so as to stop the operation of the semiconductor integrated circuit device IC in a state where the current consumption of the semiconductor integrated circuit device IC is low. . This is because the central processing unit CPU can instruct the control not to increase the current consumption of the semiconductor integrated circuit device IC by reading out the detection of the disconnection at an early stage. As a result, the semiconductor integrated circuit device IC can operate even when the power supply voltage VDD is supplied from one terminal that is not disconnected, and the risk of malfunction caused by insufficient power supply can be avoided. Immediately after the power-on reset signal is input to the internal circuit IN-C, the current consumption is low, and the risk of malfunction caused by insufficient power supply can be avoided.

  The disconnection detection circuit BDC has an input voltage comparison circuit IPSCC and a disconnection detection register BDRES, and the control logic EOR of the input voltage comparison circuit IPSCC indicates whether or not the input signal level from the point A reaches the threshold voltage Vth, and the point B The output level of the control logic EOR is changed based on whether or not the input signal level reaches the threshold voltage Vth.

  The output level of the control logic EOR is changed based on whether or not the input signal level from the point A reaches the threshold voltage Vth and whether or not the input signal level from the point B reaches the threshold voltage Vth. Therefore, when there is a disconnection, the rise of the input signal to the control logic EOR that has passed through the power supply ring PSR becomes slower than the rise of the input signal to the control logic EOR that does not pass through the power supply ring PSR. The logic output level is changed. This can effectively detect disconnection.

  A noise filter NF that receives an output from the control logic EOR is included. As a result, various noises superimposed on the power supply voltage VDD, differences in power supply rising waveforms at points A and B due to differences in parasitic resistance and parasitic capacitance between the path A and path B, line A disconnection occurs because the output level of the control logic EOR is changed due to the difference in the signal waveform input to the control logic EOR due to the difference in parasitic resistance or parasitic capacitance between L1 and the line L2. The occurrence of false detection errors is suppressed. The reason why the output level of the control logic EOR is changed due to the above-mentioned reason is that the change is made in a short time, so that a signal in the state of no change is output from the point D due to the low-pass filter effect of the noise filter NF. is there. In particular, this effect is generated by the resistance R and capacitance C of the noise filter NF.

  The noise filter NF has a hysteresis comparator HC connected to a capacitor C and a resistor R. By the hysteresis comparator HC, the comparison value at which the output of the noise filter becomes high level and the comparison value at which the output becomes low level are different, and it becomes more resistant to noise.

  When the power-on reset signal POR is input to the latch circuit LT, a signal indicating a non-disconnection state is stored in the disconnection detection register BDRES from the latch circuit LT. A signal indicating the stage line state is fixedly input to the signal input terminal of the latch circuit LT, and the output of the noise filter NF is input to the clock input terminal. By the power-on reset signal POR, the output of the input voltage comparison circuit IPSCC is brought into a non-disconnected state. Further, a signal indicating the stage line state is fixedly input to the signal input terminal of the latch circuit LT, and the output of the noise filter NF is input to the clock input terminal, so that it is ensured that the stage line state is detected even once. The latch circuit LT outputs a signal indicating the stage line state, and information indicating the disconnection state is reliably stored in the disconnection detection register BDRES.

(Embodiment 2)
FIG. 5 is a diagram showing a processing flow when a stepped line state is detected in an electronic system including the semiconductor integrated circuit device of the second embodiment.

  The electronic system ES2 includes a semiconductor integrated circuit device SoC as a system LSI, a semiconductor integrated circuit device IC, a device D1, and a device D2. The semiconductor integrated circuit device SoC controls the entire electronic system ES2 by exchanging signals with the semiconductor integrated circuit device IC, the device D1, and the device D2.

  Step S0 and step S1 are the same as those in the first embodiment, but step S2 and step S5 are performed after step S1. Step S6 is performed after step S2 as in the first embodiment. Step S7 is performed after step S6 and step S5. After step S7, step S8 is performed.

  After step S1, step S5 is performed in the following manner. The semiconductor integrated circuit device IC transmits the disconnection detection result stored in the disconnection detection register BDRES to the semiconductor integrated circuit device SoC as the system LSI.

  After step S2, step S6 is performed in the following manner. The semiconductor integrated circuit device IC notifies the semiconductor integrated circuit device SoC of the completion of saving the information necessary for the electronic system ES2.

  After step S5 and step S6, as step S7, the semiconductor integrated circuit device SoC safely stops the operation of the electronic system ES2. When the electronic system ES2 is stopped, the semiconductor integrated circuit device IC is also stopped. A typical example of the electronic system ES2 in this case is an automobile. When this operation is stopped, the semiconductor integrated circuit device SoC is still in a moving state. The other components of the electronic system ES2, the device D1, the device D2, and the semiconductor integrated circuit device IC are in a stopped state.

After step S7, as step S8, after confirming that the electronic system ES2 has safely stopped operating, the semiconductor integrated circuit device SoC stops itself. Therefore, the electronic device ES2 is completely stopped.
In addition, although it described that step S2 was the same as that of Embodiment 1, step S2 was made into step S21 as follows, and also the following steps were carried out as step S9 between step S5 and step S7. There may be. In step S21, various information to be stored in the semiconductor integrated circuit device IC (information related to the semiconductor integrated circuit device IC) is rewritten to any storage device (for example, a nonvolatile memory, and the nonvolatile memory at this time is a flash memory or the like). It is composed of possible things.) It is a step of evacuation. Further, as step S9, after step S5, the semiconductor integrated circuit device SoC saves various information (information related to the electronic system ES2 outside the semiconductor integrated circuit device IC) that needs to remain in the electronic system ES2 to some storage device. . After that, it is possible to confirm the end of the processing in step S9 and step S6 and proceed to step S7.

Furthermore, step S7 and step S8 may be replaced with step S71 as shown below.
After step S5 and step S6, the semiconductor integrated circuit device SoC stops the operation of the semiconductor integrated circuit device IC, and continues with the operation of the electronic system ES2 without using the function using the semiconductor integrated circuit device IC. May be executed. As a typical example in this case, the electronic system ES2 is an automobile, the semiconductor integrated circuit device IC is a semiconductor integrated circuit device for car navigation control, and the car navigation is not used in step S71.

  Even when the entire electronic system ES2 is not controlled by the semiconductor integrated circuit device IC as in the present embodiment, but is controlled by the semiconductor integrated circuit device LSI, step S7 is performed after step S6 or step S5. As a result, the safety of the operation of the semiconductor integrated circuit device IC can be improved, and the safety of the operation of the electronic system ES2 can be improved.

(Embodiment 3)
FIG. 6 is a configuration diagram of the semiconductor integrated circuit device according to the third embodiment.

  The difference from the semiconductor integrated circuit device IC of the first embodiment is that the semiconductor integrated circuit device IC2 of the present embodiment further includes a pull-down circuit PDC. The pull-down circuit PDC has an NMOS transistor NMOS1, an NMOS transistor NMOS2, an inverter INV, and an AND. The drain of the NMOS transistor NMOS1 is connected to the A power supply line A-PL, and the gates of the NMOS transistor NMOS1 and the NMOS transistor are connected to point E. The ground voltage GND is supplied to the sources of the NMOS transistors NMOS1 and NMOS2, and the drain of the NMOS transistor NMOS2 is connected to the B power supply line B-PL. A predetermined control signal is input to the inverter INV, the output of the inverter INV and the predetermined control signal are input to the AND AND, and the output of the AND AND is output to point E.

  FIG. 7 is a diagram illustrating the operation of the semiconductor integrated circuit device according to the third embodiment. The graph on the left side of FIG. 7 shows the operating state of points A, B, C, and D when there is no disconnection, and the graph on the right side of 73 shows points A, B, and C when the path A is disconnected. The operating state of point and point D is represented.

  As shown below, the disconnection detection circuit BDC compares the waveforms at the points A and B when the power source of the semiconductor integrated circuit device IC2 is started up, so that the disconnection occurs when the waveform difference between the points A and B is large. It is judged.

  When the power supply of the semiconductor integrated circuit device IC2 rises when there is no disconnection, a power-on reset signal POR is input to the latch circuit LT, so that a signal indicating a non-disconnection state (low level) is output from the latch circuit LT, and disconnection detection is performed. A low level is output to the register BDRES, and information indicating a non-disconnection state is stored. The power-on reset signal POR is also supplied to the other internal circuit IN-C, and resets the entire semiconductor integrated circuit device IC2. Next, as shown in the figure, the power supply voltage VDD at point A and the power supply voltage VDD at point B rise. Since it is not disconnected, point A receives power supply voltage VDD mainly from A power supply terminal PST-A, and point B receives power supply voltage VDD mainly from B power supply terminal PST-B. If there is no pull-down circuit PDC, this rise becomes a waveform shown by a dotted line as shown in the point A waveform and the point B waveform in the figure depending on the parasitic capacitance and the parasitic resistance. This is the same as the rising waveform at point A and the rising waveform at point B shown in FIG. Since there is actually a pull-down circuit PDC, the following occurs. First, a low level signal is input to the pull-down circuit PDC. Accordingly, a low level signal is input to one of the AND AND, and a high level signal inverted by the inverter INV is input to the other of the AND AND, so that the signal level at the point E becomes a low level. Next, the signal input to the pull-down circuit PDC is changed to a high level. Therefore, a high-level signal is input to one of AND AND. A low level signal inverted by the inverter INV is input to the other of the AND AND, but since the inverter INV has a predetermined delay time, the output of the inverter INV becomes a high level only for the predetermined delay time. . Therefore, the AND AND output becomes high level corresponding to a predetermined delay time, and then returns to low level, so that it becomes high level for a short time as shown in the point A waveform and the point B waveform. A signal is generated at point E. The NMOS transistor NMOS1 and NMOS transistor NMOS2 are turned on by being at the high level for a short time. Therefore, the power supply voltage VDD supplied from the A power supply terminal PST-A to the point A and the power supply voltage VDD supplied from the B power supply terminal PST-B to the point B are released to the ground. As indicated by the solid line, the waveforms at points A and B are substantially constant during a short high-level period. Therefore, since the rising waveform at point A and the rising waveform at point B overlap in almost the same shape, the output of the control logic EOR becomes almost low level, and the output waveform at point C becomes like the waveform at point C. Here, the threshold voltage Vth is a threshold voltage of the control logic EOR. As for the output from the point C, the signal at the point C which is at the high level for a short period of time by the filtering of the noise filter NF is also set to the low level, and the waveform at the point D which is the output of the noise filter NF is kept at the low level. This slight period is narrower than the filter width of the noise filter. Therefore, the disconnection detection register BDRES still stores information indicating the non-disconnection state. Thus, when the waveform difference between point A and point B is small, it is determined that there is no disconnection.

  When the power supply of the semiconductor integrated circuit device IC2 rises when the path A is disconnected, the power-on reset signal POR is input to the latch circuit LT, so that a signal indicating a non-disconnected state (low level) is generated in the latch circuit LT. Is output to the disconnection detection register BDRES, and information indicating a non-disconnection state is stored. The power-on reset signal POR is also supplied to the other internal circuit IN-C, and resets the entire semiconductor integrated circuit device IC2. Next, as shown in the figure, the power supply voltage VDD at point A and the power supply voltage VDD at point B rise. Since the path A is disconnected, the point A mainly receives the power supply voltage VDD from the B power supply terminal PST-B, and the point B also receives the power supply voltage VDD mainly from the B power supply terminal PST-B. If there is no pull-down circuit PDC, this rise becomes a waveform as shown by the dotted line of the point A waveform or the point B waveform in the figure depending on the parasitic capacitance and the parasitic resistance. This is because the rising waveform at the point B is supplied from the ED point through the path B so that the power supply voltage VDD rises to some extent, while the rising waveform at the point A passes through the path B from the ED point and further the power supply ring PSR. This is because the power supply voltage VDD is supplied through the power supply so that the rise is considerably slow. The parasitic capacitance and parasitic resistance of the path where the power supply voltage is supplied to the point A are larger than the value of the parasitic capacity and parasitic resistance of the path where the power supply voltage VDD is supplied to the point B as much as passing through the power supply ring PSR. Further, as described above, a high level signal is generated at point E for a short time. In this high level period, the power supply voltage VDD is supplied from the B power supply terminal PST-B close to the B point at the B point, so that the signal level at the B point is substantially constant, while the B point is far from the A point. Since the power supply voltage VDD is supplied from the power supply terminal PST-B through the power supply ring PSR, the signal level at the point A decreases. Therefore, the difference between the time when the rising waveform at the point A reaches the threshold voltage Vth and the time when the rising waveform at the point B reaches the threshold voltage Vth is larger than that described in the first embodiment with reference to FIG. Become. Therefore, the output of the control logic EOR is at the high level for a considerably long time, and the output waveform at the point C becomes like the waveform at the point C. Even if the output from the point C passes through the noise filter NF, the high level is maintained for a considerably long time, and the waveform at the point D, which is the output of the noise filter NF, is in a high level state for a considerably long time. This considerably long time is wider than the filter width of the noise filter. Therefore, a high level is output to the disconnection detection register BDRES, and information indicating the disconnection state is stored. This stored information is read out by the central processing unit CPU. Thus, it is determined that there is a disconnection when the waveform difference between point A and point B is large.

  When the power supply of the semiconductor integrated circuit device IC2 rises when there is a break in the path B, the waveform states at the points A, B, C, and D are as follows. In the state of the waveforms of points A, B, C and D of IC2, the waveforms of points A and B are interchanged, and other points C and D have the same waveform state. Become. Therefore, the time for the rising waveform at point A to reach the threshold voltage Vth is considerably earlier than the time for the rising waveform at point B to reach the threshold voltage Vth.

  In this manner, by providing the reset circuit, a signal that becomes a high level for a short time is generated at the point E. In the path that is disconnected during the short high level period, the signal level at point A or point B decreases, so that the output waveform at point C maintains a high level for a considerably long period. Therefore, disconnection detection can be performed more reliably.

(Embodiment 4)
FIG. 8 is a configuration diagram of the semiconductor integrated circuit device according to the fourth embodiment.

  The semiconductor integrated circuit device IC3 of the present embodiment is different from the semiconductor integrated circuit device IC of the first embodiment in that it includes a disconnection detection circuit BDC1 and a disconnection detection circuit BCD2. The disconnection detection circuit BDC1 includes an input voltage comparison circuit IPSCC1 and a disconnection detection register BDRES1. The disconnection detection circuit BDC2 includes an input voltage comparison circuit IPSCC2 and a disconnection detection register BDRES2. The input voltage comparison circuit IPSCC1 and the input voltage comparison circuit IPSCC have the same configuration as the input voltage comparison circuit IPSCC. The disconnection detection register BDRES1 and the disconnection detection register BDRES2 have the same configuration as the disconnection detection register BDRES. Therefore, the disconnection detection circuit BDC1 and the disconnection detection circuit BDC2 have the same configuration as the disconnection detection circuit BCD.

  The disconnection detection circuit BDC1 is disposed closer to the point A than the point B, and is disposed near the point A. The disconnection detection circuit BDC2 is disposed closer to the point B than the point A, and is disposed near the point B. The input voltage comparison circuit IPSCC1 receives one input from the point A via the line L1, and receives the other input from the point B via the line L2. Input voltage comparison circuit IPSCC2 receives one input from point A via line L3 and the other input from point B via line L4.

  If there is a disconnection in the path from the ED point to the A point of the external power supply line E-PL, the disconnection detection circuit BDC1 that receives the power supply voltage VDD from the power supply ring PSR in the vicinity of the A point may operate in an unstable manner. There is a possibility that the disconnection detection circuit BDC1 cannot detect the disconnection normally. This problem can be dealt with because the disconnection detection circuit BDC2 that receives the power supply voltage VDD from the power supply ring PSR near the point B does not operate so unstable, and the disconnection detection circuit BDC2 can detect the disconnection normally. If there is a disconnection in the path from the ED point to the B point of the external power supply line E-PL, the disconnection detection circuit BDC2 that receives the power supply voltage VDD from the power supply ring PSR in the vicinity of the B point may operate in an unstable manner. There is a possibility that the disconnection detection circuit BDC2 cannot detect the disconnection normally. This problem can be dealt with because the disconnection detection circuit BDC1 that receives the power supply voltage VDD from the power supply ring PSR in the vicinity of the point A is not so unstable that the disconnection detection circuit BDC1 can detect the disconnection normally. Thus, disconnection can be detected more reliably than in the first embodiment.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

MCU Microcomputer CPU Central processing unit RAM Random access memory ROM Non-volatile memory Logic Logic circuit Analog Analog circuit IC Semiconductor integrated circuit device IPSCC Input voltage comparison circuit BDRES Disconnection detection register BDC Disconnection detection circuit PST-A A power supply terminal PST-B B power supply Terminal PSR power supply ring EOR control logic NF noise filter LT latch circuit ES1 electronic system ES2 electronic system PDC pull-down circuit IPSCC1 input voltage comparison circuit BDRES1 disconnection detection register BDC1 disconnection detection circuit IPSCC2 input voltage comparison circuit BDRES2 disconnection detection register BDC2 disconnection detection circuit

Claims (10)

  A first power supply terminal and a second power supply terminal that receive the same power supply voltage, and a disconnection detection circuit, wherein the disconnection detection circuit is supplied with the power supply voltage from the first power supply terminal and the second power supply terminal, When the disconnection detection circuit detects that the supply of the power supply voltage from the first power supply terminal is interrupted while the supply of the power supply voltage from the second power supply terminal is continued, a semiconductor integrated circuit device Integrated circuit device controlled so as to stop the operation.   An internal circuit having the disconnection detection circuit; a power supply ring that supplies the power supply voltage to the internal circuit; a first power supply line that receives the power supply voltage from the first power supply terminal and supplies the power supply voltage to the power supply ring; A second power supply line that receives the power supply voltage from the second power supply terminal and supplies the power supply voltage to the power supply ring, and the first power supply line and the second power supply line when the power supply voltage rises 2. The semiconductor integrated circuit device according to claim 1, wherein the disconnection detection circuit determines disconnection of a power supply line to which the power supply voltage is supplied by comparing the waveforms.   The disconnection detection circuit includes an input voltage comparison circuit and a disconnection detection register, and whether or not the control logic of the input voltage comparison circuit reaches the threshold voltage of the signal level input from the first power supply line, and the second power supply 3. The semiconductor integrated circuit device according to claim 2, wherein an output level of the control logic is changed based on whether or not a signal level input from a line reaches the threshold voltage.   The semiconductor integrated circuit device according to claim 3, further comprising a noise filter that receives an output from the control logic.   5. The semiconductor integrated circuit device according to claim 4, further comprising: a latch circuit that receives an output of the noise filter, and a signal indicating a non-disconnection state is output from the latch circuit to the disconnection detection register by receiving a power-on reset signal. .   The noise filter has a resistor having one end connected to the output of the control logic, a capacitor having one end connected to the other end of the resistor and a ground voltage supplied to the other end, and an input connected to the other end of the resistor. 6. The semiconductor integrated circuit device according to claim 5, further comprising a hysteresis comparator. A pull-down circuit for supplying a ground voltage to the first power line and the second power line;
3. The semiconductor integrated circuit device according to claim 2, wherein when the power supply voltage is raised, the pull-down circuit supplies the ground voltage to the first power supply line and the second power supply line during a predetermined period. It further has another disconnection detection circuit different from the disconnection detection circuit,
The disconnection detection circuit is disposed closer to the first power supply line than the second power supply line, and the other disconnection detection circuit is disposed closer to the second power supply line than the first power supply line. The semiconductor integrated circuit device according to claim 2.   A first power supply terminal and a second power supply terminal that receive the same power supply voltage, a disconnection detection circuit, an internal circuit having the disconnection detection circuit, a power supply ring that supplies the power supply voltage to the internal circuit, and the first power supply A first power supply line for receiving the power supply voltage from a terminal and supplying the power supply voltage to the power supply ring; and a second power supply line for receiving the power supply voltage from the second power supply terminal and supplying the power supply voltage to the power supply ring. And the disconnection detection circuit determines the disconnection of the power supply line to which the power supply voltage is supplied by comparing the waveforms of the first power supply line and the second power supply line when the power supply voltage rises. Semiconductor integrated circuit device.   A first power supply terminal and a second power supply terminal that receive the same power supply voltage; an internal circuit to which the power supply voltage is supplied from the first power supply terminal and the second power supply terminal; and a disconnection detection circuit. When the disconnection detection circuit detects that the supply of the power supply voltage from the first power supply terminal is interrupted while the supply of the power supply voltage from the power supply terminal is continued, the operation of the internal circuit is performed. A semiconductor integrated circuit device controlled to stop.

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