JP2014001935A - Signal conversion device, and position detection apparatus using the same of in-reactor neutron flux detector - Google Patents

Signal conversion device, and position detection apparatus using the same of in-reactor neutron flux detector Download PDF

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JP2014001935A
JP2014001935A JP2012135317A JP2012135317A JP2014001935A JP 2014001935 A JP2014001935 A JP 2014001935A JP 2012135317 A JP2012135317 A JP 2012135317A JP 2012135317 A JP2012135317 A JP 2012135317A JP 2014001935 A JP2014001935 A JP 2014001935A
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JP6112786B2 (en
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Atsushi Saito
敦 齊藤
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a position detection apparatus capable of preventing reading of a wrong BCD signal in the midst of an A/D conversion process of the BCD signal output from an A/D converter that is used in the position detection device of an in-reactor neutron flux detector.SOLUTION: A timing generation part 6a of an FPGA 6 disposed for inputting a BCD signal 10 of an A/D converter 2 outputs an output timing signal 12a of a hold signal 12 to an A/D conversion part 6b; the hold function of the A/D converter 2 holds the BCD signal 10 for a first predetermined time Tto hold update of data at the final stage; when an input circuit part 6c disposed for inputting a read timing signal 16 reads the BCD signal held within a second predetermined time Tthat is within the range of the first predetermined time Tand also inputs a hold-canceling signal 13, update of data is restarted so that the FPGA 6 performs transmission to a card 4 and an external CPU 8 via a serial I/O 7.

Description

この発明は信号変換装置と、原子力発電所において原子炉内の中性子束を検出して原子炉の出力管理を行うためのデータを得る炉内核計装装置における中性子束検出器の位置検出装置に、前記信号変換装置を用いたものに係るものである。   The present invention relates to a signal conversion device and a position detection device for a neutron flux detector in an in-core nuclear instrumentation device that obtains data for detecting the neutron flux in a nuclear reactor and performing power management of the reactor at a nuclear power plant, The present invention relates to a device using the signal conversion device.

原子力発電所の炉内核計装装置においては、炉心内の燃料から放出される中性子束を測定するために、中性子検出器を先端部に具備したケーブルを、炉心内に設置された複数の検出器通路に挿入する。この検出器の位置を検出するため炉内核計装装置には、炉内核計装盤内に検出器位置検出装置が備えられている。これによって前記炉内の検出器の位置を検出するものであり、このような炉内核計装装置の構成は、例えば特許文献１に示されている。このような中性子束検出器の位置検出装置には、従来より炉内核計装装置の駆動機構に設けられたレゾルバからの検出器の位置信号をＢＣＤ５桁、２０ビッド信号に変換するＡ／Ｄ変換器が一般的に用いられている。   In an in-core nuclear instrumentation device of a nuclear power plant, in order to measure the neutron flux emitted from the fuel in the core, a plurality of detectors installed in the core are provided with cables having a neutron detector at the tip. Insert into the aisle. In order to detect the position of the detector, the in-core nuclear instrumentation device is provided with a detector position detection device in the in-core nuclear instrumentation board. Thus, the position of the detector in the furnace is detected, and the configuration of such an in-core nuclear instrumentation apparatus is disclosed in Patent Document 1, for example. Conventionally, the position detector of such a neutron flux detector is an A / D converter that converts the position signal of the detector from the resolver provided in the drive mechanism of the in-core nuclear instrumentation device into a BCD 5-digit, 20-bit signal. A vessel is commonly used.

特開平０１−２５００９８号公報Japanese Patent Laid-Open No. 01-250098

しかしながら従来の位置検出装置は、上記したようにＡ／Ｄ変換器の出力する信号をＢＣＤ５桁、２０ビッドの信号として扱っており、この２０ビッド信号はレゾルバから逐次伝送される正弦波、余弦波をデジタル化（２０ビッド）しており、Ａ／Ｄ変換の処理の途中において、異なったデータを読み込むという現象、例えば１２３４．１→１２３４．２・・・→１２３４．７→１２３４．８と変化し、次は当然１２３４．９と読み込むべきところを１２３５．０という異なったＢＣＤ信号データを読み込むという現象が発生していた。この現象は上記した、例えば１２３４．９→１２３５．０というような２０ビッド目と１ビッド目において発生しやすい。
前述した中性子束検出器の位置検出装置において、炉内核計装の制御上のしきい値近傍つまり、ある値で検出器の移動上限（下限）を停止しなければならないとする限界値近傍で、上記異なったＢＣＤ信号データを読み込むという現象が発生すると、制御上大きな問題を誘発しかねないという問題点がある。 However, the conventional position detection apparatus treats the signal output from the A / D converter as a BCD 5-digit, 20-bit signal as described above, and the 20-bit signal is a sine wave or cosine wave sequentially transmitted from the resolver. Is digitized (20 bids), and different data is read during the A / D conversion process, for example, 1234.1 → 1234.2... → 1234.7 → 1234.8 Then, the phenomenon of reading different BCD signal data, which is 1235.0, of course should be read as 1234.9 next. This phenomenon is likely to occur in the 20th and 1st bids as described above, for example, 1234.9 → 1235.0.
In the neutron flux detector position detection device described above, in the vicinity of the threshold value in the control of in-core nuclear instrumentation, that is, in the vicinity of the limit value that the upper limit (lower limit) of the detector must be stopped at a certain value, If the phenomenon of reading the different BCD signal data occurs, there is a problem in that it may induce a big problem in control.

この発明は上記のような課題を解決するためになされたものであって、Ａ／Ｄ変換器からのＢＣＤ信号の誤検出を防止可能とした信号変換装置を提供するとともに、この信号変換装置を用いた原子炉内中性子束検出器の位置検出装置を提供することを目的としている。   The present invention has been made to solve the above-described problems, and provides a signal converter that can prevent erroneous detection of a BCD signal from an A / D converter. It aims at providing the position detection apparatus of the used neutron flux detector in a nuclear reactor.

第１の発明に係る信号変換装置は、外部信号を受信するＡ／Ｄ変換器と、このＡ／Ｄ変換器が出力するＢＣＤ信号を入力するプリントカードと、このプリントカードの出力を入力するカードを備え、プリントカードにはＦＰＧＡとトランシーバが設けられており、ＦＰＧＡにはタイミング生成部とＡ／Ｄ変換制御部と入力回路部とが設けられ、タイミング生成部からのホールド信号の出力タイミング信号を入力するＡ／Ｄ変換制御部はＡ／Ｄ変換器にホールド信号を出力すると、Ａ／Ｄ変換器のホールド機能は最終出力段でのデータの更新を停止して、Ａ／Ｄ変換後のＢＣＤ信号を第１の所定の時間Ｔ１の範囲内において固定するとともに、タイミング生成部からの読み込みタイミング信号を入力する入力回路部が、第１の所定の時間Ｔ１の範囲内であって第２の所定の時間Ｔ２内に固定されたＢＣＤ信号の全ビッドの読み込みを完了し、タイミング生成部からのホールド解除信号の出力タイミング信号を入力するＡ／Ｄ変換制御部は、Ａ／Ｄ変換器にホールド解除信号を出力してＡ／Ｄ変換器は最終段でのデータの更新を再開するとともに、ＦＰＧＡは読み込んだＢＣＤ信号をシリアルデータ化しシリアルＩ／Ｏによりトランシーバを介してカードおよび外部に出力するものである。 A signal converter according to a first aspect of the present invention includes an A / D converter that receives an external signal, a print card that inputs a BCD signal output from the A / D converter, and a card that inputs the output of the print card The print card is provided with an FPGA and a transceiver, and the FPGA is provided with a timing generation unit, an A / D conversion control unit, and an input circuit unit, and outputs an output timing signal of a hold signal from the timing generation unit. When the input A / D conversion controller outputs a hold signal to the A / D converter, the hold function of the A / D converter stops updating the data at the final output stage, and the BCD after A / D conversion is fixed within the range signal of the first predetermined time T 1, the input circuit unit for inputting a read timing signal from the timing generation unit, a first predetermined time T 1 Complete reading of all bids in a range second fixed BCD signal to a predetermined time T 2, inputting the output timing signal of the hold release signal from the timing generator A / D conversion control section Outputs a hold release signal to the A / D converter, the A / D converter resumes updating the data at the final stage, and the FPGA converts the read BCD signal into serial data and transmits the transceiver by serial I / O. Via the card and externally.

第２の発明は、前記請求項１による信号変換装置が用いられているとともに、レゾルバと炉内核計装装置の制御装置とを備えた原子炉内中性子束検出器の位置検出装置であって、レゾルバの出力する原子炉内中性子束検出器の位置信号を入力する信号変換装置は、固定されたＢＣＤ信号を読み込みシリアルＩ／Ｏを介してシリアルデータを炉内核計装装置の制御装置に伝送するものである。   A second invention is a position detection device for an in-reactor neutron flux detector comprising the resolver and the control device for the in-core nuclear instrumentation device, wherein the signal conversion device according to claim 1 is used, A signal converter for inputting the position signal of the in-reactor neutron flux detector output from the resolver reads the fixed BCD signal and transmits the serial data to the control unit of the in-core nuclear instrumentation device via the serial I / O. Is.

第１の発明に係る信号変換装置は、上記のような構成を採用しているので、信号変換装置の外部から伝送される信号を正確に読み込むことが可能となり、信号の誤検出を防止でき信頼性の高い信号変換装置を得ることができる。
また第２の発明に係る原子炉内中性子束検出器の位置検出装置は上記のような構成を採用していることにより、原子炉内中性子束検出器の位置検出を正確に把握することが可能となり、Ａ／Ｄ変換後のＢＣＤ信号を誤って読み込むという現象を防止でき、特に原子炉内中性子束検出器が移動する上、下限の制御上のしきい値近傍における位置検出の信頼性が高まり、炉内核計装の制御の信頼性が向上する。 Since the signal conversion device according to the first invention employs the above-described configuration, it is possible to accurately read a signal transmitted from the outside of the signal conversion device, and to prevent erroneous detection of the signal. A highly efficient signal conversion device can be obtained.
Further, the position detection device for the in-reactor neutron flux detector according to the second invention can accurately grasp the position detection of the in-reactor neutron flux detector by adopting the above configuration. Thus, the phenomenon of erroneously reading the BCD signal after A / D conversion can be prevented. In particular, the in-reactor neutron flux detector moves and the reliability of position detection near the lower limit control threshold increases. In addition, the reliability of control of in-core nuclear instrumentation is improved.

実施の形態１による信号変換装置および実施の形態２による位置検出装置を示すブロック図である。It is a block diagram which shows the signal converter by Embodiment 1, and the position detection apparatus by Embodiment 2. FIG. 実施の形態１による授受される信号の関連を示す図である。It is a figure which shows the relationship of the signal transmitted / received by Embodiment 1. FIG. 実施の形態１によるＦＰＧＡの主要構成要素を示すブロック図である。FIG. 3 is a block diagram showing main components of the FPGA according to the first embodiment. 実施の形態１によるＡ／Ｄ変換器とＦＰＧＡとの間で授受される信号のタイミングチャートを示す図である。FIG. 3 is a diagram illustrating a timing chart of signals exchanged between the A / D converter and the FPGA according to the first embodiment.

実施の形態１．
以下、この発明による信号変換装置およびこの信号変換装置を用いた後述する原子炉内中性子束検出器の位置検出装置を図に基づいて説明する。
図１は、実施の形態１による信号変換装置５０およびこの信号変換装置５０を備えた後述する実施の形態２による原子炉内中性子束検出器の位置検出装置１００（以降、位置検出装置１００と称す）を示すブロック図である。後に詳述する位置検出装置１００はレゾルバ２０と信号変換装置５０と炉内核計装装置の制御装置５（以降、制御装置５と称す）とから構成されている。図示省略した原子炉内部に挿入された中性子束検出器の位置を前記レゾルバ２０が正弦波、余弦波のアナログ値の位置信号９として出力する。この位置信号９を外部信号として受信する実施の形態１による信号変換装置５０にはＡ／Ｄ変換器２と、前記位置信号９を扱う図示省略した機器類が統合化されたプリントカード３および状態表示パネル他の位置信号を扱うカード４とが設けられており、前記プリントカード３には論理回路のＦＰＧＡ（フィールド・プログラマブル・ゲートアレイ）６と、トランシーバ１１が設けられ、このトランシーバ１１の出力信号はシリアルＩ／Ｏ７を介し、カード４および外部の前記制御装置５に伝送される。前記トランシーバ１１はシリアルＩ／Ｏ７を介し、ＦＰＧＡ６の出力するシリアルデータ信号を受けて送信パケット生成、送信処理を行い、カード４や前記制御装置５のＣＰＵ８にシリアルＩ／Ｏ７を介してシリアルデータ信号を伝送する。 Embodiment 1 FIG.
Hereinafter, a signal converter according to the present invention and a position detector for an in-reactor neutron flux detector described later using the signal converter will be described with reference to the drawings.
FIG. 1 shows a signal conversion device 50 according to a first embodiment and a position detection device 100 (hereinafter referred to as a position detection device 100) of a neutron flux detector in a nuclear reactor according to a second embodiment that includes the signal conversion device 50 and will be described later. FIG. The position detection device 100 described in detail later includes a resolver 20, a signal conversion device 50, and a control device 5 (hereinafter referred to as the control device 5) of the in-core nuclear instrumentation device. The resolver 20 outputs the position of a neutron flux detector inserted into the reactor (not shown) as a position signal 9 having analog values of sine wave and cosine wave. The signal converter 50 according to the first embodiment that receives the position signal 9 as an external signal includes the A / D converter 2 and the print card 3 and the state in which devices not shown for handling the position signal 9 are integrated. A display panel and other cards 4 for handling position signals are provided. The print card 3 is provided with a logic circuit FPGA (Field Programmable Gate Array) 6 and a transceiver 11. Is transmitted to the card 4 and the external control device 5 via the serial I / O 7. The transceiver 11 receives a serial data signal output from the FPGA 6 via the serial I / O 7, generates a transmission packet, and performs transmission processing. The serial data signal is transmitted to the card 4 and the CPU 8 of the control device 5 via the serial I / O 7. Is transmitted.

図２に外部信号に担当するレゾルバ２０からの位置信号９と、Ａ／Ｄ変換器２およびＦＰＧＡ６との間で授受されるＢＣＤ信号１０の関連を示す。上記Ａ／Ｄ変換器２とＦＰＧＡ６とで授受される信号のタイミングは後に詳述する。
前記したようにレゾルバ２０が出力する位置信号９は正弦波、余弦波のアナログ値であり、これをＡ／Ｄ変換器２が受信しＢＣＤ信号１０に変換後ＦＰＧＡ６に出力する。このＦＰＧＡ６はＡ／Ｄ変換器２にＡ／Ｄ変換のホールド信号１２およびホールド解除信号を出力するとともに、前記ＢＣＤ信号１０を読み込み、前述の如くシリアルＩ／Ｏ７を介してシリアルデータ信号をトランシーバ１１に伝送する。 FIG. 2 shows the relationship between the position signal 9 from the resolver 20 in charge of the external signal and the BCD signal 10 exchanged between the A / D converter 2 and the FPGA 6. The timing of signals exchanged between the A / D converter 2 and the FPGA 6 will be described in detail later.
As described above, the position signal 9 output from the resolver 20 is an analog value of a sine wave or cosine wave, which is received by the A / D converter 2 and converted into the BCD signal 10 and output to the FPGA 6. The FPGA 6 outputs an A / D conversion hold signal 12 and hold release signal to the A / D converter 2, reads the BCD signal 10, and transmits the serial data signal via the serial I / O 7 as described above to the transceiver 11. Transmit to.

図３に、ＦＰＧＡ６の主要構成要素を示す。
図３において、タイミング生成部６ａは前記ホールド信号１２の出力タイミング信号１２ａおよびホールド解除信号１３の出力タイミング信号１３ａを生成し、この出力タイミング信号１２ａ、１３ａをＡ／Ｄ変換制御部６ｂに出力する。Ａ／Ｄ変換制御部６ｂは前記ホールド信号１２の出力タイミング信号１２ａを入力して、Ａ／Ｄ変換器２に第１の所定の時間Ｔ１内に最終出力段でのデータの更新停止とするホールド信号１２に出力する。この後、前記タイミング生成部６ａは入力回路部６ｃに対して読み込みタイミング信号１６を出力し、この入力回路部６ｃは前記第１の所定時間Ｔ１内であって第２の所定の時間Ｔ２内に全ビッド、この実施の形態では２０ビッドの読み込みを完了する。
読み込み完了後、タイミング生成部６ａはＡ／Ｄ変換制御部６ｂにホールド解除信号１３の出力タイミング信号１３ａを出力することにより、Ａ／Ｄ変換制御部６ｂがＡ／Ｄ変換器２にホールド解除信号１３を出力し、Ａ／Ｄ変換器２での最終出力段でのデータの更新動作が再開される。 FIG. 3 shows the main components of the FPGA 6.
In FIG. 3, the timing generator 6a generates an output timing signal 12a of the hold signal 12 and an output timing signal 13a of the hold release signal 13, and outputs the output timing signals 12a and 13a to the A / D conversion controller 6b. . A / D conversion control unit 6b receives the output timing signal 12a of the hold signal 12, and update stopping data in the final output stage a first predetermined time T 1 to the A / D converter 2 Output to hold signal 12. Thereafter, the timing generation unit 6a outputs a read timing signal 16 to the input circuit section 6c, the input circuit portion 6c is the first predetermined time T 1 within the A and the second predetermined time T 2 The reading of all the bids, that is, 20 bids in this embodiment is completed.
After the reading is completed, the timing generation unit 6a outputs the output timing signal 13a of the hold release signal 13 to the A / D conversion control unit 6b, whereby the A / D conversion control unit 6b sends the hold release signal to the A / D converter 2. 13 is output, and the data update operation at the final output stage in the A / D converter 2 is resumed.

上記Ａ／Ｄ変換器２とＦＰＧＡ６との間での授受される信号のタイミングチャートを図４に示す。
図４（ａ）は、ＦＰＧＡ６または信号変換装置５０の外部に設けられた図示省略されたクロックの出力する基本クロック信号を示し、この実施の形態１では、例えば２ｍｓｅｃの周期で出力される。
図４（ｂ）は前述したホールド信号１２を示す。このホールド信号１２を入力するＡ／Ｄ変換器２は、設けられているホールド機能によってＡ／Ｄ変換後のＢＣＤ信号１０を第１の所定の時間Ｔ１内ホールドする。ホールドする第１の所定の時間Ｔ１ｍｓｅｃは信号変換装置５０に設けられているＡ／Ｄ変換器２の固有の仕様である全ビッド（２０ビッド）の変換に要する時間Ｘ１ｍｓｅｃ、これを例えば１ｍｓｅｃとし、読み込みタイミング信号１６を入力する時間Ｘ２（数μｓｅｃ）との合計時間である第２の所定時間Ｔ２以上に相当する長さが設定されている。前述の如くこのＴ１ｍｓｅｃ間にわたり前記Ａ／Ｄ変換器２の最終出力段でのデータの更新がホールド（固定）されている。Ａ／Ｄ変換制御部６ｂがホールド信号１２を出力後、図４（ｃ）に示すように、前記全ビッド変換に要する時間Ｘ１ｍｓｅｃ経過後に、タイミング生成部６ａからの読み込みタイミング信号１６を入力する入力回路部６ｃは、図４（ｄ）のハッチングが施され前記Ｔ１ｍｓｅｃ間にわたりホールド（固定）された変換後のＢＣＤ信号１０を読み込む。この読み込み完了後に、前述した如くタイミング生成部６ａはホールド解除信号１３の出力タイミング信号１３ａをＡ／Ｄ変換制御部６ｂに出力し、このＡ／Ｄ変換制御部６ｂを介し、Ａ／Ｄ変換器２にホールド解除信号１３を出力することによりＡ／Ｄ変換器２による最終出力段でのデータ更新が再開される。 FIG. 4 shows a timing chart of signals exchanged between the A / D converter 2 and the FPGA 6.
FIG. 4A shows a basic clock signal output from a clock (not shown) provided outside the FPGA 6 or the signal converter 50. In the first embodiment, the basic clock signal is output at a cycle of 2 msec, for example.
FIG. 4B shows the hold signal 12 described above. The A / D converter 2 to which the hold signal 12 is input holds the BCD signal 10 after the A / D conversion within a first predetermined time T1 by the provided hold function. The first predetermined time T 1 msec to be held is the time X 1 msec required for conversion of all the bids (20 bids), which is a specific specification of the A / D converter 2 provided in the signal converter 50. For example, the length is set to 1 msec, and a length corresponding to a second predetermined time T 2 or more, which is a total time of the time X 2 (several μsec) for inputting the read timing signal 16, is set. As described above, updating of data at the final output stage of the A / D converter 2 is held (fixed) for T 1 msec. After the A / D conversion control unit 6b outputs the hold signal 12, as shown in FIG. 4C, the read timing signal 16 from the timing generation unit 6a is input after the time X 1 msec required for the all-bit conversion has elapsed. The input circuit section 6c to read in reads the converted BCD signal 10 that has been hatched in FIG. 4D and held (fixed) for T 1 msec. After completion of the reading, the timing generation unit 6a outputs the output timing signal 13a of the hold release signal 13 to the A / D conversion control unit 6b as described above, and the A / D converter via the A / D conversion control unit 6b. By outputting the hold release signal 13 to 2, the data update at the final output stage by the A / D converter 2 is resumed.

このようにこの実施の形態１による信号変換装置５０は、ＦＰＧＡ６が生成する信号によって、Ａ／Ｄ変換器２がＡ／Ｄ変換した後のＢＣＤ信号を第１の所定の時間Ｔ１ｍｓｅｃ内にわたりホールド（固定）し、この状態でのホールド（固定）されたＢＣＤ信号１０をＦＰＧＡ６に読み込むので、信号変換装置５０の外部から伝送される外部信号である例えばレゾルバ２０の位置信号９を正確に読み込むことが可能となり、位置信号９の誤検出を防止でき、信頼性の高い信号変換装置５０を得ることができる。
またＦＰＧＡ６以降の信号がシリアルＩ／Ｏ７で伝送されるので、安定したデータが送信されるとともに、ＦＰＧＡ６とトランシーバ１１とをプリントカード３に統合化しているので信号変換装置５０が小型化、可搬性の向上、低消費電力化、低コスト化が達成できるという効果がある。 As described above, the signal conversion apparatus 50 according to the first embodiment uses the signal generated by the FPGA 6 to convert the BCD signal after the A / D converter 2 performs A / D conversion within the first predetermined time T 1 msec. Since the BCD signal 10 held (fixed) in this state is read into the FPGA 6, the position signal 9 of the resolver 20, for example, an external signal transmitted from the outside of the signal converter 50 is accurately read. Thus, the erroneous detection of the position signal 9 can be prevented, and a highly reliable signal conversion device 50 can be obtained.
Further, since the signal after FPGA 6 is transmitted by serial I / O 7, stable data is transmitted and the FPGA 6 and the transceiver 11 are integrated into the print card 3, so that the signal converter 50 is reduced in size and portability. Improvement, low power consumption, and low cost can be achieved.

尚、上記実施例では、Ａ／Ｄ変換器２を５桁、２０ビッドのものを示したが、これに限らず、任意の桁数や１６ビッド、３２ビッドのＡ／Ｄ変換器２であってもよい。またＡ／Ｄ変換器２にホールド機能を設ける例を示したが、これに限らずＦＰＧＡ内にホールド回路を設け、Ａ／Ｄ変換器２の出力するＢＣＤ信号１０をＦＰＧＡ６内でホールドする機能を設けてもよい。
またさらに、上記実施例では基本クロックの１周期内においてＡ／Ｄ変換器２の固有の仕様による全ビッド変換に要する時間Ｘ１ｍｓｅｃ（１ｍｓｅｃ）後に、ホールド（固定）されたＢＣＤ信号１０を読み込むので、従来に比較して信号変換の回数が増加し、信号変換精度が向上するという効果もある。 In the above embodiment, the A / D converter 2 is shown as having 5 digits and 20 bits. However, the A / D converter 2 is not limited to this and is an A / D converter 2 having any number of digits and 16 bits and 32 bits. May be. Further, although an example in which a hold function is provided in the A / D converter 2 has been shown, the present invention is not limited to this, and a hold circuit is provided in the FPGA, and a function of holding the BCD signal 10 output from the A / D converter 2 in the FPGA 6 is provided. It may be provided.
Furthermore, in the above embodiment, the held (fixed) BCD signal 10 is read after a time X 1 msec (1 msec) required for all bid conversions according to the specific specification of the A / D converter 2 within one period of the basic clock. Therefore, the number of signal conversions is increased as compared with the conventional case, and the signal conversion accuracy is improved.

実施の形態２．
次に実施の形態２について説明する。
この実施の形態２は前述した実施の形態１による信号変換装置５０を、原子炉内中性子束検出器の位置検出装置（以降、位置検出装置と略す）に用いたものである。実施の形態１で説明した図１において、位置検出装置１００は図示省略した炉内核計装装置の駆動機構に設けられたレゾルバ２０と、このレゾルバ２０の出力する原子炉内中性子束検出器の位置信号９を入力する前述した実施の形態１の信号変換装置５０と、ＣＰＵ８を備えた炉内核計装装置の制御装置５とで構成されている。 Embodiment 2. FIG.
Next, a second embodiment will be described.
In the second embodiment, the signal conversion device 50 according to the first embodiment described above is used as a position detection device (hereinafter abbreviated as a position detection device) of the in-reactor neutron flux detector. In FIG. 1 described in the first embodiment, the position detection device 100 includes a resolver 20 provided in a drive mechanism of an in-core nuclear instrumentation device (not shown), and a position of an in-reactor neutron flux detector output from the resolver 20. The signal conversion device 50 according to the first embodiment that inputs the signal 9 and the control device 5 of the in-core nuclear instrumentation device including the CPU 8 are configured.

レゾルバ２０の出力する位置信号９は、信号変換装置５０のＡ／Ｄ変換器２に入力され、前述した実施の形態１と同様の動作によって信号変換がなされて、制御装置５にシリアルＩ／Ｏを介してデータが伝送される。
以上のような構成を採用することによって、原子炉内中性子束検出器の位置検出を正確に把握することが可能となり、従来技術のようにＡ／Ｄ変換後のＢＣＤ信号を誤って読み込むという現象を防止でき、特に原子炉内中性子束検出器が移動する上、下限の制御上のしきい値近傍における位置検出の信頼性が高まり、炉内核計装の制御の信頼性が向上するという効果がある。 The position signal 9 output from the resolver 20 is input to the A / D converter 2 of the signal converter 50, and signal conversion is performed by the same operation as in the first embodiment described above, and the serial I / O is sent to the controller 5. The data is transmitted via
By adopting the above configuration, it becomes possible to accurately grasp the position detection of the in-reactor neutron flux detector, and the phenomenon of erroneously reading the BCD signal after A / D conversion as in the prior art In particular, the in-reactor neutron flux detector moves, and the reliability of position detection near the lower limit control threshold increases, and the control reliability of in-core nuclear instrumentation improves. is there.

尚、この発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that within the scope of the present invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

２ Ａ／Ｄ変換器、３ プリントカード、４ カード、５ 制御装置、６ ＦＰＧＡ、
６ａ タイミング生成部、６ｂ Ａ／Ｄ変換制御部、６ｃ 入力回路、
７ シリアルＩ／Ｏ、８ ＣＰＵ、９ 位置信号、１０ ＢＣＤ信号、
１１ トランシーバ、１２ ホールド信号、
１２ａ ホールド信号の出力タイミング信号、１３ ホールド解除信号、
１３ａ ホールド解除信号の出力タイミング信号、１６ 読み込みタイミング信号、
２０ レゾルバ、５０ 信号変換装置、１００ 位置検出装置、Ｔ 第１の所定の時間、
Ｘ１ 全ビッド変換に要する時間、Ｘ２ 読み込みタイミング信号入力に要する時間。 2 A / D converter, 3 print card, 4 card, 5 control device, 6 FPGA,
6a timing generator, 6b A / D conversion controller, 6c input circuit,
7 Serial I / O, 8 CPU, 9 Position signal, 10 BCD signal,
11 transceiver, 12 hold signal,
12a Hold signal output timing signal, 13 Hold release signal,
13a Hold release signal output timing signal, 16 read timing signal,
20 resolver, 50 signal converter, 100 position detector, T first predetermined time,
X 1 the time required for the entire bid conversion, the time required for X 2 read timing signal input.

Claims (4)

外部信号を受信するＡ／Ｄ変換器と、このＡ／Ｄ変換器が出力するＢＣＤ信号を入力するプリントカードと、このプリントカードの出力を入力するカードを備えた信号変換装置において、
前記プリントカードにはＦＰＧＡとトランシーバが設けられており、前記ＦＰＧＡにはタイミング生成部とＡ／Ｄ変換制御部と入力回路部とが設けられ、前記タイミング生成部からのホールド信号の出力タイミング信号を入力する前記Ａ／Ｄ変換制御部は前記Ａ／Ｄ変換器に前記ホールド信号を出力すると、前記Ａ／Ｄ変換器のホールド機能は最終出力段でのデータの更新を停止して、Ａ／Ｄ変換後のＢＣＤ信号を第１の所定の時間Ｔ１の範囲内において固定するとともに、前記タイミング生成部からの読み込みタイミング信号を入力する前記入力回路部が、前記第１の所定の時間Ｔ１の範囲内であって第２の所定の時間Ｔ２内に前記固定されたＢＣＤ信号の全ビッドの読み込みを完了し、前記タイミング生成部からのホールド解除信号の出力タイミング信号を入力する前記Ａ／Ｄ変換制御部は、前記Ａ／Ｄ変換器に前記ホールド解除信号を出力して前記Ａ／Ｄ変換器は最終段でのデータの更新を再開するとともに、前記ＦＰＧＡは前記読み込んだＢＣＤ信号をシリアルデータ化しシリアルＩ／Ｏにより前記トランシーバを介して前記カードおよび外部に出力することを特徴とする信号変換装置。 In a signal converter including an A / D converter that receives an external signal, a print card that inputs a BCD signal output from the A / D converter, and a card that inputs an output of the print card,
The print card includes an FPGA and a transceiver, and the FPGA includes a timing generation unit, an A / D conversion control unit, and an input circuit unit, and outputs an output timing signal of a hold signal from the timing generation unit. When the input A / D conversion control unit outputs the hold signal to the A / D converter, the hold function of the A / D converter stops updating the data at the final output stage, and the A / D converter The converted BCD signal is fixed within the range of the first predetermined time T 1 , and the input circuit unit that inputs the read timing signal from the timing generation unit has the first predetermined time T 1 . second to complete the reading of all the bids of the fixed BCD signal to a predetermined time T in 2 in a range of hold release signal from the timing generator The A / D conversion control unit that inputs a power timing signal outputs the hold release signal to the A / D converter, and the A / D converter restarts updating of data in the final stage, and The FPGA converts the read BCD signal into serial data and outputs it to the card and the outside via the transceiver by serial I / O. 前記請求項１による信号変換装置が用いられているとともに、レゾルバと炉内核計装装置の制御装置とを備えた原子炉内中性子束検出器の位置検出装置であって、
前記レゾルバの出力する前記原子炉内中性子束検出器の位置信号を入力する前記信号変換装置は、前記固定されたＢＣＤ信号を読み込みシリアルＩ／Ｏを介してシリアルデータを前記炉内核計装装置の制御装置に伝送することを特徴とする原子炉内中性子束検出器の位置検出装置。 A signal converter according to claim 1 is used, and a position detecting device for an in-reactor neutron flux detector comprising a resolver and a control device for an in-core nuclear instrumentation device,
The signal converter for inputting the position signal of the in-reactor neutron flux detector output from the resolver reads the fixed BCD signal and transmits serial data via serial I / O to the in-core nuclear instrumentation device. A position detection device for a neutron flux detector in a nuclear reactor, which is transmitted to a control device. 前記第２の所定の時間Ｔ２は前記Ａ／Ｄ変換器の固有の仕様である全ビッド読み込みに要する時間Ｘ１と、前記読み込んだタイミング信号を入力するのに要する時間Ｘ２との和であり、前記第１の所定の時間Ｔ１は、前記第２の所定の時間Ｔ２より長くかつ、クロックが出力する基本クロック信号の１周期以内であることを特徴とする請求項１に記載の信号変換装置。 The second predetermined time T 2 is a sum of a time X 1 required for reading all bids, which is a specific specification of the A / D converter, and a time X 2 required for inputting the read timing signal. There, the first predetermined time T 1, the second and longer than the predetermined time T 2, according to claim 1, characterized in that within one cycle of the basic clock signal the clock output Signal converter. 最終出力段でのデータの更新を停止する前記ホールド機能は、前記Ａ／Ｄ変換器に代替して前記ＦＰＧＡに設けられていることを特徴とする請求項１に記載の信号変換装置。 The signal conversion apparatus according to claim 1, wherein the hold function for stopping updating of data at a final output stage is provided in the FPGA in place of the A / D converter.
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