JP2002353812A - High-speed ad conversion signal processing unit, rf receiver circuit, digital receiver front end circuit, mri device and high-speed analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed ad conversion signal processing unit that properly transfers digital data from a high-speed analog/digital converter to a digital signal processing section. SOLUTION: A dual clock synchronization type FIFO 34 stores digital data in a timing when a high-speed analog/digital converter 21 outputs digital data D- AD (timing on the basis of a data ready signal DATA- RADY). Then digital data D- FIFO are read from the dual clock synchronization type FIFO 34 in an operating timing of a digital signal processing section 40 (timing on the basis of a digital signal processing clock signal CLK- DIG), and given to the digital signal processing section 40. Thus, even when there exists a timing difference between the timing when the high-speed analog/digital converter outputs digital data and the clock signal for digital signal processing used by the digital signal processing section, it is absorbed and the digital data can properly be given.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a high-speed AD (Analog
to Digital) conversion signal processor, RF (Radio Frequen)
cy) The present invention relates to a receiver circuit, a digital receiver front-end circuit, an MRI (Magnetic Resonance Imaging) device, and a high-speed AD converter. For more details, see High-speed AD
Even if there is a timing difference between the timing at which digital data is output from the converter and the clock signal for digital signal processing used in the digital signal processing unit, the difference is absorbed and the digital data is properly transmitted from the high-speed AD converter to the digital signal processing unit. High-speed AD conversion signal processing device that can be transferred, RF that can be used in the high-speed AD conversion signal processing device
The present invention relates to a receiver circuit, a digital receiver front-end circuit, an MRI device using the high-speed AD conversion signal processing device, and the like, and a high-speed AD conversion device that can be used in the high-speed AD conversion signal processing device.

[0002]

2. Description of the Related Art In recent years, digitization of signal processing has been promoted in MRI apparatuses. That is, the NMR signal received by the receiving coil is converted into digital data by a high-speed AD converter, and then passed to a digital signal processing unit. The digital signal processing unit performs digital signal processing (for example, digital filtering), and then passes the digital signal to a computer. A method for performing image reconstruction and the like has been developed.

[0003]

When digital data output from a high-speed AD converter is passed to a digital signal processing unit, the timing at which digital data is output from the high-speed AD converter and a clock signal for digital signal processing used in the digital signal processing unit And there is a timing shift. This timing shift naturally occurs when the high-speed AD converter clock signal and the digital signal processing clock signal are independently generated, but also occurs when one clock signal is distributed to both. The cause is high-speed A
An RF pulse transformer is used in the clock signal circuit for the high-speed AD converter to generate the differential RF clock signal required by the D-converter, and the timing at which digital data is output from the high-speed AD converter varies from device to device. And that the delay time of the digital data transmission system differs from the delay time of the clock signal transmission system. However, there is a problem that if the timing is shifted, digital data cannot be properly passed from the high-speed AD converter to the digital signal processing unit.

Therefore, a first object of the present invention is to provide a high-speed AD
Even if there is a timing difference between the timing at which the digital data is output from the converter and the digital signal processing clock signal used in the digital signal processing unit, the difference is absorbed and the digital data is transferred from the high-speed AD converter to the digital signal processing unit. It is an object of the present invention to provide a high-speed A / D conversion signal processing device that can pass the data properly. Further, the second aspect of the present invention
The object of R is that R can be used in the high-speed AD conversion signal processing device.
An F receiver circuit and a digital receiver front end circuit are provided. A third object of the present invention is to provide an MRI apparatus using the high-speed AD conversion signal processing apparatus or the like. Furthermore, a fourth object of the present invention is to provide a high-speed AD converter which can be used in the high-speed AD conversion signal processing device.
A conversion device is provided.

[0005]

According to a first aspect of the present invention, there is provided a high-speed AD converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, and a digital signal processing for processing the digital data into a digital signal. And a digital signal processing clock signal for storing digital data output from the high-speed AD converter in synchronization with a data ready signal output from the high-speed AD converter and using the stored digital data in the digital signal processing unit And a data storage means for reading out the data in synchronization with the digital signal processing unit and transferring the data to the digital signal processing unit. The first
In the high-speed AD conversion signal processing device according to
The digital data is stored in the data storage means at a timing when the digital data is output from the converter (a timing based on the data ready signal). Then, the digital data is read out from the data storage unit at the operation timing of the digital signal processing unit (timing based on the digital signal processing clock signal) and passed to the digital signal processing unit. Thereby, even if there is a timing difference between the timing at which the digital data is output from the high-speed AD converter and the clock signal for digital signal processing used in the digital signal processing unit, the difference is absorbed through the data storage means. The digital data can be properly passed from the high-speed AD converter to the digital signal processing unit. In the above configuration, the “data ready signal” means a “signal indicating that it is an output period of valid data” output from the high-speed AD converter, and is sometimes called a “data valid signal”.

According to a second aspect of the present invention, in the high-speed A / D conversion signal processing device having the above-described configuration, the data storage means includes a dual clock synchronous type FIFO (First-In First First-In First-Out).
-Out), and a write control circuit for storing digital data output from the high-speed AD converter in response to the data ready signal in the dual-clock synchronous FIFO in response to a start signal instructing the start of storage; A read control circuit for reading digital data from the dual clock synchronous FIFO in synchronization with the digital signal processing clock signal in response to an empty signal output from the dual clock synchronous FIFO. Provided is a high-speed AD conversion signal processing device. In the high-speed AD conversion signal processing device according to the second aspect, by supplying a start signal from the outside, digital data output from the high-speed AD converter can be written into the dual-clock synchronous FIFO. And the digital data is a dual clock synchronous type FIFO.
The digital data is read from the dual-clock synchronous FIFO in response to the empty signal output when the data is written to the digital memory, so that the digital data can be appropriately passed from the high-speed AD converter to the digital signal processing unit.

According to a third aspect of the present invention, in the high-speed A / D conversion signal processing device having the above-described configuration, the read control circuit notifies the outside that digital data is being read from the dual clock synchronous FIFO. A high-speed A that generates and outputs a sync ready signal of
Provided is a D-converted signal processing device. In the high-speed AD conversion signal processing device according to the third aspect, the timing at which digital data is output from the dual clock synchronous FIFO can be known by monitoring the sync ready signal.

According to a fourth aspect of the present invention, there is provided a high-speed AD conversion signal processing device having the above-mentioned configuration, wherein a high-stable crystal oscillator and an RF clock signal for outputting an RF clock signal obtained by multiplying the frequency of an output signal of the high-stable crystal oscillator are provided. A multiplier circuit;
An RF pulse transformer for a high-speed AD converter that generates a differential RF clock signal from an F clock signal and uses the RF clock signal as a clock for the high-speed AD converter is provided. In the high-speed A / D conversion signal processing device according to the fourth aspect, the differential RF clock signal required by the high-speed A / D converter can be suitably generated.

According to a fifth aspect of the present invention, in the high-speed A / D conversion signal processing device having the above-described configuration, a separating RF pulse transformer for generating a separated clock signal electrically separated from the RF clock signal from the RF clock signal. And a comparator which generates the digital signal processing clock signal from the separated clock signal. The high-speed AD conversion signal processing device according to the fifth aspect can generate a differential RF clock signal and a digital signal processing clock signal required by the high-speed AD converter from one clock signal. In addition, since the separating RF pulse transformer is used, it is possible to prevent noise from entering one of the analog RF circuit and the digital circuit through the clock transmission system.

In a sixth aspect, the present invention provides a high-speed A / D conversion signal processing device having the above configuration, wherein the NMR signal received by the receiving coil is processed as an input analog signal by the high-speed A / D conversion signal processing device. A featured MRI apparatus is provided. In the MRI apparatus according to the sixth aspect, digitization of received signal processing can be favorably advanced.

In a seventh aspect, the present invention provides a high-speed A / D converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, a high-stable crystal oscillator, and a frequency of an output signal of the high-stable crystal oscillator. Multiplied RF
An RF multiplying circuit for outputting a clock signal, an RF pulse transformer for a high-speed AD converter for generating a differential RF clock signal from the RF clock signal and using the clock for the high-speed AD converter, and data output from the high-speed AD converter A clock driver for outputting a ready signal to the outside, a separating RF pulse transformer for generating a separated clock signal electrically separated from the RF clock signal from the RF clock signal, and a clock for digital signal processing from the separated clock signal An RF receiver comprising: a comparator for generating a signal; and a latch for holding and outputting digital data output from the high-speed AD converter in synchronization with a data ready signal output from the high-speed AD converter. Provide a circuit. If the RF receiver circuit according to the seventh aspect is used, digitization of the reception signal processing of the MRI apparatus can be favorably advanced.

In an eighth aspect, the present invention provides a first clock buffer for generating a data ready signal from a first input clock signal, and a digital signal processing clock signal from a second input clock signal and also to the outside. A second clock buffer for outputting, a latch for holding and outputting input digital data in synchronization with the data ready signal, and a digital memory for storing and storing digital data output from the latch in synchronization with the data ready signal Data storage means for reading and outputting data in synchronization with the digital signal processing clock signal. If the digital receiver front-end circuit according to the eighth aspect is used, digitization of the reception signal processing of the MRI apparatus can be favorably advanced.

According to a ninth aspect of the present invention, in the digital receiver front end circuit having the above configuration, the data storage means includes a dual clock synchronous FIFO and the input digital data in response to a start signal instructing a storage start. A write control circuit that stores the data in the dual clock synchronous FIFO in synchronization with the data ready signal, and digital data from the dual clock synchronous FIFO in response to an empty signal output from the dual clock synchronous FIFO. A digital receiver front-end circuit, comprising: a read control circuit that reads data in synchronization with a digital signal processing clock signal. If the digital receiver front-end circuit according to the ninth aspect is used, digitization of the reception signal processing of the MRI apparatus can be favorably advanced.

According to a tenth aspect of the present invention, in the digital receiver front-end circuit having the above-described configuration, the read control circuit is for externally notifying that digital data is being read from the dual clock synchronous FIFO. A digital receiver front-end circuit for generating and outputting a sync ready signal is provided.
If the digital receiver front-end circuit according to the tenth aspect is used, digitization of the reception signal processing of the MRI apparatus can be favorably advanced.

According to an eleventh aspect, the present invention provides an RF receiver circuit having the above-described configuration, a digital receiver front-end circuit having the above-described configuration, and a digital signal processing section. A digital signal input to the RF receiver circuit as a signal, digital data output from a latch of the RF receiver circuit input to the digital receiver front-end circuit as input digital data, and data ready output from a clock driver of the RF receiver circuit. A signal is input to the digital receiver front-end circuit as a first input clock signal, and a digital signal processing clock signal output from a comparator of the RF receiver circuit is input to the digital receiver front-end circuit as a second input clock signal. And the digital An MRI apparatus characterized in that digital data output from a dual clock synchronous FIFO of a sheather front end circuit and a digital signal processing clock signal output from the second clock buffer are input to the digital signal processing unit. I do. In the MRI apparatus according to the eleventh aspect, digitization of received signal processing can be favorably advanced.

In a twelfth aspect, the present invention provides an RF receiver circuit having the above-described configuration, a digital receiver front-end circuit having the above-described configuration, a digital signal processing section, and generating the start signal in accordance with a pulse sequence. A control logic unit for inputting to the receiver front-end circuit, and inputting the NMR signal received by the receiving coil as an input analog signal to the RF receiver circuit,
Digital data output from a latch of a receiver circuit is input to the digital receiver front-end circuit as input digital data, and a data ready signal output from a clock driver of the RF receiver circuit is used as a first input clock signal in the digital receiver front end. A digital signal processing clock signal output from a comparator of the RF receiver circuit is input to the digital receiver front-end circuit as a second input clock signal, and dual clock synchronization of the digital receiver front-end circuit is performed. Digital data output from the type FIFO and a digital signal processing clock signal output from the second clock buffer are input to the digital signal processing unit, and a second clock of the digital receiver front end circuit is input to the digital signal processing unit. The digital signal processing clock signal output from the Kkubaffa provides an MRI apparatus characterized by input to the control logic unit. In the MRI apparatus according to the twelfth aspect, digitization of the received signal processing can be favorably advanced.

According to a thirteenth aspect, the present invention provides an RF receiver circuit having the above-described configuration, a digital receiver front-end circuit having the above-described configuration, a digital signal processing section, and generating the start signal in accordance with a pulse sequence. A control logic unit for inputting to the receiver front-end circuit, and inputting the NMR signal received by the receiving coil as an input analog signal to the RF receiver circuit,
Digital data output from a latch of a receiver circuit is input to the digital receiver front-end circuit as input digital data, and a data ready signal output from a clock driver of the RF receiver circuit is used as a first input clock signal in the digital receiver front end. A digital signal processing clock signal output from a comparator of the RF receiver circuit is input to the digital receiver front-end circuit as a second input clock signal, and dual clock synchronization of the digital receiver front-end circuit is performed. Digital data output from a type FIFO and a digital signal processing clock signal output from the second clock buffer are input to the digital signal processing unit, and read control of the digital receiver front-end circuit is performed. It provides an MRI apparatus characterized by inputting a digital signal processing clock signal output from the sync ready signal and the second clock buffer are output from the circuit to the control logic unit. The thirteenth
In the MRI apparatus according to the aspect described above, digitization of received signal processing can be favorably advanced.

According to a fourteenth aspect, the present invention provides a high-speed AD converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, and a digital data output from the high-speed AD converter output from the high-speed AD converter. A high-speed A / D converter comprising: a data storage means for storing the digital data in synchronization with a data ready signal to be read out and reading and outputting the stored digital data in synchronization with a read clock signal supplied from outside. I do. In the high-speed AD converter according to the fourteenth aspect, the digital data is stored in the data storage unit at the timing when the digital data is output from the high-speed AD converter. Then, the digital data is read from the data storage means in synchronization with a read clock signal supplied from the outside. Accordingly, even if there is a timing difference between the timing at which digital data is output from the high-speed AD converter and the clock signal used in the external circuit for processing the digital data, the difference can be absorbed.

According to a fifteenth aspect of the present invention, in the high-speed AD converter having the above-mentioned configuration, the data storage means includes a dual-clock synchronous FIFO and the high-speed AD converter in response to a start signal given from the outside. A write control circuit for storing output digital data in the dual clock synchronous FIFO in synchronization with the data ready signal; and a dual clock synchronous FIFO in response to an empty signal output from the dual clock synchronous FIFO. And a read control circuit for reading digital data in synchronization with the read clock signal. In the high-speed AD converter according to the fifteenth aspect,
By supplying a start signal from the outside, digital data output from the high-speed AD converter can be written to the dual-clock synchronous FIFO. And the digital data is a dual clock synchronous type FIF
Since digital data is read from the dual-clock synchronous FIFO in response to an empty signal output when written to O, the digital data can be properly passed from a high-speed AD converter to an external circuit that processes the digital data. .

According to a sixteenth aspect, the present invention provides the high-speed AD conversion signal processing device having the above-described configuration, wherein the read control circuit notifies the outside that digital data is being read from the dual clock synchronous FIFO. A high-speed A that generates and outputs a sync ready signal of
Provided is a D-converted signal processing device. In the high-speed AD converter according to the sixteenth aspect, the timing at which digital data is output from the dual clock synchronous FIFO can be known by monitoring the sync ready signal.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to this.

First Embodiment FIG. 1 shows an MRI apparatus 1 according to a first embodiment of the present invention.
It is a block diagram showing 00. In the MRI apparatus 100, the magnet assembly 1 has a space portion (bore) for inserting a subject inside, and a static magnetic field that applies a constant static magnetic field to the subject so as to surround the space portion. The coil 1p and a gradient magnetic field of the X, Y, and Z axes (X
A gradient magnetic field coil 1g for generating a slice gradient axis, a read gradient axis, and a phase encoding gradient axis is formed by a combination of the axis, the Y axis, and the Z axis), and for exciting spins of nuclei in the subject. A transmission coil 1t for applying an RF pulse and a reception coil 1r for detecting an NMR signal from the subject are arranged. The static magnetic field coil 1p, the gradient magnetic field coil 1g, the transmission coil 1t, and the reception coil 1
r is a static magnetic field power supply 2, a gradient magnetic field drive circuit 3, and R
F power amplifier 4 and preamplifier 5 are connected.
Note that a permanent magnet may be used instead of the static magnetic field coil 1p and the static magnetic field power supply 2.

The sequence storage circuit 6 operates the gradient magnetic field drive circuit 3 based on the stored pulse sequence in accordance with a command from the computer 7 to generate a gradient magnetic field from the gradient magnetic field coil 1g of the magnet assembly 1 and , The gate modulation circuit 8 is operated to modulate the carrier output signal of the RF oscillation circuit 9 into a pulse signal having a predetermined timing and a predetermined envelope shape, which is added to the RF power amplifier 4 as an RF pulse, and the RF power amplifier 4 After power amplification
It is applied to the transmission coil 1t of the magnet assembly 1 to selectively excite a desired imaging surface.

The preamplifier 5 includes a magnet assembly 1
, And amplifies the NMR signal from the subject received by the receiving coil 1r, and inputs the amplified signal to the high-speed AD conversion signal processing device 10.
The high-speed AD conversion signal processing device 10 converts the NMR signal into digital data, performs digital signal processing, and inputs the digital signal to the computer 7. The high-speed AD conversion signal processing device 10 will be described later in detail. The control logic unit 11 controls the operation of the high-speed AD conversion signal processing device 10 based on an instruction from the computer 7.

The computer 7 receives information input from the operation console 12. The computer 7 reads digital data from the AD conversion signal processing device 10 and performs an image reconstruction operation to generate an MR image. In addition, the computer 7 is responsible for overall control including the control described above. The display device 13 displays the MR image.

FIG. 2 is a block diagram showing a configuration example of the high-speed AD conversion signal processing device 10. The high-speed AD conversion signal processing device 10 includes an RF receiver circuit 20, a digital receiver front-end circuit 30, and a digital signal processing circuit 40. The RF receiver circuit 20 is electrically and magnetically shielded from digital circuits such as the digital receiver front-end circuit 30 and the digital signal processing circuit 40 to prevent noise from the digital circuits.

The RF receiver circuit 20 includes a high-speed AD converter 21 for converting an input NMR signal into digital data D_AD at an operation speed of 20 MHz, 40 MHz, etc., a high-stable crystal oscillator 22, and a frequency of an output signal of the high-stable crystal oscillator 22. An RF multiplying circuit 23 that outputs an RF clock signal obtained by multiplying the RF clock signal; and an RF pulse transformer 2 for a high-speed AD converter that generates a differential RF clock signal ENC / ENC * from the RF clock signal and uses it as a clock for a high-speed AD converter.
4, a clock driver 25 for inverting the data ready signal DATA_RDY output from the high-speed AD converter 21 and outputting the inverted signal to the outside, and a separation for generating a separated clock signal electrically separated from the RF clock signal from the RF clock signal. RF pulse transformer 26, a comparator 27 for generating a digital signal processing clock signal from the separated clock signal, and digital data D_AD output from the high-speed AD converter 21 held in synchronization with a data ready signal DATA_RDY. And a latch 28 for outputting D_RF.

FIG. 5 shows the differential RF clock signals ENC and ENC *.
, Digital data D_AD, and data ready signal DATA_RDY
And the timing of the digital data D_RF. Differential RF
Digital data D_AD is output at the rising edge of the clock signal ENC (falling edge of ENC *). Also, digital data D_AD
Is stable, the data ready signal DATA_RDY is output. Then, at the rise of the data ready signal DATA_RDY, the digital data D_RF is output.

Returning to FIG. 2, the digital receiver front-end circuit 30 includes a first clock buffer 31 for generating a data ready signal CLK_AD from a data ready signal DATA_RDY input from the clock driver 25 of the RF receiver circuit 20, and an RF receiver circuit. A second clock buffer 32 that generates a digital signal processing clock signal CLK_DIG from the digital signal processing clock signal input from the comparator 27 and outputs the digital signal processing clock signal CLK_DIG to the outside, and is input from a latch 28 of the RF receiver circuit 20. Digital data D_
A latch 33 that holds RF in synchronization with the data ready signal CLK_AD and outputs digital data D_DIG, and stores and stores digital data D_DIG in synchronization with the data ready signal CLK_AD when the write request signal WRREQ becomes “H”. However, when digital data D_DIG is stored, empty signal EMPTY
Is set to "L" and the read request signal RDREQ becomes "H", the stored digital data D_DIG is read out in synchronization with the digital signal processing clock signal CLK_DIG to output a digital clock D_FIFO.
An output from the dual-clock synchronous FIFO 34; a write control circuit 35 that sets the write request signal WRREQ to “H” in synchronization with the data ready signal CLK_AD in response to a start signal START input from the control logic unit 11 Read request RDREQ in synchronization with the digital signal processing clock signal CLK_DIG according to the empty signal EMPTY
To “H” and dual clock synchronous FIFO
And a read control circuit 36 for generating and outputting a sync ready signal SYNC_RDY for notifying that the digital data D_FIFO is being output from the outside.

FIG. 3 shows a configuration example of the write control circuit 35. The write control circuit 35 is composed of two D-flip-flops 351 and 352 connected in series, and is the second clock of the data ready signal CLK_AD after the start signal START instructing the start of storage becomes “H”. At the rising edge, the write request signal WRREQ becomes “H”.

FIG. 4 shows a configuration example of the read control circuit 36. The read control circuit 36 includes an inversion circuit 361, an AND gate 362, and two D-flip-flops 363 and 364 connected in series.
WRREQ goes to “H” and empty signal EMPTY goes to “L”
Clock signal for digital signal processing CLK_DIG
The read request RDREQ goes "H" at the rising edge of the first clock, and the sync ready signal SYNC_RDY goes "H" at the rising edge of the second clock.

FIG. 5 shows a data ready signal CLK_AD, a digital signal processing clock signal CLK_DIG, and a start signal S
TART, the write request signal WRREQ, and the digital data (FI
FO), an empty signal EMPTY, and a read request RDREQ
And digital data D_FIFO output from the dual clock synchronous FIFO 34, and a sync ready signal SYNC_RDY
The timing of is shown. Digital data D_DIG is output from the latch 33 at the rise of the data ready signal CLK_AD. When the start signal START becomes “H”, the write request signal WRREQ becomes “H” at the rising of the second clock of the data ready signal CLK_AD. While the write request signal WRREQ is “L”, the dual clock synchronous FIFO 34
Does not store digital data D_DIG. When the write request signal WRREQ becomes “H”, the dual clock synchronous FIFO stores digital data D_DIG.
The dual-clock synchronous FIFO 34 keeps the empty signal EMPTY at "H" while the digital data D_DIG is not stored, but makes the empty signal EMPTY "L" when at least one digital data D_DIG is stored. The write request WRREQ becomes “H” and the empty signal E
At the rising edge of the first clock of the digital signal processing clock signal CLK_DIG after MPTY goes “L”, the read request RDREQ goes “H”. Read request RDREQ is "H"
Then, the dual clock synchronous FIFO 34 outputs digital data D_FIFO in synchronization with the rise of the digital signal processing clock signal CLK_DIG. Further, at the rising edge of the second clock of the digital signal processing clock signal CLK_DIG after the read request RDREQ becomes “H”, the sync ready signal SYNC_RDY becomes “H”.

The digital signal processing section 40 operates with the digital signal processing clock signal CLK_DIG and outputs the digital data D
_FIFO is read and subjected to digital signal processing such as digital demodulation (digital quadrature detection) and digital filtering, and then passed to the computer 7.

The control logic unit 11 operates with the digital signal processing clock signal CLK_DIG, and sets the start signal START to “H” or “L” based on an instruction from the computer 7. When the sync ready signal SYNC_RDY becomes "H", the operation of the digital signal processing unit 40 is started.

The computer 7 outputs a start signal at power-on.
An instruction to set START to "L" is issued, and an instruction to set start signal START to "H" is issued just before the start of data collection.
An instruction to set START to "L" is issued.

According to the high-speed AD conversion signal processing device 10 described above, the digital data D_AD
Is output by the dual-clock synchronous FIFO 34, and the digital data D_AD is absorbed by the high-speed AD converter 21. From the digital signal processing unit 40. Further, since the operation clock frequency can be easily switched, 0.2T to 1.5T or 3T is used.
It can correspond to the MRI apparatus of all magnetic field strengths such as T and 4T. According to the RF receiver circuit 20 and the digital receiver front end circuit 30, the high-speed AD
The conversion signal processing device 10 can be suitably configured.
Further, according to the MRI apparatus 100, it is possible to digitize the received signal processing.

Second Embodiment FIG. 6 is a block diagram showing another configuration example of the high-speed AD conversion signal processing device 10. The high-speed A / D conversion signal processing device 10 includes a high-speed A / D conversion device 50 formed as an LSI (Large Scale Integration), a clock circuit 60, and a digital signal processing circuit 40.

The high-speed AD converter 50 converts the input NMR signal into digital data D_AD at an operating speed of 20 MHz, 40 MHz or the like, and converts the digital data D_A when the write request signal WRREQ becomes “H”.
When D is stored in synchronization with the data ready signal CLK_AD and at least one digital data D_AD is stored, the empty signal EMPTY is set to “L” and when the read request signal RDREQ is set to “H”, the stored digital data D_AD is digitally stored. A dual clock synchronous FIFO 34 that outputs read digital data D_FIFO in synchronization with the signal processing clock signal CLK_DIG, and a write request signal in synchronization with the data ready signal CLK_AD in response to a start signal START input from the control logic unit 11 The read request RDREQ is set to “H” in synchronization with the digital signal processing clock signal CLK_DIG in response to the write control circuit 35 that sets WRREQ to “H” and the empty signal EMPTY output from the dual clock synchronous FIFO 34. Digital data D_FIFO is being output from dual clock synchronous FIFO 34 Sync ready signal SYNC_RDY for informing the door to the outside
And a read control circuit 36 for generating and outputting the same.

The clock circuit 60 has a high stability crystal oscillator 2
2, an RF multiplying circuit 23 that outputs an RF clock signal obtained by multiplying the frequency of the output signal of the high stability crystal oscillator 22;
From the RF clock signal, a differential RF clock signal ENC / E
An RF pulse transformer 24 for high-speed AD converter for generating NC * and using the clock for the high-speed AD converter;
A separating RF pulse transformer 26 for generating a separated clock signal electrically separated from the RF clock signal from the F clock signal, a comparator 27 for generating a digital signal processing clock signal from the separated clock signal, and a comparator 27
And a clock buffer 32 that generates a digital signal processing clock signal CLK_DIG from the digital signal processing clock signal input from the CPU.

The above-described high-speed AD conversion signal processing apparatus 10 can provide substantially the same operation and effect as those of the first embodiment. Further, since the high-speed AD converter 50 is formed as an LSI, the number of parts can be reduced. Note that high-speed AD
Since the LSI of the conversion device 50 outputs digital data in parallel at high speed, a DSP (Digital Signal Processa) is used.
In combination with r) and the like, it can be used for other purposes (for example, a software defined radio that supports communication with high quality and high dynamic range).

[Other Embodiments] Instead of the RF multiplier circuit 23, a PLL (Phase Locked Loo
p) A synthesizer circuit may be used. The start signal START may be set to “H” using a power-on reset signal. Part or all of the circuit is CPLD (Complex Pr
ogrammable Logic Device) and FPGA (Field-Program)
mable Logic Array).

[0042]

According to the high-speed AD conversion signal processing device of the present invention, there is a timing difference between the timing at which digital data is output from the high-speed AD converter and the digital signal processing clock signal used in the digital signal processing section. The digital data can be properly passed from the high-speed A / D converter to the digital signal processing unit by absorbing this. Further, according to the RF receiver circuit and the digital receiver front-end circuit of the present invention, the high-speed AD conversion signal processing device can be suitably configured.
Further, according to the MRI apparatus of the present invention, it is possible to digitize received signal processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an MRI apparatus according to a first embodiment.

FIG. 2 is a block diagram showing a high-speed AD conversion signal processing device according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration example of a write control circuit;

FIG. 4 is a block diagram illustrating a configuration example of a read control circuit.

FIG. 5 is a timing chart of signals according to the first embodiment.

FIG. 6 is a block diagram illustrating a high-speed AD conversion signal processing device according to a second embodiment.

[Explanation of symbols]

 Reference Signs List 10 high-speed AD conversion signal processing device 11 control logic unit 20 RF receiver circuit 30 digital receiver front-end circuit 40 digital signal processing unit 50 high-speed AD conversion device 100 MRI device

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hiroyuki Miyano 4-7, Asahigaoka, Hino-shi, Tokyo 127 GE Yokogawa Medical Systems Co., Ltd. F-term (reference) 4C096 AA20 AB50 AD02 AD12 AD23 DA01 DA02 5J022 AA01 BA05 CD02 CE00 CE08

Claims (16)

[Claims] 1. A high-speed A / D converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, a digital signal processing unit for performing digital signal processing on the digital data, and a digital data output from the high-speed A / D converter. Data storage for storing in synchronization with a data ready signal output from the high-speed AD converter and reading out the stored digital data in synchronization with a digital signal processing clock signal used in the digital signal processing unit and passing the read digital data to the digital signal processing unit And a high-speed AD conversion signal processing device. 2. The high-speed A / D conversion signal processing device according to claim 1, wherein said data storage means is output from said high-speed A / D converter in response to a dual clock synchronous FIFO and a start signal instructing a start of storage. A write control circuit for storing digital data in the dual clock synchronous FIFO in synchronization with the data ready signal; and a digital data from the dual clock synchronous FIFO in response to an empty signal output from the dual clock synchronous FIFO. A high-speed AD conversion signal processing device, comprising: a read control circuit that reads out the data in synchronization with the digital signal processing clock signal. 3. The high-speed AD conversion signal processing device according to claim 2, wherein the read control circuit outputs a sync ready signal for notifying to the outside that digital data is being read from the dual clock synchronous FIFO. A high-speed AD conversion signal processing device characterized by generating and outputting. 4. The high-speed AD conversion signal processing device according to claim 1, wherein a high-stable crystal oscillator and an RF clock signal obtained by multiplying a frequency of an output signal of the high-stable crystal oscillator are output. A high-speed AD conversion signal processing apparatus, comprising: an RF multiplying circuit for generating a differential RF clock signal from the RF clock signal; and an RF pulse transformer for a high-speed AD converter used as a clock for the high-speed AD converter. . 5. The separation RF pulse transformer according to claim 4, wherein the separation RF pulse transformer generates a separation clock signal electrically separated from the RF clock signal from the RF clock signal, and the separation clock. A comparator for generating the digital signal processing clock signal from the signal. 6. The high-speed AD according to claim 1, wherein:
Equipped with a conversion signal processing device, NM received by the receiving coil
An MRI apparatus wherein the R signal is processed as an input analog signal by the high-speed AD conversion signal processing apparatus. 7. A high-speed AD converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, a high-stable crystal oscillator, and an RF clock signal obtained by multiplying the frequency of an output signal of the high-stable crystal oscillator. R
An F multiplying circuit, a high-speed AD converter RF pulse transformer that generates a differential RF clock signal from the RF clock signal and uses the RF clock signal as the high-speed AD converter clock, and a data ready signal output from the high-speed AD converter to the outside A clock driver for outputting, and a separating RF pulse transformer for generating a separated clock signal electrically separated from the RF clock signal from the RF clock signal;
A comparator for generating the digital signal processing clock signal from the separated clock signal; and a latch for holding and outputting digital data output from the high-speed AD converter in synchronization with the data ready signal. RF receiver circuit. 8. A first clock buffer for generating a data ready signal from a first input clock signal, a second clock buffer for generating a digital signal processing clock signal from a second input clock signal and outputting it to the outside, A latch for holding and outputting input digital data in synchronization with the data ready signal; storing the digital data output from the latch in synchronization with the data ready signal; and storing the stored digital data in the digital signal processing clock. A digital receiver front-end circuit, comprising: a data storage means for reading and outputting in synchronization with a signal. 9. The digital receiver front-end circuit according to claim 8, wherein said data storage means transmits said input digital data to said data ready signal in response to a dual clock synchronous FIFO and a start signal instructing a start of storage. Synchronously with the dual clock synchronous type F
A write control circuit for storing the data in an IFO, and a read control circuit for reading digital data from the dual clock synchronous FIFO in synchronization with the clock signal for digital signal processing in response to an empty signal output from the dual clock synchronous FIFO And a digital receiver front-end circuit comprising: 10. The digital receiver front-end circuit according to claim 9, wherein the read control circuit generates a sync ready signal for notifying to the outside that digital data is being read from the dual clock synchronous FIFO. And a digital receiver front-end circuit. 11. A receiver comprising the RF receiver circuit according to claim 7, the digital receiver front-end circuit according to any one of claims 8 to 10, and a digital signal processing unit, wherein the reception signal is received by a reception coil. An NMR signal is input to the RF receiver circuit as an input analog signal, digital data output from a latch of the RF receiver circuit is input to the digital receiver front-end circuit as input digital data, and a clock driver of the RF receiver circuit is input. Output data ready signal to first
Inputting the digital receiver front-end circuit as an input clock signal, and inputting a digital signal processing clock signal output from a comparator of the RF receiver circuit to the digital receiver front-end circuit as a second input clock signal; An MRI apparatus, wherein digital data output from a dual-clock synchronous FIFO of a receiver front-end circuit and a clock signal for digital signal processing output from the second clock buffer are input to the digital signal processing unit. 12. The RF receiver circuit according to claim 7, a digital receiver front-end circuit according to claim 9 or 10, a digital signal processing unit, and generating the start signal according to a pulse sequence. A control logic unit for inputting to the digital receiver front-end circuit, inputting the NMR signal received by the receiving coil to the RF receiver circuit as an input analog signal, and outputting digital data output from a latch of the RF receiver circuit. Inputting the input digital data to the digital receiver front-end circuit, inputting a data ready signal output from a clock driver of the RF receiver circuit to the digital receiver front-end circuit as a first input clock signal; Digital output from the comparator Clock signal for processing the second signal
An input clock signal is input to the digital receiver front-end circuit, and digital data output from a dual-clock synchronous FIFO of the digital receiver front-end circuit and a digital signal processing clock signal output from the second clock buffer are input to the digital receiver front-end circuit. An MRI apparatus comprising: a digital signal processing unit; and a digital signal processing clock signal output from a second clock buffer of the digital receiver front-end circuit, input to the control logic unit. 13. The RF receiver circuit according to claim 7, a digital receiver front-end circuit according to claim 10, a digital signal processing unit, and the digital receiver front circuit that generates the start signal according to a pulse sequence. And a control logic unit for inputting to the end circuit.
An NMR signal received by a receiving coil is input to the RF receiver circuit as an input analog signal, and digital data output from a latch of the RF receiver circuit is input to the digital receiver front-end circuit as input digital data. A data ready signal output from a clock driver of the circuit is input to the digital receiver front end circuit as a first input clock signal, and a digital signal processing clock signal output from a comparator of the RF receiver circuit is input to a second input clock. A digital signal output from the dual-clock synchronous FIFO of the digital receiver front-end circuit and a digital signal output from the second clock buffer. A lock signal is input to the digital signal processing unit, and a sync ready signal output from a read control circuit of the digital receiver front-end circuit and a digital signal processing clock signal output from the second clock buffer are input to the control logic unit. An MRI apparatus characterized by inputting to an MRI. 14. A high-speed AD converter for converting an input analog signal into digital data at an operation speed of 20 MHz or more, and synchronizing digital data output from the high-speed AD converter with a data ready signal output from the high-speed AD converter. A high-speed A / D conversion device comprising: a data storage means for storing and storing the digital data in synchronism with an externally applied read clock signal. 15. The high-speed AD converter according to claim 14, wherein said data storage means includes a dual clock synchronous FIFO and digital data output from said high-speed AD converter in response to an externally applied start signal. A write control circuit for storing the data in the dual clock synchronous FIFO in synchronization with the data ready signal, and the dual clock synchronous FIFO in response to an empty signal output from the dual clock synchronous FIFO.
A high-speed AD conversion signal processing device, comprising: a read control circuit for reading digital data from O in synchronization with the read clock signal. 16. The high-speed AD conversion signal processing device according to claim 15, wherein said read control circuit outputs a sync ready signal for notifying to the outside that digital data is being read from said dual clock synchronous FIFO. A high-speed AD conversion signal processing device characterized by generating and outputting.