JP2013546105A5 - - Google Patents

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Publication number
JP2013546105A5
JP2013546105A5 JP2013544736A JP2013544736A JP2013546105A5 JP 2013546105 A5 JP2013546105 A5 JP 2013546105A5 JP 2013544736 A JP2013544736 A JP 2013544736A JP 2013544736 A JP2013544736 A JP 2013544736A JP 2013546105 A5 JP2013546105 A5 JP 2013546105A5
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JP
Japan
Prior art keywords
simd
system call
work item
call request
wavefront
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JP2013544736A
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English (en)
Japanese (ja)
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JP2013546105A (ja
JP6228459B2 (ja
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Priority claimed from US13/307,505 external-priority patent/US8752064B2/en
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Publication of JP2013546105A publication Critical patent/JP2013546105A/ja
Publication of JP2013546105A5 publication Critical patent/JP2013546105A5/ja
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Publication of JP6228459B2 publication Critical patent/JP6228459B2/ja
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JP2013544736A 2010-12-14 2011-12-14 システムコール要求の通信の最適化 Active JP6228459B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US42295310P 2010-12-14 2010-12-14
US61/422,953 2010-12-14
US13/307,505 US8752064B2 (en) 2010-12-14 2011-11-30 Optimizing communication of system call requests
US13/307,505 2011-11-30
PCT/US2011/064859 WO2012082867A1 (en) 2010-12-14 2011-12-14 Optimizing communication of system call requests

Publications (3)

Publication Number Publication Date
JP2013546105A JP2013546105A (ja) 2013-12-26
JP2013546105A5 true JP2013546105A5 (cg-RX-API-DMAC7.html) 2015-02-12
JP6228459B2 JP6228459B2 (ja) 2017-11-08

Family

ID=46245087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013544736A Active JP6228459B2 (ja) 2010-12-14 2011-12-14 システムコール要求の通信の最適化

Country Status (6)

Country Link
US (1) US8752064B2 (cg-RX-API-DMAC7.html)
EP (1) EP2652575A4 (cg-RX-API-DMAC7.html)
JP (1) JP6228459B2 (cg-RX-API-DMAC7.html)
KR (1) KR101788267B1 (cg-RX-API-DMAC7.html)
CN (1) CN103262002B (cg-RX-API-DMAC7.html)
WO (1) WO2012082867A1 (cg-RX-API-DMAC7.html)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9513975B2 (en) * 2012-05-02 2016-12-06 Nvidia Corporation Technique for computational nested parallelism
US9038075B2 (en) * 2012-11-26 2015-05-19 Red Hat, Inc. Batch execution of system calls in an operating system
US10235732B2 (en) * 2013-12-27 2019-03-19 Intel Corporation Scheduling and dispatch of GPGPU workloads
US11126559B2 (en) 2013-12-30 2021-09-21 Michael Henry Kass Translation look-aside buffer and prefetch indicator
US10216632B2 (en) 2013-12-30 2019-02-26 Michael Henry Kass Memory system cache eviction policies
US10002080B2 (en) * 2013-12-30 2018-06-19 Michael Henry Kass Memory system address modification policies
US10521390B2 (en) * 2016-11-17 2019-12-31 The United States Of America As Represented By The Secretary Of The Air Force Systems and method for mapping FIFOs to processor address space
US11093251B2 (en) 2017-10-31 2021-08-17 Micron Technology, Inc. System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
US11513840B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor
US11119782B2 (en) 2018-05-07 2021-09-14 Micron Technology, Inc. Thread commencement using a work descriptor packet in a self-scheduling processor
US11513838B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread state monitoring in a system having a multi-threaded, self-scheduling processor
US11132233B2 (en) 2018-05-07 2021-09-28 Micron Technology, Inc. Thread priority management in a multi-threaded, self-scheduling processor
US11126587B2 (en) 2018-05-07 2021-09-21 Micron Technology, Inc. Event messaging in a system having a self-scheduling processor and a hybrid threading fabric
US11513837B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric
US11119972B2 (en) 2018-05-07 2021-09-14 Micron Technology, Inc. Multi-threaded, self-scheduling processor
US11074078B2 (en) 2018-05-07 2021-07-27 Micron Technology, Inc. Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion
US11157286B2 (en) 2018-05-07 2021-10-26 Micron Technology, Inc. Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor
US11513839B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Memory request size management in a multi-threaded, self-scheduling processor
US11068305B2 (en) 2018-05-07 2021-07-20 Micron Technology, Inc. System call management in a user-mode, multi-threaded, self-scheduling processor
CN110716750B (zh) * 2018-07-11 2025-05-30 超威半导体公司 用于部分波前合并的方法和系统
US11250107B2 (en) * 2019-07-15 2022-02-15 International Business Machines Corporation Method for interfacing with hardware accelerators
CN112230931B (zh) * 2020-10-22 2021-11-02 上海壁仞智能科技有限公司 适用于图形处理器的二次卸载的编译方法、装置和介质

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842811B2 (en) * 2000-02-24 2005-01-11 Pts Corporation Methods and apparatus for scalable array processor interrupt detection and response
EP1880274A2 (en) 2005-04-22 2008-01-23 Altrix Logic, Inc. Array of data processing elements with variable precision interconnect
CN101446909B (zh) * 2007-11-30 2011-12-28 国际商业机器公司 用于管理任务事件的方法和系统
US8106914B2 (en) * 2007-12-07 2012-01-31 Nvidia Corporation Fused multiply-add functional unit
US8312254B2 (en) * 2008-03-24 2012-11-13 Nvidia Corporation Indirect function call instructions in a synchronous parallel thread processor
JP5461533B2 (ja) 2008-05-30 2014-04-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ローカル及びグローバルのデータ共有
US8904366B2 (en) 2009-05-15 2014-12-02 International Business Machines Corporation Use of vectorization instruction sets
US9195487B2 (en) * 2009-05-19 2015-11-24 Vmware, Inc. Interposition method suitable for hardware-assisted virtual machine
US8661435B2 (en) * 2010-09-21 2014-02-25 Unisys Corporation System and method for affinity dispatching for task management in an emulated multiprocessor environment
US8725989B2 (en) * 2010-12-09 2014-05-13 Intel Corporation Performing function calls using single instruction multiple data (SIMD) registers

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