JP2013541123A - Method and apparatus for determining the state of a phase change memory cell - Google Patents

Abstract

A method and apparatus for determining the state of a phase change memory cell.
A plurality of measurements are made on a cell, and the measured value depends on current-to-voltage characteristics below the cell threshold. The measurement is processed to obtain a metric that depends on the slope of the current-to-voltage characteristic below the threshold. The state of the cell is then determined based on this metric, which is hardly affected by drift unlike the absolute resistance of the cell.
[Selection] Figure 1

Description

  The present invention relates generally to phase change memory, and more particularly to a method and apparatus for determining the state of a phase change memory cell.

  Phase-change memory (PCM) is a novel non-volatile solid-state memory technology that utilizes reversible switching between at least two states of a particular chalcogenide material with different electrical conductivities. PCM is fast, has very good retention and endurance characteristics, and is expected to scale future lithography nodes. For these reasons, it is believed to have the potential to replace or complement flash memory in today's mainstream memory and storage applications.

  In commercially available PCM devices, the basic storage unit (cell) can be set to one of two states, crystalline and amorphous, by heating. In the amorphous state representing binary 0, the electrical resistance of the cell is high. When heated to a temperature above its crystallization point and then cooled, the chalcogenide material is converted to a conductive crystalline state. This low resistance state represents binary one. Thereafter, when the cell is heated to a temperature above the melting point of the chalcogenide, the chalcogenide material returns to its amorphous state by rapid cooling. To write data to the PCM cell, a voltage or current pulse is applied to the cell to heat the chalcogenide material to an appropriate temperature and after cooling to the desired cell state. In order to read the cell, the state of the cell is determined using the resistance of the cell as a metric. Cell resistance is measured by biasing the cell at a specific constant voltage level and measuring the current flowing through the cell, or by measuring the voltage generated across the cell by passing a constant current. This measurement is based on an area below the threshold of the current-to-voltage characteristic of the cell, i.e., the switching threshold voltage (i.e., the chalcogenide is in a conductive “ON” state, the current flows through the cell, and the cell flows via Joule heat. It is possible to heat and this is done in the region below the voltage (which can induce a phase change). In regimes below this threshold, high resistance measurements representing binary 0 and low resistance measurements representing binary 1 can be read from the cell without affecting the cell state.

  As PCM becomes mainstream, an important requirement for PCM is to bring the cost / bit ratio to a level that is competitive with multilevel cell (MLC) flash memory technology. This is an MLC function that can be reduced. Multi-level memory cells can be set to s different resistance levels, where s> 2, thus allowing storage of multiple bits per cell. For example, a NOR flash memory can store four levels per cell, or 2 bits. MLC NAND flash memory chips are currently available that can store 4 bits of data (ie, 16 levels) per single flash cell using 43 nm process technology. In the PCM cell, MLC operation is realized by utilizing the partially amorphous state of the chalcogenide cell. By changing the effective volume of the amorphous phase within the chalcogenide material, different cell levels are set. As a result, the cell resistance changes. Commercial PCM chips currently only store 1 bit per cell, but 4-bit storage per cell with PCM chips has already been experimentally demonstrated.

  One problem in PCM devices is known as short-term resistance drift or structural relaxation, often a physical phenomenon called simply “drift”. This problem is particularly important in MLC devices and presents a significant technical barrier to reliable MLC functionality with PCM. Structural relaxation is believed to be due to local atomic rearrangements in the amorphous phase of the phase change material and affects the conductivity of these materials. Specifically, the resistance of a PCM cell programmed in an amorphous or partially amorphous state in MLC PCM increases with time and is also affected by temperature. For this reason, the cell resistance measured at different times is observed to fluctuate and follow a tendency to increase with increasing time. The events contributing to this resistance shift are stochastic in nature and time of occurrence, and are therefore very difficult to predict and mitigate. Due to resistance drift, different resistance levels corresponding to different cell states (amorphous / crystalline material phase composition within the active volume) overlap each other at random time instances, resulting in random errors in cell state determination Can bring

  Several techniques have been proposed to address this resistance drift problem. One technique involves the use of reference cells, whereby certain portions of the collection of memory cells are reserved for drift mitigation applications. Each of these reference cells is programmed to a specific cell state, and the resistance of these cells is periodically spaced to obtain an estimate of the resistance drift relative to other cells (ie, those used for actual user data storage). Is monitored. The drift estimated from the user cell measurements is then removed in order to obtain a resistance level that is free from drift effects. The effectiveness of such reference cell-based drift cancellation largely depends on the assumption that similar cell states exhibit similar drift characteristics. However, the validity of this assumption is due to significant inter-cell variability (due to process variation (which increases with smaller cell dimensions)) and the inevitable presence of parameter variations within the cell (primarily due to material variability). There is a question of sex and incomplete drift cancellation will occur.

  Another proposal for handling drift is drift acceleration. During (or after) the programming of the memory cell, the cell is annealed at a specific (sufficiently low) temperature for a period of time, thereby accelerating the effects of drift by the Arrhenius relationship. It is assumed that the cell resistance does not drift significantly after annealing. The effect of this approach has not been fully demonstrated by experiments. Furthermore, since the phenomenon of phase change is thermally activated, cell annealing can lead to undesirable disturbances in the cell state.

  An encoding technique for dealing with drift has also been proposed. In this technique, memory cells are programmed and read as blocks of cells (codewords) rather than individually. The redundancy added in these codewords is intended to provide codewords that are not affected by drift and to provide error-free information retrieval in decoding. Drift coding can be a potentially powerful technique, but its effectiveness usually corresponds to the redundancy of the used code. High redundancy hinders the amount of memory available for actual user data storage. Usually, only minimal redundancy is acceptable, and this can reduce the effectiveness of the code to deal with drift.

One embodiment of an aspect of the invention provides a method for determining the state of a phase change memory cell. This method
Performing a plurality of measurements according to a current-to-voltage characteristic below a threshold of the cell;
Processing the measurement to obtain a metric dependent on a slope of the current-to-voltage characteristic;
Determining a state of a cell based on the metric;
including.

  In embodiments of the present invention, a metric is used that depends on the slope of the current-to-voltage (I / V) characteristic below the threshold of the cell, ie, the slope of the I / V characteristic curve below the switching threshold voltage. The slope of the I / V characteristic below the threshold follows the resistance differentiation, that is, the derivative of the resistance, but does not depend on the absolute resistance value at all. As described above, the cell resistance changes greatly with time, but the slope of the I / V characteristic in the regime below the threshold value hardly changes over time. This is because the I / V gradient below the threshold is a function of the effective volume of the amorphous phase in the cell. Thus, the effective amorphous volume is a good indicator of cell state, and it is known that drift does not affect the geometry of the amorphous phase (drift is due to defect pair annihilation in the amorphous phase and It is estimated that it does not affect the volume).

  The method embodying the present invention utilizes a sub-threshold I / V slope to obtain a cell state metric that is substantially drift-invariant. Specifically, the metrics used in embodiments of the present invention are almost unaffected by drift. That is, apart from inevitable noise fluctuations, it is almost unchanged over time. The sub-threshold I / V gradient is a function of the effective amorphous volume in the cell and is therefore an indicator of cell state, so of course the above metric is also a characteristic of the cell state and thus different states in the MLC PCM. It can be used to distinguish between. The validity of this discussion, and the efficiency of this metric as an indicator of cell state, has been demonstrated in experimental results for an array of actual PCM cells, which will be further explained below. Thus, embodiments of the present invention provide a method for determining the state of a PCM cell in such a way that the retrieved information is resistant to drift through the use of the aforementioned metrics. Methods according to embodiments of the present invention may not make any assumptions about the nature of the drift itself and may not result in an inherent loss of user storage capacity. Thus, embodiments of the present invention can provide improved cell state determination for PCM arrays, which generally promotes improved MLC functionality and efficient operation of PCM devices.

  The aforementioned metrics can be directly or indirectly dependent on the slope of the I / V characteristic below the threshold in various ways depending on the slope. The point is that this metric is in some way associated with a sub-threshold I / V slope and is therefore not directly dependent on the absolute resistance of the cell, as Influenced by drift. In other words, according to embodiments of the present invention, the PCM cell state can be determined based on a metric that is not or substantially independent of the absolute resistance of the cell. In accordance with embodiments of the present invention, at least two measurements are made on the cell to derive this metric, and these measurements are (directly or indirectly) below a threshold I / V slope. It depends. As will be explained further below, more than 2 measurements can be made to enable averaging and improve accuracy. The obtained measurements can then be processed in various ways to obtain the final metric used to evaluate the cell state. For example, some embodiments include making multiple measurements of cell current at different cell bias voltages such that the metric depends on a difference in function of the cell current measured at different bias voltages. can do. Similarly, the voltage across the cell for different applied cell currents can be measured so that the metric depends on the difference in the function of the measured cell voltage. Alternatively, for example, multiple measurements of cell resistance are made at different points on the I / V curve below the threshold so that the metric depends on the difference in the cell resistance function measured at the different points. You can also In these examples, the specific function of the measurement value of interest may be the measurement value itself, or it may be a somewhat complex function of the value, such as logarithm.

  Also, the specific method for determining the cell state from the metric may vary depending on different embodiments. The details of this step can be found in the cell type (number of levels), the precise shape of the metric itself, and any techniques that may be used in addition to the basic metric derivation method, for example to further improve reading accuracy. It will depend on some additional correction technique and so on. In preferred embodiments, the cell state can be determined by simply comparing the derived metric (with or without further processing) to one or more reference values indicative of different cell states. . Embodiments of the present invention can also be applied to two-level PCM cells, but are particularly advantageous for multi-level cell applications because of the greater drift problem with MLC devices. When applied to determine the state of a multi-level cell (ie, an s-level cell where s> 2), the preferred method includes a derived metric with multiple reference values indicating the s-level of the cell. Determining the state of the cell by comparing to. Such a reference value can define the level of the cell in various ways, for example, associated with a predetermined threshold that defines a boundary for a measurement range that maps different readback levels.

An embodiment of the second aspect of the invention provides an apparatus for determining the state of a phase change memory cell. This device
A measurement circuit that performs multiple measurements according to current-to-voltage characteristics below the threshold of the cell;
A controller for processing the measured values to obtain a metric dependent on a slope of the current-to-voltage characteristic, the controller determining a state of the cell based on the metric; A controller,
including.

  According to a further embodiment of the present invention, the PCM cell state is determined based on a metric that is not or substantially independent of the absolute resistance value of the cell.

An embodiment of the third aspect of the present invention is:
A memory including a plurality of phase change memory cells;
A read / write device for reading and writing data from the plurality of phase change memory cells;
A phase change memory device including
The read / write device includes a device for determining the state of the memory cell according to the second aspect of the invention.

  In general, although the present specification describes various functions in relation to a method embodying the present invention, the corresponding function can be provided in an apparatus or device embodying the present invention, and vice versa. .

  By way of example, preferred embodiments of the present invention are described below with reference to the accompanying drawings.

1 is a schematic block diagram of a phase change memory device embodying the present invention. The average programming curve for an 8-level PCM cell is shown. The time dependence of the PCM cell at different applied voltages is shown. Fig. 2 shows a simple calculation circuit of a difference metric for generating a cell state metric in the device of Fig. 1; The result of FIG. 3 after an average value removal process is shown. FIG. 6a shows the time dependence of the difference metric used in the device of FIG. 1 before removal of the mean value, and FIG. 6b shows the time dependence of the difference metric used in the device of FIG. 1 after removal of the mean value. Showing gender. It is the figure which compared the time dependence of cell resistance with the time dependence of another metric. FIG. 8a shows the operation of the digital implementation of the measurement circuit of the device of FIG. 1, and FIG. 8b shows the operation of the analog implementation of the measurement circuit of the device of FIG. FIG. 2 compares the effect of drift on cell state measurements for different levels using the raw resistance metric and the difference metric of the device of FIG. It shows how the average difference metric varies along the stored cell level. It is the schematic of the PCM cell showing the effective amorphous thickness of the cell.

  FIG. 1 is a simplified schematic diagram of a phase change memory device embodying the present invention. Device 1 includes a phase change memory 2 for storing data in one or more integrated arrays of multilevel PCM cells. Although shown as a single block in the figure, in general, the memory 2 includes, for example, a PCM that spans multiple storage banks, each containing multiple packages of storage chips, eg, from a single chip or die. Any desired configuration of storage units can be included. Reading and writing of data with respect to the memory 2 is performed by the reading / writing device 3. The device 3 includes a data write and read measurement circuit 4 for writing data to the PCM cell, measuring the cell to determine the cell state and thereby enabling readback of the stored data. Circuit 4 can address the address of individual PCM cells by applying appropriate voltages to the word and bit line array of memory assembly 2 for writing and reading. This process is performed in a generally known manner, except as described in detail below. The read / write controller 5 generally controls the operation of the device 3 and derives a cell state metric from the read measurement, as will be described in more detail below, and this metric is used for cell state determination, ie level detection. Includes features for use. In general, the function of the controller 5 can be implemented in hardware, software, or a combination thereof. In general, a logic circuit that is wired and connected is desirable from the viewpoint of operation speed. Appropriate implementations will be apparent to those skilled in the art from the description herein. As indicated by block 6 in the figure, the user data input to the device 1 is usually subjected to some kind of encoding, such as encoding for error correction, before being provided to the read / write device 3 as write data. The shape is written. Similarly, the readback data output by the device 3 is generally processed by the read processing module 7 to recover the original input user data, for example, code word detection and error correction operations. Is called. Such processing by modules 6 and 7 has nothing to do with the described cell state metric system and need not be described in detail herein.

  Each of the multi-level cells in memory 2 can be set to one of the predetermined resistance levels of s, where s> 2, corresponding to the different amorphous / crystalline states of the cell. The resistance values that partition these different levels are usually spaced unequal, typically located in the log domain. In the particular example of s = 8, each cell stores 8 levels and can provide 3 bits of storage per cell. Circuit 4 applies a voltage pulse to set the cell to a state corresponding to the appropriate resistance level in order to write data to a given cell. FIG. 2 shows how the cell resistance varies with the voltage applied to the PCM cell. This figure shows the average programming curve for 60 8-level PCM cells as a logarithm of (average) cell resistance R obtained by increasing the amplitude Vg of the applied voltage pulse. Eight predetermined resistance levels R0 to R7 are indicated by horizontal lines in the figure. The left side of this programming curve (left of the vertical dotted line at Vg = 1.5 volts) demonstrates how the programmed resistance initially decreases with increasing voltage from 0 volts. . This is due to the increased crystallization in the chalcogenide material of the cell. Vg = 1.5 volts corresponds to the maximum crystallization state. Thereafter, melting increases with increasing voltage, resulting in a larger effective volume of amorphous phase in the cell. This results in an increase in the programmed resistance along the right programming curve shown to the right of the vertical dotted line in the figure. According to conventional practice, data is written to the cell of FIG. 1 by programming the cell on the programming slope to the right of the curve of FIG.

Reading the memory cell includes determining the state of the cell, i.e., detecting which of the predetermined levels R0-R7 the cell is set to. In conventional devices, this is done by making a direct measurement of cell resistance. Specifically, the cell current is measured for a given applied voltage, the cell resistance is calculated and used as a cell state metric, which is compared to a predetermined level to determine the cell state. This measurement is performed in a region below the threshold value of the current-to-voltage (I / V) characteristic of the cell so that the measurement does not affect the cell state. This I / V characteristic is strongly non-linear in the region below the threshold, and therefore different resistances are measured at different bias voltages. This is evident from the plot of log R versus time in FIG. 3, which shows that the measured resistance of the PCM cell decreases with increasing applied voltage. This figure also clearly shows the effect of drift on the resistance measurement. Specifically, the resistance of the amorphous phase is approximately: R (t) = R ₀ (t / t ₀ ) ^v , and thus log R (t) = log R ₀ + vlog (t / t ₀ ) This increases with time. V in the equation is the drift index, which is believed to be proportional to the volume of the amorphous phase in the active region of the PCM cell. This drift index has been shown to increase with increasing temperature. Drift is a stochastic phenomenon that can be treated as non-stationary noise and is therefore very difficult to predict.

The device 1 of FIG. 1 uses a cell state determination method that uses a metric that depends on the slope of the I / V characteristic below a threshold. This provides a metric that is independent of the absolute resistance of the cell. In order to read a cell, the reading measurement circuit 4 performs a plurality of measurements according to an I / V characteristic that is equal to or less than the threshold value of the cell. In this exemplary embodiment, as the difference between the logarithmic resistor R ₂ in the voltage V ₂ different from the logarithm of the cell resistance R ₁ at a particular bias voltage V _1, simple for the following I / V slope threshold A metric is obtained. Since the I / V slope below the threshold is almost constant over time, the difference metric logR ₁ -logR ₂ will have the same properties. In fact, logR ₁ and logR ₂ will fluctuate significantly and on average will increase with time, but these variations are such that subtraction between them removes their common components due to drift. Closely correlated in manner. The remaining components are mostly due to uncorrelated and drift-free noise and other fluctuations. Note that this approach makes no specific assumptions about the nature of drift as a function of time. Any arbitrary drift characteristic (which appears to be a function of time) can be effectively eliminated.

In the read operation of device 1, the measurement circuit 4 determines that the current I ₁ flowing through the cell for application of the first (sub-threshold) voltage V ₁ and the current for application of the second (sub-threshold) voltage V _2. to detect the I _2. The resulting resistance measurements R ₁ = V ₁ / I ₁ and R ₂ = V ₂ / I ₂ are output to the controller 5. The controller 5 then calculates the difference metric logR ₁ -logR ₂ . This can be implemented in the digital or analog domain in the controller 5 using a simple differential amplifier circuit as represented in FIG. Since the resulting metric depends on the resistance difference, the metric depends on the slope of the I / V characteristic, but not on any absolute resistance (and hence absolute current or voltage) value. The I / V slope below the threshold is a function of the effective amorphous volume in the cell, as described above, and is therefore an indicator of cell status. Therefore, of course, this difference metric is also a cell state characteristic. Thus, this difference metric can be used to distinguish between different storage levels with little drift effect for the reasons described above. This is demonstrated by the following description of experimental results.

First, referring again to FIG. 3, it can be observed that the measured values of log (R (t)) at different voltages appear to differ only by a constant amount. Therefore, the structural relaxation (drift) of the material should not be voltage dependent, at least at low voltages (without annealing). The following model is used to explain these measurements.
r (t, V _i ) = R _i + w (t)
W (t) in the equation is a zero average function of time, R _i depends only on V _i , and r () is used to represent log (R ()). R _i is given by logarithmizing the above-described cell resistances R _1, R ₂ and the like. Therefore,
The average E taken against time is
E [r (t, V _i )] = R _i
From now on, for all (i)
r (t, V _i ) −E [r (t, V _i )] = w (t).
This is supported by FIG. 5, which shows the result of FIG. 3 after removal of the average value.
Here, given the difference DR (t, V _i , _k ) between r (t) pairs measured at different voltages V _i , V _k ,
DR (t, V _i , _k ) = r (t, V _i ) −r (t, V _k ) = R _i −R _k
This is independent of (t), i.e. constant over time. Therefore, all DR (t, V _i , _k ) waveforms should be constant over time (gradient = 0). Note that this difference metric does not assume any information about drift characteristics (ie, w (t) can be arbitrary). These predictions are clearly supported by FIGS. 6a and 6b. FIG. 6a is a plot of the difference metric versus log time for different voltage pairs V _i , V _k , and FIG. 6b shows the mean value removal (DR (t, V _i , _k ) −E [DR ( t, V _i , _k )]) shows the same result.

  FIG. 7 shows a direct comparison between the difference metric D and the conventional raw resistance measurement (absolute resistance on the log scale) as a function of log time. These solid lines show a linear fit to the results of each trace. This most clearly demonstrates that the difference metric is less time dependent than the raw metric. Thus, the difference metric is a nearly drift-invariant indicator, and without drift characteristics information (eg, whether logR (t) is proportional to log (t) or due to some other drift model Can provide a functioning indicator).

In the above, a simple model is used to explain these measurements, but R (t) measured at different voltages, assuming R-versus-time power law behavior (general drift model). You can also think of a more sophisticated model. According to the standard drift model
log [R (t)] = α (R ₀ ) + vlogt: where R ₀ = R (0), v is a drift / power exponent, and t ₀ = 1 without loss of generality ing.
With a sophisticated model,
log [R (t, V _i )] = α (R ₀ , V _i ) + (v + w _i ) logt
Where mean E _i {w _i } = 0, v depends on R level, w _i << v, and the difference metric is
_{log [R (t, V i} )] - log [R (t, V k)] = [α (R 0, V i) -α (R 0, V k)] + (w i -w k) logt Take the form of
The first term in the square brackets has a measured value of R (0), which has a value that increases with | V _i −V _k |. The second term is a weak function of time (w _i << v). At this time, the quality of the metric (time invariance, variation) can be improved by taking an average.
E {log [R (t, V _i )] − log [R (t, V _k )]} = E [α (R ₀ , V _i ) −α (R ₀ , V _k )]
This value is not time dependent. This average value can be calculated from many different voltage pairs V _i , V _k . Such an averaging process can be implemented in a simple manner in the device of FIG. During the cell read operation, the measurement circuit 4 detects the cell current at several different applied bit-line (BL) voltages. This is shown in FIG. 8a for a digital circuit implementation and in FIG. 8b for an analog circuit implementation. The resistance measurements (V / I) obtained at each voltage are provided to the controller 5, which calculates the difference between these pairs of resistance values and averages the results to the final average difference metric. Get.

  FIG. 9 compares the slope of the average difference metric versus time waveform for different cell levels with the equivalent waveform slope for the raw (absolute) resistance metric. These slopes are drift index estimators, and the results clearly show the superior performance of the mean difference metric.

  Since we have demonstrated drift tolerance as an indicator of the cell state of this difference metric, we will address the problem of level discrimination. To be effective, the metric is naturally level dependent and should ideally allow level detection with sufficient margin. FIG. 10 shows how the average difference metric varies with the stored resistance level, and the average is taken over multiple pairs of voltages as described above. This figure shows that this difference metric has a discriminating power between stored resistance levels sufficient to use as an effective indicator of cell state. Level detection is performed in the controller 5 of the device 1 by simply comparing the average difference metric obtained for the cell with a plurality of predetermined reference values. These reference values can be, for example, pre-calculated metric values that define different cell levels, or thresholds that define the boundaries between each range of metric values that are considered to map these different cell levels. , Can correspond. Thus, the stored cell level is derived by a simple comparison between the calculated metric and the reference value in the controller 5. The obtained readback data is then output by the controller 5 and further read processing is performed to restore the user data as described above.

  By utilizing the cell state metrics described above, it is clear that the above embodiments can implement a new technique for PCM cell state determination, and the information retrieved thereby is substantially resistant to drift. Let's go. This technique may not make any assumptions about the nature of the drift itself, and may not cause any inherent loss of user storage capacity. Device 1 thus constitutes a new MLC PCM device that utilizes a novel cell state metric technique that provides ease of implementation in addition to improved performance.

Of course, it will be apparent that many changes and modifications may be made to the exemplary embodiments described above. For example, various other metrics can be envisioned based on I / V characteristics below the threshold of the PCM cell. Another simple metric can be obtained as the difference between logarithms of cell currents at different bias voltages V _i , V _k , or similarly as the logarithm difference of voltages measured at different constant current levels It is. Although the present specification uses the logarithm of the detected quantities, other functions of these quantities, or the detected values themselves, could be used to calculate the difference metric. In addition, a simple difference metric provides a rough numerical approximation to the I / V slope (which still has similar properties (time invariance, R level dependence) for the I / V slope, but is desired. Better numerical approximation can be used and improved accuracy can be provided. Numerical approximation to the derivative of a function is a well-studied subject, and various developments in this aspect will be obvious to those skilled in the art. Other possible metrics for sub-threshold I / V slopes are readily apparent by considering the difference metric proposed above in connection with the analytic equation for conduction in sub-threshold regimes. A specific example will be described below with reference to FIG.

FIG. 11 is a schematic diagram of a PCM cell, where the shaded hemisphere represents the effective volume of the amorphous phase within the active volume of the cell at thickness t _gst . This amorphous volume has an effective thickness u _a as shown in the figure. Conduction in amorphous chalcogenides is believed to be due to thermally activated carrier hopping between localized defect states (traps). Two main models for trap-limited conduction in the amorphous phase are pool conduction for high defect densities (Ielmini-Zhang) and pool-Frenkel conduction for low defect densities. These models represent the dependence of the cell current I on the applied voltage V in relation to the temperature T, the effective amorphous thickness u _a , and various other parameters. For the pool conduction model, the difference metric can be expressed as:

In the equation, dz is an average distance between traps, k _B is a Boltzmann constant, and q is a charge of one electron. Similarly, u _a can be estimated as:

The effective amorphous thickness u _a thus estimated could be used as a cell state metric in another embodiment of the invention.

  Similar analysis for the Pool Frenkel model shows that the difference metric is

In the equation, ε is an effective dielectric constant. Similarly, √u _a can be estimated as the following equation.

The parameter √u _a thus estimated could also be used as a cell state metric in another embodiment.

  It should be noted that other techniques could be used to improve performance, as needed, in conjunction with the cell state metric system described above, in embodiments of the present invention. To cope with drift, improved performance can be obtained, among other things, by successfully combining this cell state metric system with other techniques such as encoding. As another example, reference values used for level detection can be updated on a dynamic basis, for example, periodically based on reference cell or model-based correction techniques. Also, uncorrelated noise in the measured values can be suppressed by averaging the results along the way described above.

  Many additional changes and modifications may be made to the described exemplary embodiments without departing from the scope of the present invention.

Claims (15)

A method for determining a state of a phase change memory cell, the method comprising:
Making a plurality of measurements according to current-to-voltage characteristics below the threshold of the cell;
Processing the measurement to obtain a metric dependent on a slope of the current-to-voltage characteristic;
Determining the state of the cell based on the metric;
Including methods.   A method for determining the state of an s level phase change memory cell with s> 2, the method comprising: comparing the metric with a plurality of reference values indicative of the s level of the cell; The method of claim 1, comprising determining the state of the cell.   The method of claim 1, comprising performing multiple measurements of cell current at different bias voltages, wherein the metric depends on a difference in function of the measured cell current at the different bias voltages. the method of.   The method includes the step of making multiple measurements of the voltage across the cell for different applied cell currents, the metric depending on a difference in function of the measured cell voltage at the different applied currents. Or the method of claim 2.   Making a plurality of measurements of cell resistance at different points on the current-to-voltage characteristic, wherein the metric depends on a difference in a function of the measured cell resistance at the different points. 3. A method according to claim 1 or claim 2.   The method according to claim 3, wherein the function of the measured value includes a logarithm of the value. The method according to claim 1, wherein the metric depends on the effective amorphous thickness (u _a ) in the cell. The method of claim 7, wherein the metric comprises an estimate of the effective amorphous thickness (u _a ) in the cell.   9. The method according to any of claims 1 to 8, comprising the step of taking more than two measurements, wherein the step of processing comprises an averaging process. An apparatus for determining a state of a phase change memory cell, the apparatus comprising:
A measurement circuit (4) for performing a plurality of measurements according to current-to-voltage characteristics below the threshold of the cell;
A controller (5) for processing the measured value to obtain a metric dependent on a slope of the current-to-voltage characteristic, wherein the controller (5) is configured to determine the state of the cell based on the metric. Said controller (5) adapted to determine
Including the device.   An apparatus for determining the state of an s level phase change memory cell with s> 2, wherein the controller (5) includes the metric as a plurality of reference values indicative of the s level of the cell. The apparatus according to claim 10, wherein the apparatus is adapted to determine the state of the cell.   The measurement circuit (4) is adapted to perform a plurality of measurements of the cell current at different bias voltages, and the metric depends on a difference in a function of the measured cell current at the different bias voltages. 12. Apparatus according to claim 10 or claim 11.   The measurement circuit (4) is configured to perform a plurality of measurements of voltages across the cell with respect to different applied cell currents, and the metric includes the measured cell voltage with the different applied currents. 12. An apparatus according to claim 10 or claim 11 that depends on a difference in function.   The measurement circuit (4) is configured to perform a plurality of cell resistance measurements at different points on the current-vs-voltage characteristics, and the metric is the cell resistance measured at the different points. 12. An apparatus according to claim 10 or claim 11 which depends on a difference in function of A memory (2) including a plurality of phase change memory cells;
A read / write device (3) for reading and writing data to said phase change memory cell, said read / write device (3) comprising said memory memory device according to claim 10-14. The read / write device (3) comprising a device for determining the state of a cell;
A phase change memory device (1) comprising:

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