JP2013254484A5 - - Google Patents
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- JP2013254484A5 JP2013254484A5 JP2013087861A JP2013087861A JP2013254484A5 JP 2013254484 A5 JP2013254484 A5 JP 2013254484A5 JP 2013087861 A JP2013087861 A JP 2013087861A JP 2013087861 A JP2013087861 A JP 2013087861A JP 2013254484 A5 JP2013254484 A5 JP 2013254484A5
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- conditional branch
- prediction
- branch instruction
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 10
- 230000004044 response Effects 0.000 claims 6
- OCKGFTQIICXDQW-ZEQRLZLVSA-N 5-[(1r)-1-hydroxy-2-[4-[(2r)-2-hydroxy-2-(4-methyl-1-oxo-3h-2-benzofuran-5-yl)ethyl]piperazin-1-yl]ethyl]-4-methyl-3h-2-benzofuran-1-one Chemical compound C1=C2C(=O)OCC2=C(C)C([C@@H](O)CN2CCN(CC2)C[C@H](O)C2=CC=C3C(=O)OCC3=C2C)=C1 OCKGFTQIICXDQW-ZEQRLZLVSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/437,482 US9116686B2 (en) | 2012-04-02 | 2012-04-02 | Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction |
| US13/437,482 | 2012-04-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013254484A JP2013254484A (ja) | 2013-12-19 |
| JP2013254484A5 true JP2013254484A5 (enExample) | 2015-01-22 |
Family
ID=48044642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013087861A Pending JP2013254484A (ja) | 2012-04-02 | 2013-04-02 | ベクトル分割ループの性能の向上 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9116686B2 (enExample) |
| EP (1) | EP2648090A3 (enExample) |
| JP (1) | JP2013254484A (enExample) |
| KR (1) | KR101511837B1 (enExample) |
| CN (1) | CN103383640B (enExample) |
| BR (1) | BR102013007865A2 (enExample) |
| TW (1) | TWI512617B (enExample) |
| WO (1) | WO2013151861A1 (enExample) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9323531B2 (en) * | 2013-03-15 | 2016-04-26 | Intel Corporation | Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register |
| US10241793B2 (en) | 2013-03-15 | 2019-03-26 | Analog Devices Global | Paralleizing loops in the presence of possible memory aliases |
| GB2519108A (en) | 2013-10-09 | 2015-04-15 | Advanced Risc Mach Ltd | A data processing apparatus and method for controlling performance of speculative vector operations |
| GB2519107B (en) | 2013-10-09 | 2020-05-13 | Advanced Risc Mach Ltd | A data processing apparatus and method for performing speculative vector access operations |
| WO2015145190A1 (en) | 2014-03-27 | 2015-10-01 | Intel Corporation | Processors, methods, systems, and instructions to store consecutive source elements to unmasked result elements with propagation to masked result elements |
| US10223119B2 (en) | 2014-03-28 | 2019-03-05 | Intel Corporation | Processors, methods, systems, and instructions to store source elements to corresponding unmasked result elements with propagation to masked result elements |
| US10289417B2 (en) | 2014-10-21 | 2019-05-14 | Arm Limited | Branch prediction suppression for blocks of instructions predicted to not include a branch instruction |
| US20160179550A1 (en) * | 2014-12-23 | 2016-06-23 | Intel Corporation | Fast vector dynamic memory conflict detection |
| GB2540941B (en) * | 2015-07-31 | 2017-11-15 | Advanced Risc Mach Ltd | Data processing |
| GB2545248B (en) | 2015-12-10 | 2018-04-04 | Advanced Risc Mach Ltd | Data processing |
| GB2548602B (en) * | 2016-03-23 | 2019-10-23 | Advanced Risc Mach Ltd | Program loop control |
| GB2549737B (en) * | 2016-04-26 | 2019-05-08 | Advanced Risc Mach Ltd | An apparatus and method for managing address collisions when performing vector operations |
| GB2571527B (en) * | 2018-02-28 | 2020-09-16 | Advanced Risc Mach Ltd | Data processing |
| US11860996B1 (en) | 2018-04-06 | 2024-01-02 | Apple Inc. | Security concepts for web frameworks |
| US10915322B2 (en) * | 2018-09-18 | 2021-02-09 | Advanced Micro Devices, Inc. | Using loop exit prediction to accelerate or suppress loop mode of a processor |
| WO2020148906A1 (ja) * | 2019-01-18 | 2020-07-23 | 日本電気株式会社 | 最適化装置、最適化方法、及びコンピュータ読み取り可能な記録媒体 |
| US11327862B2 (en) | 2019-05-20 | 2022-05-10 | Micron Technology, Inc. | Multi-lane solutions for addressing vector elements using vector index registers |
| US11340904B2 (en) | 2019-05-20 | 2022-05-24 | Micron Technology, Inc. | Vector index registers |
| US11507374B2 (en) | 2019-05-20 | 2022-11-22 | Micron Technology, Inc. | True/false vector index registers and methods of populating thereof |
| US11403256B2 (en) * | 2019-05-20 | 2022-08-02 | Micron Technology, Inc. | Conditional operations in a vector processor having true and false vector index registers |
| US11989554B2 (en) * | 2020-12-23 | 2024-05-21 | Intel Corporation | Processing pipeline with zero loop overhead |
| CN115113934B (zh) * | 2022-08-31 | 2022-11-11 | 腾讯科技（深圳）有限公司 | 指令处理方法、装置、程序产品、计算机设备和介质 |
Family Cites Families (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5228131A (en) * | 1988-02-24 | 1993-07-13 | Mitsubishi Denki Kabushiki Kaisha | Data processor with selectively enabled and disabled branch prediction operation |
| US5903750A (en) | 1996-11-20 | 1999-05-11 | Institute For The Development Of Emerging Architectures, L.L.P. | Dynamic branch prediction for branch instructions with multiple targets |
| JPH1185515A (ja) | 1997-09-10 | 1999-03-30 | Ricoh Co Ltd | マイクロプロセッサ |
| US6988183B1 (en) | 1998-06-26 | 2006-01-17 | Derek Chi-Lan Wong | Methods for increasing instruction-level parallelism in microprocessors and digital system |
| US6353883B1 (en) | 1998-08-04 | 2002-03-05 | Intel Corporation | Method and apparatus for performing predicate prediction |
| EP1122639A3 (en) * | 1998-08-24 | 2002-02-13 | Advanced Micro Devices, Inc. | Mechanism for load block on store address generation and universal dependency vector/queue entry |
| JP2000322257A (ja) | 1999-05-10 | 2000-11-24 | Nec Corp | 条件分岐命令の投機的実行制御方法 |
| US7159099B2 (en) | 2002-06-28 | 2007-01-02 | Motorola, Inc. | Streaming vector processor with reconfigurable interconnection switch |
| US7571302B1 (en) | 2004-02-04 | 2009-08-04 | Lei Chen | Dynamic data dependence tracking and its application to branch prediction |
| US20060168432A1 (en) | 2005-01-24 | 2006-07-27 | Paul Caprioli | Branch prediction accuracy in a processor that supports speculative execution |
| US7587580B2 (en) | 2005-02-03 | 2009-09-08 | Qualcomm Corporated | Power efficient instruction prefetch mechanism |
| US20070288732A1 (en) * | 2006-06-08 | 2007-12-13 | Luick David A | Hybrid Branch Prediction Scheme |
| WO2008029450A1 (fr) | 2006-09-05 | 2008-03-13 | Fujitsu Limited | Dispositif de traitement d'informations comprenant un mécanisme de correction d'erreur de prédiction d'embranchement |
| US7627742B2 (en) | 2007-04-10 | 2009-12-01 | International Business Machines Corporation | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system |
| US8006070B2 (en) | 2007-12-05 | 2011-08-23 | International Business Machines Corporation | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system |
| US8417921B2 (en) | 2008-08-15 | 2013-04-09 | Apple Inc. | Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector |
| US8271832B2 (en) | 2008-08-15 | 2012-09-18 | Apple Inc. | Non-faulting and first-faulting instructions for processing vectors |
| US8959316B2 (en) | 2008-08-15 | 2015-02-17 | Apple Inc. | Actual instruction and actual-fault instructions for processing vectors |
| US20100325399A1 (en) | 2008-08-15 | 2010-12-23 | Apple Inc. | Vector test instruction for processing vectors |
| US8793472B2 (en) | 2008-08-15 | 2014-07-29 | Apple Inc. | Vector index instruction for generating a result vector with incremental values based on a start value and an increment value |
| US20110035568A1 (en) | 2008-08-15 | 2011-02-10 | Apple Inc. | Select first and select last instructions for processing vectors |
| US8447956B2 (en) | 2008-08-15 | 2013-05-21 | Apple Inc. | Running subtract and running divide instructions for processing vectors |
| US8131979B2 (en) | 2008-08-15 | 2012-03-06 | Apple Inc. | Check-hazard instructions for processing vectors |
| US8984262B2 (en) | 2008-08-15 | 2015-03-17 | Apple Inc. | Generate predicates instruction for processing vectors |
| US20110283092A1 (en) | 2008-08-15 | 2011-11-17 | Apple Inc. | Getfirst and assignlast instructions for processing vectors |
| US8650383B2 (en) | 2008-08-15 | 2014-02-11 | Apple Inc. | Vector processing with predicate vector for setting element values based on key element position by executing remaining instruction |
| US20100115233A1 (en) | 2008-10-31 | 2010-05-06 | Convey Computer | Dynamically-selectable vector register partitioning |
| JP5387819B2 (ja) | 2008-12-26 | 2014-01-15 | 日本電気株式会社 | 分岐予測の信頼度見積もり回路及びその方法 |
| US8521996B2 (en) | 2009-02-12 | 2013-08-27 | Via Technologies, Inc. | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution |
| US9176737B2 (en) | 2011-02-07 | 2015-11-03 | Arm Limited | Controlling the execution of adjacent instructions that are dependent upon a same data condition |
| US9268569B2 (en) | 2012-02-24 | 2016-02-23 | Apple Inc. | Branch misprediction behavior suppression on zero predicate branch mispredict |
-
2012
- 2012-04-02 US US13/437,482 patent/US9116686B2/en active Active
-
2013
- 2013-03-28 WO PCT/US2013/034360 patent/WO2013151861A1/en not_active Ceased
- 2013-03-28 EP EP13161570.0A patent/EP2648090A3/en not_active Withdrawn
- 2013-04-01 TW TW102111747A patent/TWI512617B/zh active
- 2013-04-01 BR BRBR102013007865-4A patent/BR102013007865A2/pt not_active Application Discontinuation
- 2013-04-02 JP JP2013087861A patent/JP2013254484A/ja active Pending
- 2013-04-02 KR KR20130035807A patent/KR101511837B1/ko active Active
- 2013-04-02 CN CN201310112340.9A patent/CN103383640B/zh active Active
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