JP2013251590A - Error correction decoding circuit and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in an error correction decoding circuit.SOLUTION: An error correction decoding circuit comprises: an error pattern generation circuit 2 which generates an error pattern indicating an erratic place in a received word; a delay circuit 4 which holds information on the received word; a write control circuit 3 which writes a received word information symbol into the delay circuit 4 and does not write at least part of a received word inspection symbol into the delay circuit 4; a read control circuit 5 which reads out the received word information symbol written into the delay circuit 4 and does not read out at least part of the received word inspection symbol written into the delay circuit 4; and an exclusive OR circuit 6 which exclusive-OR the received word read out from the delay circuit 4 with the error pattern.

Description

  The present invention relates to an error correction decoding circuit for packet communication.

In the optical communication field, a method using a Reed-Solomon code that is a binary BCH code or a non-binary BCH code is known as an error correction method. Details of the binary BCH code and the Reed-Solomon code are described in Non-Patent Document 1 and Non-Patent Document 2, for example.
In recent years, there has been a growing demand for power saving in the field of optical communications, and it has become possible to reduce power consumption of communication devices by studying at the circuit level to enable the components of communication devices to save power, and by coordinating multiple communication devices. Studies at the protocol level are underway. For example, in communication, it is known that the daily traffic volume fluctuates. Therefore, there is a method of saving power by enabling and disabling a part of functions according to the traffic volume.

  In the study at the circuit level, it is necessary to consider the power saving of each circuit. Therefore, power saving is also required for the encoding circuit and decoding circuit of Reed-Solomon code and BCH code. In particular, since the decoding circuit performs more complicated processing than the encoding circuit, power consumption is large, and power saving of the decoding circuit is required.

  As an example of a conventional error correction decoding circuit for packet communication, RS (255, 223, 8) adopted in 10G-EPON (10 Gigabit-Ethernet (registered trademark) Passive Optical Network) of IEEE802.3av standard is taken as an example. This will be described with reference to FIGS. RS (255, 223, 8) indicates a Reed-Solomon code having a code length of 255 bytes, an information symbol length of 223 bytes, a check symbol length of 32 (= 255-223) bytes, and a byte length of 8 bits.

  Hereinafter, the received word format, functional blocks (delay circuit, error detection circuit, error pattern generation circuit, packet detection circuit), and timing chart will be described. The code word means a unit for processing a block code such as a Reed-Solomon code, and the received word means a unit for processing inside the circuit.

  An outline of the format of the received word is shown in FIG. Details of this format are described in Non-Patent Document 3 and Non-Patent Document 4. The received data string is obtained by converting an optical signal into an electric signal, serial-parallel conversion, and dividing it into 66-bit units. In the IEEE 802.3av standard, the received data string is a series of received codewords 100 as shown in FIG. 8, and each received codeword 100 is composed of a payload 101 and a parity 102. The payload 101 has 27 66-bit transmission blocks 103 and 104, and the parity 102 has 4 66-bit parity blocks 105. The 66-bit long blocks 103 to 105 each include a 2-bit header and a 64-bit data field. The data field portions of the 66-bit length transmission blocks 103 and 104 are scrambled so that the appearance probabilities of bit “0” and bit “1” are equal. The scramble process is described in Non-Patent Document 4. The data field portion of the 66-bit long parity block 105 includes 8 bytes of RS (255, 223, 8) check symbols.

  The 66-bit length transmission blocks 103 and 104 include a data block 103 including packet data and a control block 104 which is not packet data. In the case of the data block 103, the 2-bit header value is “01”, and the packet data is stored in the 64-bit data field. In the case of the control block 104, the 2-bit header is “10”, and various values are stored in the 64-bit data field. There are several types of control block 104, but a typical example is a fixed pattern idle control block. In the data field of the idle control block, 8 types of fixed value type code (0x1E) of 8 bits and 7 bits of idle code (0x00) are stored. However, the idle control block is not a fixed pattern due to the scramble process at the stage in the received data string. Other control blocks 104 include a start control block that indicates the beginning of a packet and a terminate control block that indicates the end of the packet.

  A received code word is extracted from the received data string, and a code word is formed from the received code word. In order to extract the codeword from the received data string, the first bit of the 2-bit header is removed from each of the 66-bit length transmission blocks 103 and 104 to generate 27 65-bit length transmission blocks 103a and 104a, An information symbol block 107 having a length of 223 bytes (= 27 × 65 bits + 29 bits) is obtained by adding a block 106 consisting of a continuous collection of 29 bits of “0” to the head of the 27 transmission blocks 103a and 104a. . Further, the header is removed from each 66-bit parity block 105 to generate four 64-bit parity blocks 105a, and these four parity blocks 105a are used as 32-byte check symbol blocks 108. The information symbol block 107 and the check symbol block 108 are used as a 255-byte code word 109 for error correction decoding processing.

  Therefore, the received word 110 having a length of 255 bytes is defined as the code word 109 divided into 1-byte units in this conventional example. Therefore, each byte of the code word 109 appears continuously in the received word 110.

  An example of a block diagram of an error correction decoding circuit in conventional packet communication is shown in FIG. The delay circuit 202 delays the received word 206 by the processing time of the error detection circuit 200 and the error pattern generation circuit 201, and outputs the delayed received word 207. The delay circuit 202 is generally composed of a memory, and consumes a large amount of power during write access and read access.

  The error detection circuit 200 calculates an error syndrome 208 from the received word 206. Details of the error syndrome 208 are described in Non-Patent Document 1 and Non-Patent Document 2. In the case of RS (255, 223, 8), there are 32 error syndromes 208. When all error syndromes 208 are “0”, it indicates that there is no error in the received word 206, and when at least one error syndrome 208 is not “0”, it indicates that there is an error in the received word 206.

  The error pattern generation circuit 201 performs processing for obtaining an error pattern 209 having a length of 255 bytes from the error syndrome 208. The error pattern 209 is all “0” when there is no error in the received word 206, and the bit where the error occurs is “1” when there is an error in the received word 206. If the error correction code is within the error correction capability range, it is possible to obtain an error pattern 209 in which all locations where errors occur are “1”. Therefore, communication systems and devices are usually designed so as not to exceed the error correction capability.

The exclusive OR circuit 203 corrects the error of the received word 207 by taking the exclusive OR of the received word 207 output from the delay circuit 202 and the error pattern 209, and outputs a corrected received word 210.
The packet detection circuit 205 deletes a check symbol from the corrected received word 210, detects a start control block, a termination control block, an idle control block, a data block, etc. stored in the information symbol, and deletes the idle control block. Thus, the packet data is reconstructed. At this time, since all the transmission blocks have been scrambled, the packet detection circuit 205 performs descrambling processing for releasing the scramble processing of the transmission blocks.

  FIG. 10 is a timing chart showing the operation of the error correction decoding circuit shown in FIG. The clock in FIG. 10 is generated in synchronization with each byte of the code word and the received word 206 by a clock generation means (not shown). Since the length of the code word and the reception word 206 is 255 bytes, the generation interval of the code word head flag 211 is 255 clocks. One clock after the code word head flag 211, D223 corresponding to the head symbol of the code word appears in the received word 206. In FIG. 10, D223 indicates the 223rd byte of the information symbol, and D1 indicates the 1st byte of the information symbol. When information symbols D223 to D1 are continuously received, the end of the information symbol block is reached. P32 indicates the 32nd byte of the check symbol, and P1 indicates the 1st byte of the check symbol. When the check symbols P32 to P1 are continuously received, the end of the check symbol block, that is, the end of the code word is obtained. Here, in order to receive D223 earliest, it is defined as the head symbol.

  A parity interval signal 214 is output in synchronization with the information symbol and check symbol of the received word 206. The parity interval signal 214 becomes significant (HIGH) when a check symbol appears in the received word 206 and becomes insignificant (LOW) when an information symbol appears in the received word 206. With regard to the definitions of significant and non-significant, in the present invention, hereinafter, significant is HIGH and non-significant is LOW. However, significance may be LOW and non-significance may be HIGH, and whether the significance is HIGH or LOW is determined at the time of circuit design.

  In this conventional example, the syndrome calculation of the error detection circuit 200 and the error correction processing of the error pattern generation circuit 201 are completed, and the timing at which the error pattern 209 corresponding to the codeword is output is determined at the time when the codeword reception is completed (see FIG. The time point was 100 clocks after t2). In FIG. 10, ED223 is an error pattern corresponding to information symbol D223, and ED1 is an error pattern corresponding to information symbol D1. EP32 is an error pattern corresponding to the check symbol P32, and EP1 is an error pattern corresponding to the check symbol P1.

The delay circuit 202 delays the received word 206 by the processing time of the error detection circuit 200 and the error pattern generation circuit 201, that is, 100 clocks, and outputs the delayed received word 207. As a result, the received word 207 is output from the delay circuit 202 so as to match the timing of the error pattern 209. For example, the information symbol D223 of the received word 207 is output from the delay circuit 202 in accordance with the symbol ED223 of the error pattern 209.
The exclusive OR circuit 203 performs exclusive OR of the received word 207 and the error pattern 209 and outputs the corrected received word 210 after one clock.

  The parity interval signal generation circuit 204 delays the parity interval signal 214 by a delay time obtained by adding the delay time of the delay circuit 202 (100 clocks) and the delay time of the exclusive OR circuit 203 (1 clock). A signal 212 is generated. The parity interval signal 212 becomes significant (HIGH) when a check symbol appears in the corrected received word 210 and becomes insignificant (LOW) when an information symbol appears in the corrected received word 210.

The packet detection circuit 205 reconstructs the packet 213 by deleting the check symbol from the corrected received word 210 and deleting the idle control block of the information symbol based on the timing of the parity interval signal 212.
The above is the outline of the operation of the conventional error correction decoding circuit.

In the optical communication field, since the data error rate is often small, the probability that there is no error is higher than the case where there is an error in the codeword. Therefore, it is expected that the effect will be great if the power saving of the decoding process is performed when there is no error in the codeword. The delay circuit 202 occupies most of the dynamic power consumption of the error correction decoding circuit when there is no error in the codeword.
In addition, when there is no traffic, in order to correct a code word consisting of a payload filled with an idle control block and a parity for detecting an error in the payload, in a conventional error correction decoding circuit, a received word is an idle control block. Even when only the word is included, the received word is written to and read from the delay circuit 202.

Hideki Imai, “Information Theory”, Shosodo, pp. 177, 1984, ISBN 4-7856-11139-1. Yoshikazu Nishimura, “Introduction to Digital Error Correction Technology in Wireless Data Communication”, CQ Publishing, pp. 77-94, 2004, ISBN 4-7898-397-6. IEEE802.3av-2009, pp. 124 “64B / 66B overview 10Gb / s phy for EPON SG”, <http://www.ieee802.org/3/10GEPON_study/public/july06/thaler_1_0706.pdf>

  As described above, in the conventional error correction decoding circuit, even when the code word does not include the data block and only the idle control block, the code word is always written to and read from the delay circuit. It was. Similarly, for the parity, writing to and reading from the delay circuit has always been performed. The reason why writing to and reading from the delay circuit is always performed in this manner is that there is a possibility that an error is included in the code word, and it is difficult to determine that only the idle control block is included.

  Therefore, in the conventional error correction decoding circuit, even when the code word includes only the idle control block, the power consumption cannot be reduced because the delay circuit consumes the same power as when the data block is included. was there. Further, the conventional error correction decoding circuit has a problem in that power consumption cannot be reduced because the check symbol block is always written to and read from the delay circuit.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an error correction decoding circuit and method capable of reducing power consumption as compared with the prior art.

  An error correction decoding circuit according to the present invention includes an error pattern generation circuit that generates an error pattern indicating an error portion of a received word, a delay circuit that holds information on the received word, and information on the received word written in the delay circuit A read control circuit that reads symbols and does not read at least some check symbols of the received word written in the delay circuit, and an arithmetic circuit that corrects the received word read from the delay circuit based on the error pattern; It is characterized by providing.

  The error correction decoding circuit of the present invention includes an error pattern generation circuit that generates an error pattern indicating an error portion of a received word, a delay circuit that holds information on the received word, and delays information symbols of the received word. A write control circuit for writing to the circuit and not writing at least a part of the check symbols of the received word to the delay circuit; and an arithmetic circuit for correcting the received word delayed by the delay circuit based on the error pattern. It is characterized by.

The error correction decoding circuit of the present invention includes an error detection circuit that generates error presence / absence information indicating presence / absence of an error in a received word, an error pattern generation circuit that generates an error pattern indicating an error location of the received word, A delay circuit that holds information of a received word, an idle prediction detection circuit that generates predicted idle information that is a result of predictive detection of an idle control block included in the received word, and a reception that is normally written in the delay circuit When both the information symbol and the check symbol of the word are read and the idle prediction information is significant and the error presence / absence information indicates no error, the significant idle prediction information and the error presence / absence information indicating no error are supported. A read control circuit that does not read at least part of the information symbols to be read from the delay circuit, and a received word read from the delay circuit It is characterized in further comprising an arithmetic circuit for correcting, based on the error pattern.
In addition, one configuration example of the error correction decoding circuit of the present invention further includes a write control circuit that does not write at least a part of the information symbol in the delay circuit when the idle control block is detected and detected. It is what.

  Further, the error correction decoding method of the present invention includes an error pattern generation step for generating an error pattern indicating an error location of a received word, and reading the information symbol of the received word written in the delay circuit, and writing the information symbol in the delay circuit A read control step that does not read at least a part of the check symbols of the received word, and a calculation step that corrects the received word read from the delay circuit based on the error pattern are provided.

  Also, the error correction decoding method of the present invention includes an error pattern generation step for generating an error pattern indicating an error location of a received word, writing information symbols of the received word to a delay circuit, and checking at least a part of the received word A write control step that does not write a symbol in the delay circuit, and a calculation step that corrects a received word delayed by the delay circuit based on the error pattern.

  The error correction decoding method of the present invention includes an error detection step for generating error presence / absence information indicating the presence / absence of an error in a received word, an error pattern generation step for generating an error pattern indicating an error location of the received word, Idle prediction detection step for generating predicted idle information that is a result of predictive detection of an idle control block included in a received word, and reading both the information symbol and the check symbol of the received word normally written in the delay circuit, When the idle prediction information is significant and the error presence / absence information indicates no error, at least a part of the information symbol corresponding to the significant idle prediction information and the error presence / absence information indicating no error is read from the delay circuit. A read control step that does not include the received word read from the delay circuit based on the error pattern. It is characterized in further comprising a calculating step for.

  According to the present invention, since at least a part of the check symbol is not read from the delay circuit, the number of read accesses to the delay circuit can be reduced, and the power consumption of the delay circuit can be reduced. As a result, in the present invention, the power consumption of the error correction decoding circuit can be reduced.

  In the present invention, since at least a part of the check symbol is not written to the delay circuit, the number of write accesses to the delay circuit can be reduced, and the power consumption of the delay circuit can be reduced. As a result, in the present invention, the power consumption of the error correction decoding circuit can be reduced.

  In the present invention, when the information symbol block of the received word includes an idle control block, at least part of the information symbol block is not read from the delay circuit, so that the number of read accesses to the delay circuit can be reduced, and the consumption of the delay circuit is reduced. Electric power can be reduced. As a result, in the present invention, the power consumption of the error correction decoding circuit can be reduced.

  Further, in the present invention, when the idle control block is predicted and detected, at least a part of the information symbol is not written in the delay circuit, so that the number of write accesses to the delay circuit can be reduced, and the power consumption of the delay circuit Can be reduced.

It is a block diagram which shows the structure of the error correction decoding circuit based on the 1st Embodiment of this invention. 3 is a timing chart illustrating an operation of the error correction decoding circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the error correction decoding circuit based on the 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the error correction decoding circuit based on the 2nd Embodiment of this invention. It is a flowchart which shows the operation | movement of the read-control circuit based on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the error correction decoding circuit based on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the error correction decoding circuit based on the 4th Embodiment of this invention. It is a figure which shows the format of a received word. It is a block diagram which shows the structure of the conventional error correction decoding circuit. It is a timing chart which shows operation | movement of the conventional error correction decoding circuit.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The first embodiment of the present invention is characterized by reducing the number of reads and writes of the delay circuit and reducing the power consumption by not writing and reading the check symbol block to and from the delay circuit.

  FIG. 1 is a block diagram showing the configuration of the error correction decoding circuit of this embodiment, and FIG. 2 is a timing chart showing the operation of the error correction decoding circuit of this embodiment. The error correction decoding circuit of the present embodiment includes an error detection circuit 1, an error pattern generation circuit 2, a write control circuit 3, a delay circuit 4, a read control circuit 5, an exclusive OR circuit 6, a parity. An interval signal generation circuit 7 and a packet detection circuit 8 are included. The difference between the present embodiment and the conventional example is that a write control circuit 3 and a read control circuit 5 are added.

The operation of the error correction decoding circuit according to this embodiment will be described below. As in the prior art, the clock in FIG. 2 is generated in synchronization with each byte of the code word and the received word 9 by a clock generation means (not shown). The generation interval of the code word head flag 16 is 255 clocks.
The error detection circuit 1 calculates an error syndrome 10 from the received word 9. The error pattern generation circuit 2 performs processing for obtaining an error pattern 11 having a length of 255 bytes from the error syndrome 10. Also in the present embodiment, the timing at which the syndrome calculation of the error detection circuit 1 and the error correction processing of the error pattern generation circuit 2 are completed and the error pattern 11 corresponding to the code word is output is determined at the time when the reception of the code word is completed ( The time point is 100 clocks after t2) in FIG.

  The parity interval signal generation circuit 7 generates a parity interval signal 17 based on the codeword head flag 16. The parity interval signal 17 becomes significant (HIGH) when a check symbol for 32 clocks appears in the received word 9 and becomes insignificant (LOW) when an information symbol appears in the received word 9.

  The write control circuit 3 outputs the received word 9 to the delay circuit 4 and generates a write instruction signal 13 based on the parity interval signal 17. The write instruction signal 13 becomes insignificant (LOW) when the parity interval signal 17 is significant (HIGH), that is, when a check symbol appears in the received word 9, and when the parity interval signal 17 is insignificant (LOW), that is, Significant (HIGH) when an information symbol appears in the received word 9.

  The write control circuit 3 writes the received word 9 to the delay circuit 4 when the write instruction signal 13 is significant (HIGH), and does not write to the delay circuit 4 when the write instruction signal 13 is insignificant (LOW). . Therefore, the received word 9 is not written to the delay circuit 4 during 32 clocks when the check symbols P32 to P1 are received. The delay circuit 4 delays the received word 9 by the processing time of the error detection circuit 1 and the error pattern generation circuit 2, that is, 100 clocks, and outputs the delayed received word 12.

  The parity interval signal generation circuit 7 delays the parity interval signal 17 by a delay time (99 clocks) obtained by subtracting the time (1 clock) required to read out the delay circuit 4 from the delay time (100 clocks) of the delay circuit 4. A parity interval signal 18 is generated. In this embodiment, 100 clocks are required for the processing of the error detection circuit 1 and the error pattern generation circuit 2, and 255 clocks are required for the reception of the code word. Therefore, the delay circuit 4 starts after 355 (= 255 + 100) clocks. In order to read a received word, the delay time of the parity interval signal 18 with respect to the parity interval signal 17 is set to 354 clocks.

  The read control circuit 5 generates a read instruction signal 14 based on the parity interval signal 18. The read instruction signal 14 becomes insignificant (LOW) when the parity interval signal 18 is significant (HIGH), that is, one clock before the timing at which the check symbol appears in the received word 12, and the parity interval signal 18 is insignificant. It becomes significant (HIGH) when (LOW), that is, one clock before the timing at which the information symbol appears in the received word 12.

  The read control circuit 5 reads the received word 12 from the delay circuit 4 when the read instruction signal 14 is significant (HIGH), and does not read from the delay circuit 4 when the read instruction signal 14 is insignificant (LOW). . Therefore, the read word 12 is not read from the delay circuit 4 during the 32 clocks in which the check symbols P32 to P1 appear in the receive word 12. For this reason, the value of the check symbol period of the received word 12 is indefinite. In FIG. 2, XX represents indefiniteness.

  The exclusive OR circuit 6, which is an arithmetic circuit, performs an exclusive OR of the received word 12 read from the delay circuit 4 and the error pattern 11 and outputs a corrected received word 15 after one clock. As described above, since the value of the check symbol period of the received word 12 is indefinite, the value of the check symbol period in the corrected received word 15 is also undefined. Since the value of the check symbol period is not used in the subsequent packet detection circuit 8, there is no problem even if the value of the period corresponding to the check symbol of the corrected received word 15 becomes indefinite.

  The read control circuit 5 has a parity corresponding to a delay time (2 clocks) obtained by adding a time (1 clock) required for reading the received word 12 from the delay circuit 4 and a delay time (1 clock) of the exclusive OR circuit 6. A parity interval signal 19 obtained by delaying the interval signal 18 is generated. The parity interval signal 19 becomes significant (HIGH) when a check symbol for 32 clocks appears in the corrected received word 15, and becomes insignificant (LOW) when an information symbol appears in the corrected received word 15.

The packet detection circuit 8 deletes the check symbol from the corrected received word 15 based on the timing of the parity interval signal 19, and also includes a start control block, a terminate control block, an idle control block stored in the information symbol of the corrected received word 15, The packet 20 is reconstructed by detecting a data block or the like and deleting the idle control block. At this time, since all the transmission blocks have been scrambled, the packet detection circuit 8 performs descrambling processing for releasing the scramble processing of the transmission blocks.
This is the end of the operation of the error correction decoding circuit of the present embodiment.

  In the present embodiment, the check symbol of the received word 9 is not written into the delay circuit 4, and the check symbol of the received word 12 that is delayed from the received word 9 is not read out from the delay circuit 4. 4 can be reduced, and the power consumption of the error correction decoding circuit can be reduced as compared with the prior art.

  In the present embodiment, the power reduction effect is increased without writing all the check symbols of the received word 9 to the delay circuit 4, but a part of the check symbols of the received word 9 may be written to the delay circuit 4. Even when a part of the check symbols is written, the power consumption can be reduced as compared with the case where all the check symbols are written in the delay circuit as in the prior art. Similarly, some check symbols of the received word 12 may be read from the delay circuit 4.

  Further, in this embodiment, the bit width of the received word is 8 bits, and one symbol is written to the delay circuit 4 every clock, and the delay circuit 4 is not written and read only for a period of 32 clocks. However, the bit width of the received word may be 40 bits (5 bytes) or other bit widths. For example, it may be 256 bits (32 bytes) or less in which a period in which a received word is composed of only check symbols exists for one clock or more. At this time, the parity interval signal is configured to be significant when only the check symbol is included in the received word, and is insignificant when the received word includes symbols other than the check symbol.

  In the present embodiment, significance is set to HIGH and insignificance is set to LOW. However, significance may be set to LOW and nonsignificance may be set to HIGH. Further, the association between significant / insignificant and HIGH / LOW may be changed for each signal.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. The second embodiment of the present invention predicts and detects an idle control block in the decoding process of RS (255, 223, 8), and when it is determined that there is no error in a portion determined to be an idle control block, The idle control block portion is not read from the delay circuit. Thereby, in the present embodiment, the number of read accesses of the delay circuit is reduced and the power consumption is reduced.

  FIG. 3 is a block diagram showing the configuration of the error correction decoding circuit of this embodiment, and FIG. 4 is a timing chart showing the operation of the error correction decoding circuit of this embodiment. The error correction decoding circuit of the present embodiment includes an error detection circuit 1a, an error pattern generation circuit 2, a delay circuit 4, a read control circuit 5a, an exclusive OR circuit 6, and a parity interval signal generation circuit 7a. The packet detection circuit 8a and the idle prediction detection circuit 21 are provided. The difference between the present embodiment and the conventional example is that a read control circuit 5a and an idle prediction detection circuit 21 are added.

The operation of the error correction decoding circuit according to this embodiment will be described below. As in the prior art, the clock in FIG. 4 is generated in synchronization with each byte of the code word and the received word 9 by clock generation means (not shown).
The error detection circuit 1 a calculates an error syndrome 10 from the received word 9. Further, the error detection circuit 1a outputs error presence / absence information 22 of the received word 9. The error presence / absence information 22 becomes non-significant (LOW) when any of the error syndromes 10 is “0” (no error in the received word 9), and significant when at least one error syndrome 10 is not “0”. (HIGH).

The error pattern generation circuit 2 performs processing for obtaining an error pattern 11 having a length of 255 bytes from the error syndrome 10. Also in the present embodiment, the timing at which the syndrome calculation of the error detection circuit 1a and the error correction processing of the error pattern generation circuit 2 are completed and the error pattern 11 corresponding to the code word is output is determined at the time when the reception of the code word is completed ( The time is 100 clocks after t3) in FIG.
The delay circuit 4 delays the received word 9 by the processing time of the error detection circuit 1a and the error pattern generation circuit 2, that is, 100 clocks, and outputs the delayed received word 12.

  The idle prediction detection circuit 21 receives the received data string 23 and the codeword head flag 16 and outputs prediction idle information 24 that is a result of predicting and detecting an idle control block. Specifically, the idle prediction detection circuit 21 detects 27 transmission blocks corresponding to the information symbol block of the code word based on the timing of the code word head flag 16, and all the 27 transmission blocks are idle. When the control block matches the fixed pattern of the control block, the predicted idle information 24 becomes significant (HIGH) in the period of 223 clocks in which the 27 transmission blocks appear in the received word 12, and in the remaining 32 clock periods of the received word 12 The predicted idle information 24 is assumed to be insignificant (LOW).

Further, the idle prediction detection circuit 21 makes the prediction idle information 24 non-significant in all periods of the received word 12 having a length of 255 bytes when at least one of the 27 transmission blocks does not match the fixed pattern of the idle control block ( LOW).
The received word 12 is read from the delay circuit 4 after 355 (= 255 + 100) clocks from the reception start time of the code word (t1 in FIG. 4), but it takes one clock time to read the received word 12 from the delay circuit 4. It takes. Therefore, when all 27 transmission blocks match the fixed pattern of the idle control block, the idle prediction detection circuit 21 determines that the predicted idle information 24 is significant after 354 (= 255 + 100−1) clocks from the reception start time of the codeword ( HIGH).

  Since the data field of the transmission block is scrambled so that the appearance probabilities of bit “0” and bit “1” are equal, the idle prediction detection circuit 21 descrambles for the detection of the idle control block. A circuit (not shown) is provided inside. In FIG. 4, the data string after the descrambling process is described as a received data string 27. Details of the descrambling circuit are described in Non-Patent Document 3, for example.

  The read control circuit 5a outputs a read instruction signal 14 to the delay circuit 4, and outputs fixed idle information 25 to the packet detection circuit 8a. A characteristic of the read control circuit 5a is that the read instruction signal 14 is made insignificant (LOW) when the predicted idle information 24 is significant (HIGH). However, the prediction by the idle prediction detection circuit 21 may be off. Prediction may be lost when there is a bit error in the current codeword and when there is a bit error in the immediately preceding codeword.

If there is an error in the current codeword, a transmission block that is not an idle control block may coincide with the pattern of the idle control block.
In addition, even when there is a bit error in the transmission block at the end (D9 to D1) of the information symbol block of the immediately preceding code word, a transmission block that is not an idle control block may coincide with the pattern of the idle control block. In the descrambling circuit in the idle prediction detection circuit 21, in order to correctly perform descrambling processing on a certain transmission block, transmission frame data having no bit error immediately before it is necessary. This is because the descrambling circuit uses the information for the previous 56 bits.

  In view of the above, the read control circuit 5a outputs a read instruction signal 14 according to the flowchart of FIG. Specifically, the read control circuit 5a indicates that the error presence / absence information 22 of the immediately preceding codeword indicates no error (insignificant), the error / absence information 22 of the current codeword indicates no error, and predictive idle information When 24 is significant (HIGH) and is not in a period corresponding to the last transmission block included in the information symbol of the code word (YES in step S1), the read instruction signal 14 is made insignificant (LOW) ( Step S2).

  Further, the read control circuit 5a calculates the time (1 clock) required for reading the received word 12 from the delay circuit 4 and the delay time (1 clock) of the exclusive OR circuit 6 when step S1 is YES. Confirmed idle information 25 is generated by delaying the predicted idle information 24 by the added delay time (2 clocks) (step S2). That is, when the 27 transmission blocks of the corrected received word 15 include only the idle control block, the definite idle information 25 is significant (HIGH) in the period of 223 clocks in which the 27 transmission blocks appear in the corrected received word 15. Become.

  Further, the read control circuit 5a indicates that the error presence / absence information 22 of the immediately preceding code word indicates that there is an error (significant), that the error presence / absence information 22 of the current code word indicates that there is an error, and that the predicted idle information 24 is When at least one of the non-significant (LOW) and the period corresponding to the last transmission block is applicable (NO in step S1), the read instruction signal 14 is made significant (HIGH) (step) S3). Further, the read control circuit 5a sets the confirmed idle information 25 to be insignificant (LOW) when step S1 is NO (step S3).

The read control circuit 5a reads the received word 12 from the delay circuit 4 when the read instruction signal 14 is significant (HIGH), and does not read from the delay circuit 4 when the read instruction signal 14 is insignificant (LOW). .
For a code word that has started to be received 255 clocks before time t1 in FIG. 4, the prediction idle information 24 is significant (HIGH) during the period (time t2 to t4 in FIG. 4) in which the read control circuit 5a processes this code word. However, the error presence / absence information 22 (error presence / absence information 22 before time t2) of the immediately preceding code word is significant (HIGH). For this reason, the read control circuit 5a sets the read instruction signal 14 to significant (HIGH) and sets the definite idle information 25 to insignificant (LOW).

  Further, for the code word that has started to be received at time t1 in FIG. 4, the predicted idle information 24 is significant (HIGH) in the period (time t4 to t6 in FIG. 4) during which the read control circuit 5a processes this code word. In addition, the error presence / absence information 22 (error presence / absence information 22 before time t4) of the immediately preceding codeword is not significant (LOW). For this reason, the read control circuit 5a sets the read instruction signal 14 to insignificant (LOW) and sets the definite idle information 25 to significant (HIGH). However, the read control circuit 5a makes the read instruction signal 14 significant (HIGH) for the period corresponding to the last transmission block (65 bits, 9 clocks).

  The exclusive OR circuit 6 performs an exclusive OR of the received word 12 read from the delay circuit 4 and output from the read control circuit 5a and the error pattern 11, and outputs a corrected received word 15 after one clock.

  The parity interval signal generation circuit 7a is the first embodiment corresponding to the delay time (101 clocks) obtained by adding the delay time of the delay circuit 4 (100 clocks) and the delay time of the exclusive OR circuit 6 (1 clock). The parity interval signal 26 is generated by delaying the parity interval signal 17 of. The parity interval signal 26 becomes significant (HIGH) when a check symbol for 32 clocks appears in the corrected received word 15, and becomes insignificant (LOW) when an information symbol appears in the corrected received word 15.

  The packet detection circuit 8a deletes the check symbol from the corrected received word 15 based on the timing of the parity interval signal 26, and starts control block, terminate control block, idle control block, data stored in the information symbol of the corrected received word 15 By detecting a block or the like, the idle control block is deleted, and when the determined idle information 25 is significant (HIGH), all the idle control blocks are deleted to reconstruct the packet 20. At this time, since all the transmission blocks are scrambled, the packet detection circuit 8a performs a descrambling process for releasing the scramble process of the transmission block. This is the end of the operation of the error correction decoding circuit of the present embodiment.

  In the present embodiment, when the idle control block is predicted and detected and it is determined that there is no error in the portion determined to be the idle control block, the portion of the idle control block is not read from the delay circuit 4, The power required for reading out the delay circuit 4 can be reduced, and the power consumption of the error correction decoding circuit can be reduced as compared with the prior art.

In the present embodiment, an example in which the bit width of the received word is 8 bits and one symbol is written to the delay circuit 4 every clock is shown. However, the bit width of the received word is 40 bits (5 Bytes) or other bit widths.
In this embodiment, D223 to D221 having a value of “0” appear in the received word. However, since it is “0”, it may be omitted and may be configured as one codeword with 252 clocks. .

Further, in the present embodiment, an example in which the read instruction signal 14 is made insignificant (LOW) in units of one codeword when all the codewords are idle control blocks is shown. The read instruction signal 14 may be insignificant (LOW) for the coincidence section. However, for the first and last transmission blocks included in the coincidence section, the read instruction signal 14 needs to be significant (HIGH) regardless of whether there is an error.
In the present embodiment, the predicted idle detection circuit 21 receives a received data string, but may receive a received word.

  In the present embodiment, the codeword configuration conforms to IEEE802.3av, and an example in which a descrambling circuit is required for the received data string in order to detect an idle control block is shown. However, IEEE802.3av is shown. When conversion is performed on the received data string, the same effect can be obtained by providing a conversion circuit for converting the received data string into a form that can be detected by the idle control block. Examples of such a conversion circuit include a conversion circuit that performs a deinterleave process for exchanging the positions of received data strings, and a conversion circuit that performs a descrambling process different from the IEEE 802.3av standard.

  In the present embodiment, the codeword configuration conforms to IEEE802.3av, and an example in which a descrambling circuit is necessary for detecting an idle control block has been shown. However, in general, the idle control block has a fixed pattern. In some cases, a descrambling circuit is unnecessary, and a configuration in which the received word is compared may be used.

  In the present embodiment, the writing to the delay circuit 4 is also performed when the transmission block of the received word 9 matches the fixed pattern of the idle control block. However, the transmission block of the received word 9 is changed to the fixed pattern of the idle control block. When there is no dependency relationship with the preceding and following received words, a write control circuit is added so that the received word 9 is not written in the delay circuit 4 only in the section that matches the fixed pattern of the idle control block, and based on the idle prediction information Thus, the read control circuit 5a may output the same pattern as the idle control block as the received word 12.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the error correction decoding circuit according to the present embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals. The error correction decoding circuit of this embodiment includes an error detection circuit 1, an error pattern generation circuit 2, a write control circuit 3, a delay circuit 4, an exclusive OR circuit 6, and a parity interval signal generation circuit 7b. And a packet detection circuit 8.

  In the present embodiment, the read control circuit 5 is deleted from the first embodiment. Since there is no read control circuit 5, the parity interval signal generation circuit 7b has a parity interval signal 28 obtained by delaying the parity interval signal 18 of the first embodiment by the delay time (one clock) of the exclusive OR circuit 6. And output to the packet detection circuit 8. The operation of the other configuration is as described in the first embodiment.

  Thus, in this embodiment, since the check symbol of the received word 9 is not written in the delay circuit 4, the power required for writing in the delay circuit 4 can be reduced, and the error correction decoding circuit can be reduced as compared with the prior art. Power consumption can be reduced.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the error correction decoding circuit according to the present embodiment. The same components as those shown in FIG. The error correction decoding circuit of the present embodiment includes an error detection circuit 1, an error pattern generation circuit 2, a delay circuit 4, a read control circuit 5, an exclusive OR circuit 6, and a parity interval signal generation circuit 7c. And a packet detection circuit 8.

  In the present embodiment, the write control circuit 3 is omitted from the first embodiment. The operation of the parity interval signal generation circuit 7c is the same as that of the parity interval signal generation circuit 7 of the first embodiment except that the parity interval signal 17 is not output to the outside.

  Thus, in the present embodiment, since the check symbol of the received word 12 obtained by delaying the received word 9 is not read from the delay circuit 4, the power required for reading the delay circuit 4 can be reduced. In comparison, the power consumption of the error correction decoding circuit can be reduced.

In addition, this invention is not limited to the above-mentioned thing, Of course, it changes in the range which does not deviate from the summary of this invention. It is obvious that the decoding method of the present invention can be implemented by a microcomputer, a software program using a network processor, or a logic circuit such as an LSI.
For example, the error correction decoding circuit can be realized by a computer having a CPU, a storage device, and an interface, and a program for controlling these hardware resources. The CPU executes the processes described in the first to fourth embodiments in accordance with a program stored in the storage device.

  The present invention can be applied to an error correction decoding circuit.

  DESCRIPTION OF SYMBOLS 1,1a ... Error detection circuit, 2 ... Error pattern generation circuit, 3 ... Write control circuit, 4 ... Delay circuit, 5, 5a ... Read control circuit, 6 ... Exclusive OR circuit, 7, 7a, 7b, 7c ... Parity interval signal generation circuit, 8, 8a ... packet detection circuit, 21 ... idle prediction detection circuit.

Claims (8)

An error pattern generation circuit for generating an error pattern indicating an error part of the received word;
A delay circuit for holding the received word information;
A read control circuit that reads information symbols of received words written in the delay circuit and does not read at least some check symbols of the received words written in the delay circuit;
An error correction decoding circuit comprising: an arithmetic circuit that corrects a received word read from the delay circuit based on the error pattern. An error pattern generation circuit for generating an error pattern indicating an error part of the received word;
A delay circuit for holding the received word information;
A write control circuit that writes information symbols of the received word to the delay circuit, and does not write at least some check symbols of the received word to the delay circuit;
An error correction decoding circuit comprising: an arithmetic circuit that corrects a received word delayed by the delay circuit based on the error pattern. An error detection circuit for generating error presence / absence information indicating the presence / absence of an error in the received word;
An error pattern generation circuit for generating an error pattern indicating an error part of the received word;
A delay circuit for holding the received word information;
An idle prediction detection circuit that generates predicted idle information that is a result of predictive detection of an idle control block included in the received word;
Normally, when both the information symbol and the check symbol of the received word written in the delay circuit are read and the idle prediction information is significant and the error presence / absence information indicates no error, the significant idle prediction information A read control circuit that does not read from the delay circuit at least a part of the information symbol corresponding to the error presence information indicating no error, and
An error correction decoding circuit comprising: an arithmetic circuit that corrects a received word read from the delay circuit based on the error pattern. The error correction decoding circuit according to claim 3,
The error correction decoding circuit further comprises a write control circuit that does not write at least a part of the information symbol in the delay circuit when the idle control block is predicted and detected. An error pattern generation step for generating an error pattern indicating an error part of the received word;
A read control step of reading information symbols of the received word written in the delay circuit and not reading at least a part of the check symbols of the received word written in the delay circuit;
An error correction decoding method comprising: an arithmetic step of correcting a received word read from the delay circuit based on the error pattern. An error pattern generation step for generating an error pattern indicating an error part of the received word;
A write control step of writing information symbols of the received word to a delay circuit, and not writing at least a part of the check symbols of the received word to the delay circuit;
An error correction decoding method comprising: an arithmetic step of correcting a received word delayed by the delay circuit based on the error pattern. An error detection step for generating error presence / absence information indicating presence / absence of an error in the received word;
An error pattern generation step of generating an error pattern indicating an error part of the received word;
Idle prediction detection step for generating predicted idle information that is a result of predictive detection of an idle control block included in the received word;
Normally, both the information symbol and the check symbol of the received word written in the delay circuit are read, and when the idle prediction information is significant and the error presence / absence information indicates no error, the significant idle prediction information and A read control step of not reading at least a part of the information symbol corresponding to the error presence / absence information indicating no error from the delay circuit;
An error correction decoding method comprising: an arithmetic step of correcting a received word read from the delay circuit based on the error pattern. The error correction decoding method according to claim 7,
The error correction decoding method further comprises a write control step of not writing at least a part of the information symbol in the delay circuit when the idle control block is detected and detected.

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