JP2013251306A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which does not affect the characteristics of a signal processing circuit even when light is shielded by using multiple wiring layers disposed in a lamination manner.SOLUTION: A semiconductor device according to one embodiment includes an eighth wiring layer 8, a seventh wiring layer 7, and a sixth wiring layer 6 which are provided above a substrate 10 having a transistor formation region 30. The eighth wiring layer 8 has a slit. The seventh wiring layer 7 includes a light shielding layer 7a and a connection layer 7b. The light shielding layer 7a is provided below the eighth wiring layer 8 so as to cover the slit of the eighth wiring layer 8. The sixth wiring layer 6 includes a light shielding layer 6a and a connection layer 6b. The light shielding layer 6a is provided below the seventh wiring layer 7 so as to cover a slit of the seventh wiring layer 7. The eighth wiring layer 8 is connected with the light shielding layer 6a by a seventh via 27 and a sixth via 26. Electric potential of the eighth wiring layer 8 and the light shielding layer 6a differs from electric potential of the light shielding layer 7a.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for an optical semiconductor device, for example.

  In photodiodes, phototransistors, infrared sensors, and the like, which are typical optical semiconductors, a light receiving portion that performs light detection and an internal signal processing circuit are generally formed on the same silicon substrate.

  In the photodiode, the upper layer metal wiring is not disposed above the light receiving portion, and light is easily incident. On the other hand, above the internal signal processing circuit, an upper metal wiring is arranged on the entire surface in order to suppress the photoelectric effect caused by the incidence of light on the internal signal processing circuit. In anticipation of the wiring shield effect, the upper metal wiring is connected to the GND potential or the like.

  In recent years, microfabrication and multilayer wiring of semiconductor devices have been advanced. In a multi-layered semiconductor device, the logic of a signal processing circuit is generally constituted by a low-layer metal wiring, and the upper-layer metal wiring is generally used as a power supply wiring or a GND wiring. This is because the upper metal wiring is thicker than the lower metal wiring, so that the impedance can be easily reduced.

  Although it is desirable to dispose the uppermost layer metal wiring on the entire surface for light shielding, the uppermost layer metal wiring is generally a comb-shaped wiring or a mesh wiring structure due to the limitation of the metal wiring density in a fine process.

  Patent Document 1 discloses a semiconductor device having a plurality of first wiring layers and second wiring layers that shield a light-shielded region provided with transistor elements and the like. The plurality of first wiring layers are arranged at predetermined intervals in consideration of wiring density and the like. The second wiring layer is formed in an upper layer of the first wiring layer via an interlayer insulating film. The second wiring layer is located between the adjacent first wiring layers, and a part of the second wiring layer overlaps the first wiring layer.

  At the position where the first wiring layer and the second wiring layer overlap, the first wiring layer is connected to the second wiring layer through a via formed in the interlayer insulating film. The light shielding region is covered with at least one of the first wiring layer and the second wiring layer. In order to prevent the incidence of light from the lateral direction, a via connecting the first wiring layer and the second wiring layer is used as a light shielding wall. Patent Documents 2 and 3 also describe structures similar to the semiconductor device described in Patent Document 1.

Japanese Patent No. 03561463 JP 2006-186043 A Patent No. 0470857

  The semiconductor device described in Patent Document 1 has a problem that a malfunction of the signal processing circuit may occur. The reason will be described. The multi-layer wiring process has many limitations because it requires optimization of metal wiring density and pattern uniformity during layout design, and planarization of the wiring by CMP (Chemical Mechanical Polishing) during device manufacturing.

  In Patent Document 1, light is blocked by two upper wiring layers connected by vias. For this reason, all of these two wiring layers are metal wirings having the same potential. As a result, the metal wiring of the power supply potential or the GND potential may be extremely biased to the upper part of the signal processing circuit. If the power supply voltage drop or the GND potential floats, the characteristics of the signal processing circuit may be affected.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device has first, second, and third wiring layers provided above a semiconductor layer having a light-shielded region. The first wiring layer has a first slit. The second wiring layer has a second slit, and is provided below the first wiring layer so as to cover the first slit. The third wiring layer has a third slit, and is provided below the second wiring layer so as to cover the second slit. The first wiring layer and the third wiring layer are connected by the first via, and the potentials of the first wiring layer and the third wiring layer are different from the potential of the second wiring layer.

  According to the embodiment, it is possible to provide a semiconductor device that does not affect the characteristics of the signal processing circuit even when light shielding is performed using a plurality of wiring layers arranged in a stacked manner.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 8 is a top view of portions of an eighth wiring layer 8, a seventh interlayer insulating layer 17, a seventh via 27, and a seventh wiring layer 7 of the semiconductor device of FIG. FIG. 7 is a top view of the seventh wiring layer 7, the sixth interlayer insulating layer 16, the sixth via 26, and the sixth wiring layer 6 of the semiconductor device of FIG. FIG. 7 is a top view of a sixth wiring layer 6, a fifth interlayer insulating layer 15, a fifth via 25, and a fifth wiring layer 5 of the semiconductor device of FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a top view of a portion A of the semiconductor device of FIG. 5. FIG. 6 is a top view of part B of the semiconductor device of FIG. 5. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. It is the figure which looked at the A section of the semiconductor device of FIG. 7 from the upper surface. It is the figure which looked at the B section of the semiconductor device of FIG. 7 from the upper surface.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description will be omitted. In addition, the following description will be divided into a plurality of embodiments, but unless otherwise specified, they are not irrelevant to each other, and one is a modification, details, and supplements of a part or all of the other. There is a relationship such as explanation.

  Embodiments relate to a wiring structure of a semiconductor device (LSI: Large Scale Integration), and more particularly to a wiring structure of an optical semiconductor device such as a photodiode, a phototransistor, an infrared sensor, or the like. The embodiment relates to a technique for shielding light incident on a light receiving unit such as an optical sensor of an optical semiconductor device so as not to reach an internal signal processing circuit.

  The semiconductor device according to the embodiment includes first, second, and third wiring layers provided above a semiconductor layer having a light-shielded region. The first wiring layer has a first slit. The second wiring layer has a second slit, and is provided below the first wiring layer so as to cover the first slit. The third wiring layer has a third slit, and is provided below the second wiring layer so as to cover the second slit. The first wiring layer and the third wiring layer are connected by the first via, and the potentials of the first wiring layer and the third wiring layer are different from the potential of the second wiring layer.

  Even when a slit is provided in the wiring layer due to restrictions on the wiring density or the like, the slit can be covered with another wiring layer, so that the light-shielded region can be reliably shielded from light. Further, by connecting the first wiring layer and the third wiring layer with vias, it is possible to block light incident from an oblique direction. Furthermore, by alternately arranging wiring layers having different potentials, it is possible to suppress the influence on the characteristics of the signal processing circuit.

Embodiment 1 FIG.
A semiconductor device 100 according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a substrate 10, a first wiring layer 1 to an eighth wiring layer 8, a first interlayer insulating layer 11 to a seventh interlayer insulating layer 17, a cover insulating layer 18, a first via 21 to a seventh via 27, a transistor. A formation region 30, an impurity region 31, a gate electrode 32, a P-type well region 33, and an N-type well region 34 are included.

  A transistor forming region 30 which is a light-shielded region is formed on the substrate 10 which is a P-type silicon substrate. Three impurity regions 31 are formed in the transistor formation region 30. Gate electrodes 32 are respectively provided at positions corresponding to the impurity regions 31 on the substrate 10. In the substrate 10, a P-type well region 33 and an N-type well region 34 are formed independently of each other in a region away from the transistor formation region 30.

  The first embodiment shows an example in which eight wiring layers are provided. On the substrate 10, the first wiring layer 1 to the eighth wiring layer 8 and the first interlayer insulating layer 11 to the seventh interlayer insulating layer 17 are alternately stacked. The first wiring layer 1 is formed on the region of the substrate 10 where the P-type well region 33, the N-type well region 34, and the impurity region 31 are formed. A first interlayer insulating layer 11 is formed on the first wiring layer 1. A second wiring layer 2 is formed on the first interlayer insulating layer 11. The first wiring layer 1 and the second wiring layer 2 are connected by a first via 21 provided in the first interlayer insulating layer 11.

  A second interlayer insulating layer 12 is formed on the second wiring layer 2. A third wiring layer 3 is formed on the second interlayer insulating layer 12. The second wiring layer 2 and the third wiring layer 3 are connected by a second via 22 provided in the second interlayer insulating layer 12. A third interlayer insulating layer 13 is formed on the third wiring layer 3. A fourth wiring layer 4 is formed on the third interlayer insulating layer 13. The third wiring layer 3 and the fourth wiring layer 4 are connected by a third via 23 provided in the third interlayer insulating layer 13. A fourth interlayer insulating layer 14 is formed on the fourth wiring layer 4. A fifth wiring layer 5 is formed on the fourth interlayer insulating layer 14. The fourth wiring layer 4 and the fifth wiring layer 5 are connected by a fourth via 24 provided in the fourth interlayer insulating layer 14.

  In the semiconductor device 100 according to the first embodiment, the eighth wiring layer 8, the seventh wiring layer 7, the sixth wiring layer 6, and the fifth wiring layer are provided so that at least the transistor formation region 30 that is a light shielding region is shielded from light. 5 is arranged. Due to design restrictions such as wiring density, slits are formed in the eighth wiring layer 8. A seventh wiring layer 7 is provided below the eighth wiring layer 8 via a seventh interlayer insulating layer 17.

  The seventh wiring layer 7 includes a light shielding layer 7a and a connection layer 7b. The light shielding layers 7a and the connection layers 7b are formed in the same process and are alternately arranged in the horizontal direction. A slit is formed between the light shielding layer 7a and the connection layer 7b. Normally, when light enters from the slit of the eighth wiring layer 8, the light reaches the seventh wiring layer 7 because the seventh interlayer insulating layer 17 has a high light transmittance. In the first embodiment, the light shielding layer 7 a is disposed so as to cover the slit of the eighth wiring layer 8.

  The incident angle of light reaching the lower wiring layer is determined by the size of the slit of the eighth wiring layer 8 and the thickness of the eighth wiring layer 8. The light shielding layer 7 a disposed under the slit of the eighth wiring layer 8 is formed with a size capable of blocking the light according to the incident angle of the light incident from the slit of the eighth wiring layer 8.

  The connection layer 7 b is disposed under the eighth wiring layer 8. The connection layer 7 b and the eighth wiring layer 8 are electrically connected by a seventh via 27 provided in the seventh interlayer insulating layer 17. The light shielding layer 7 a is not connected to the eighth wiring layer 8.

  A sixth wiring layer 6 is provided below the seventh wiring layer 7 via a sixth interlayer insulating layer 16. The sixth wiring layer 6 includes a light shielding layer 6a and a connection layer 6b. The light shielding layers 6a and the connection layers 6b are formed in the same process and are alternately arranged in the horizontal direction. A slit is formed between the light shielding layer 6a and the connection layer 6b.

  When light enters from the slit of the eighth wiring layer 8, the light reaches the sixth wiring layer 6 through the seventh interlayer insulating layer 17, the slit of the seventh wiring layer 7, and the sixth interlayer insulating layer 16. There is a case. In the first embodiment, the light shielding layer 6 a is disposed so as to cover the slit of the seventh wiring layer 7 in order to shield this light. The light shielding layer 6a is formed in a size capable of blocking the light according to the incident angle of the light incident from the slit of the seventh wiring layer 7.

  The connection layer 6b is disposed under the light shielding layer 7a. The connection layer 6 b and the light shielding layer 7 a are electrically connected by a sixth via 26 provided in the sixth interlayer insulating layer 16. The light shielding layer 6a is connected to the connection layer 7b. Therefore, the light shielding layer 6 a is connected to the eighth wiring layer 8 through the seventh via 27, the connection layer 7 b, and the sixth via 26.

  A fifth wiring layer 5 is provided below the sixth wiring layer 6 via a fifth interlayer insulating layer 15. The fifth wiring layer 5 includes a light shielding layer 5a and a connection layer 5b. The light shielding layers 5a and the connection layers 5b are formed in the same process and are alternately arranged in the horizontal direction. A slit is formed between the light shielding layer 5a and the connection layer 5b.

  When light enters from the slit of the eighth wiring layer 8, the light may reach the sixth wiring layer 6. In the first embodiment, the light shielding layer 5 a is disposed so as to cover the slit of the sixth wiring layer 6 in order to shield this light. The light shielding layer 5a is formed with a size capable of blocking the light according to the incident angle of the light incident from the slit of the sixth wiring layer 6.

  The connection layer 5b is disposed under the light shielding layer 6a. The connection layer 5 b and the light shielding layer 6 a are electrically connected by a fifth via 25 provided in the fifth interlayer insulating layer 15. The light shielding layer 5a is connected to the connection layer 6b. Therefore, the light shielding layer 5a is connected to the light shielding layer 7a through the sixth via 26, the connection layer 6b, and the fifth via 25.

  Here, with reference to FIGS. 2 to 4, the structure viewed from the top surface of the semiconductor device 100 according to the first embodiment will be described. FIG. 2 is a top view of the portion (IA) of the eighth wiring layer 8, the seventh interlayer insulating layer 17, the seventh via 27, and the seventh wiring layer 7 of the semiconductor device 100 of FIG. A cross-sectional view taken along the line IA-IA in FIG. 2 is shown in FIG. As shown in FIG. 2, the slit between the eighth wiring layers 8 is closed by the light shielding layer 7a. On the connection layer 7b, a plurality of seventh vias 27 are provided along the longitudinal direction. The eighth wiring layer 8 and the connection layer 7 b are connected by the seventh via 27.

  FIG. 3 is a top view of the seventh wiring layer 7, the sixth interlayer insulating layer 16, the sixth via 26, and the sixth wiring layer 6 (IB) of the semiconductor device of FIG. A cross-sectional view taken along the line IB-IB in FIG. 3 is shown in FIG. As shown in FIG. 3, the slit between the light shielding layer 7a and the connection layer 7b is closed by the light shielding layer 6a. A plurality of sixth vias 26 are provided on the connection layer 6b along the longitudinal direction. The light shielding layer 7 a and the connection layer 6 b are connected by the sixth via 26. A plurality of sixth vias 26 arranged along the longitudinal direction are also provided on the light shielding layer 6a. The connection layer 7 b and the light shielding layer 6 a are connected by a sixth via 26.

  FIG. 4 is a top view of a portion (IC) of the sixth wiring layer 6, the fifth interlayer insulating layer 15, the fifth via 25, and the fifth wiring layer 5 of the semiconductor device of FIG. A sectional view taken along the line IC-IC in FIG. 4 is shown in FIG. As shown in FIG. 4, the slit between the light shielding layer 6a and the connection layer 6b is closed by the light shielding layer 5a. On the connection layer 5b, a plurality of fifth vias 25 are provided along the longitudinal direction. The light shielding layer 6 a and the connection layer 5 b are connected by the fifth via 25. A plurality of fifth vias 25 arranged along the longitudinal direction are also provided on the light shielding layer 5a. The connection layer 6b and the light shielding layer 5a are connected by a fifth via 25.

  According to the first embodiment, the light from the slit formed in the upper wiring layer is blocked by the light shielding layer disposed in the lower layer. Further, the seventh via 27, the sixth via 26, and the fifth via 25 can block light incident from an oblique direction. Thereby, fluctuations in characteristics due to light of elements formed in the transistor formation region 30 can be suppressed.

  Since the upper wiring layer is thicker than the lower wiring layer, by supplying a GND potential (ground potential) and a VDD potential (power supply potential), impedance can be reduced and a wiring shielding effect can be obtained. it can. For example, the GND potential can be supplied to the uppermost eighth wiring layer 8. The eighth wiring layer 8 is connected to the connection layer 7 b through the seventh via 27. The connection layer 7 b is connected to the light shielding layer 6 a through the sixth via 26. For this reason, the light shielding layer 6a becomes a GND potential.

  A VDD potential can be supplied to the light shielding layer 7a. The light shielding layer 7 a is connected to the connection layer 6 b through the sixth via 26. Since the connection layer 6b is connected to the light shielding layer 5a via the fifth via 25, the light shielding layer 5a has a VDD potential. Thus, in the first wiring layer 1 according to the first embodiment, the wiring layers to which the VDD potential is supplied and the wiring layers to which the GND potential is supplied are alternately arranged.

  Normally, when a signal processing circuit or the like operates at a high speed, if the operating current rises and the wiring impedance is biased, a voltage drop is noticeable and the circuit characteristics are affected. However, according to the first embodiment, the wiring of the power supply potential or the GND potential is not extremely biased to the upper part of the signal processing circuit, and it is possible to prevent a malfunction due to the impedance bias.

  Further, parasitic capacitance is formed between the eighth wiring layer 8, the sixth wiring layer 6, and the seventh wiring layer 7 connected by the seventh via 27, the connection layer 7 b, and the sixth via 26. In addition, a parasitic capacitance is formed between the light shielding layer 7 a and the light shielding layer 5 a connected by the sixth via 26, the connection layer 6 b, and the fifth via 25, and the sixth wiring layer 6. Thereby, the voltage drop of VDD and GND can be suppressed.

  Further, different potentials (VDD, GND) are supplied to the light shielding layer 5a and the connection layer 5b. The light shielding layers 5a and the connection layers 5b are alternately arranged in the horizontal direction. For this reason, by using the light shielding layer 5a and the connection layer 5b, it is possible to easily supply the VDD potential and the GND potential to the circuit constituted by the wiring layer below the fifth wiring layer 5. For example, as shown in FIG. 1, the VDD potential can be supplied to the N-type well region 34 through the wiring layer and the via below using the light shielding layer 5 a. Further, using the connection layer 5b, the GND potential can be supplied to the P-type well region 33 through the underlying wiring layer and via.

  In the first embodiment, the wiring layer that blocks light has a four-layer structure of the eighth wiring layer 8, the seventh wiring layer 7, the sixth wiring layer 6, and the fifth wiring layer 5. It is not limited.

Embodiment 2. FIG.
A semiconductor device 100A according to the second embodiment will be described with reference to FIGS. FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device 100A according to the second embodiment. 6 is a top view of the fourth wiring layer 4 and the third via 23 (VA) of the semiconductor device 100A of FIG. 5, and FIG. 7 is the third wiring layer 3 and the second via 22. It is the figure which looked at (VB) from the upper surface. In the second embodiment, an example in which four wiring layers are formed is shown. 5-7, the same code | symbol is attached | subjected to the component same as the component mentioned above.

  As shown in FIG. 6, the uppermost fourth wiring layer 4 is disposed on substantially the entire surface of the semiconductor device 100A. Due to the wiring density, the fourth wiring layer 4 is penetrated in some places. That is, a plurality of openings are formed in the fourth wiring layer 4. In the example shown in FIG. 6, it is formed so as to be arranged in a matrix with four openings in the horizontal direction and four openings in the vertical direction. The fourth wiring layer 4 has the same potential throughout the semiconductor device 100A. The third via 23 is disposed along the longitudinal direction of the opening provided in the fourth wiring layer 4.

  As shown in FIG. 7, the third wiring layer 3 is also disposed on substantially the entire surface of the semiconductor device 100A. The third wiring layer 3 is also penetrated in some places, and a plurality of openings are formed. The third wiring layer 3 is formed in the portion where the opening of the fourth wiring layer 4 is formed, and the light from the opening of the fourth wiring layer 4 is shielded. A connection layer 3 b formed in the same process as the third wiring layer 3 is formed in the opening of the third wiring layer 3. The connection layer 3b is connected to the fourth wiring layer 4 through the second via 22 formed on the connection layer 3b. In such an example, as in the first embodiment, it is possible to suppress malfunction of the signal processing circuit and to stabilize the GND potential and the VDD potential.

Embodiment 3 FIG.
A semiconductor device according to the third embodiment will be described with reference to FIGS. FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. 9 is a top view of the fourth wiring layer 4 and the third via 23 (XA) of the semiconductor device of FIG. 8, and FIG. 10 shows the third wiring layer 3 and the second via 22 ( It is the figure which looked at XB) from the upper surface. Embodiment 3 shows an example in which four wiring layers are formed.

  The third embodiment is different from the second embodiment in that a connection layer 4 b is provided in the opening of the uppermost fourth wiring layer 4. Other configurations are the same as those of the third embodiment. The connection layer 4b is connected to the third wiring layer 3 through a third via 23 provided under the connection layer 4b. Referring to FIGS. 9 and 10, the fourth wiring layer 4 and the third wiring layer 3 have a structure in which the positions where the openings are formed are inverted. That is, the position where the opening of the fourth wiring layer 4 is formed is blocked by the third wiring layer 3.

  Thus, by dividing the fourth wiring layer 4 and providing the connection layer 4b, for example, when the VDD potential is supplied to the fourth wiring layer 4 and the GND wiring is supplied to the third wiring layer 3, the implementation is performed. The parasitic capacitance value between VDD and GND can be made larger than in the second mode.

  As described above, according to the semiconductor device according to the embodiment, by alternately arranging the GND potential wiring layer and the power supply potential wiring, the power supply wiring connected to the internal signal processing circuit and the wiring of the GND wiring are arranged. The impedance difference can be made uniform, the signal processing circuit can be operated stably, and malfunction can be prevented.

  Further, by alternately arranging the GND potential wiring layer and the power supply potential wiring, the parasitic capacitance between the VDD potential wiring layer and the GND potential wiring layer can be increased between the power supply GND via an insulating film. As a result, voltage drop can be suppressed, and fluctuations in the GND potential and the VDD potential can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 1st wiring layer 2 2nd wiring layer 3 3rd wiring layer 3b Connection layer 4 4th wiring layer 4b Connection layer 5 5th wiring layer 5a Light shielding layer 5b Connection layer 6 6th wiring layer 6a Light shielding layer 6b Connection layer 7 7th 7 wiring layer 7a light shielding layer 7b connecting layer 8 eighth wiring layer 10 substrate 11 first interlayer insulating layer 12 second interlayer insulating layer 13 third interlayer insulating layer 14 fourth interlayer insulating layer 15 fifth interlayer insulating layer 16 sixth interlayer Insulating layer 17 7th interlayer insulating layer 18 Cover insulating layer 21 1st via 22 2nd via 23 3rd via 24 4th via 25 5th via 26 6th via 27 7th via 30 Transistor formation region 31 Impurity region 32 Gate electrode 33 P-type well region 34 N-type well region 100 Semiconductor device

Claims (14)

A semiconductor layer having a light-shielded region;
A first wiring layer having a first slit provided above the semiconductor layer;
A second wiring layer having a second slit provided below the first wiring layer so as to cover the first slit;
A third wiring layer having a third slit provided below the second wiring layer so as to cover the second slit;
A first via that connects the first wiring layer and the third wiring layer;
A semiconductor device in which a potential of the first wiring layer and the third wiring layer is different from a potential of the second wiring layer. A first connection layer provided in the second slit and formed in the same step as the second wiring layer;
The semiconductor device according to claim 1, wherein the first wiring layer and the third wiring layer are connected through the first via and the first connection layer. The second wiring layer is formed with a size that blocks light incident from the first slit,
The semiconductor device according to claim 1, wherein the third wiring layer is formed with a size that blocks light incident from the second slit. The first wiring layer and the third wiring layer are connected to a power supply potential or a ground potential,
The semiconductor device according to claim 1, wherein the second wiring layer is connected to a power supply potential or a ground potential different from that of the first wiring layer and the third wiring layer. A fourth wiring layer having a fourth slit provided below the third wiring layer so as to cover the third slit;
A second via connecting the second wiring layer and the fourth wiring layer;
The semiconductor device according to claim 1, further comprising: A second connection layer formed in the third slit and formed in the same step as the third wiring layer;
The semiconductor device according to claim 5, wherein the second wiring layer and the fourth wiring layer are connected via the second via and the second connection layer. A third connection layer formed in the fourth slit and formed in the same step as the fourth wiring layer;
The semiconductor device according to claim 5, wherein the third connection layer is connected to the third wiring layer. Forming a first wiring layer having a first slit above the semiconductor layer having the light-shielded region;
Forming a second wiring layer having a second slit provided below the first wiring layer so as to cover the first slit;
Forming a third wiring layer having a third slit provided below the second wiring layer so as to cover the second slit;
Connecting the first wiring layer and the third wiring layer with a first via;
A method of manufacturing a semiconductor device, wherein the first wiring layer and the third wiring layer are connected to a first potential, and the second wiring layer is connected to a second potential different from the first potential. In the second slit, further forming a first connection layer in the same process as the second wiring layer,
The method of manufacturing a semiconductor device according to claim 8, wherein the first wiring layer and the third wiring layer are connected through the first via and the first connection layer. The second wiring layer is formed with a size that blocks light incident from the first slit,
The method of manufacturing a semiconductor device according to claim 8, wherein the third wiring layer is formed with a size that blocks light incident from the second slit. Connecting the first wiring layer and the third wiring layer to a power supply potential or a ground potential;
The method for manufacturing a semiconductor device according to claim 8, wherein the second wiring layer is connected to a power supply potential or a ground potential different from that of the first wiring layer and the third wiring layer. Forming a fourth wiring layer having a fourth slit below the third wiring layer so as to cover the third slit;
Connecting the second wiring layer and the fourth wiring layer with a second via;
The semiconductor device according to claim 8. In the third slit, a second connection layer is formed in the same process as the third wiring layer,
The method of manufacturing a semiconductor device according to claim 12, wherein the second wiring layer and the fourth wiring layer are connected through the second via and the second connection layer. In the fourth slit, a third connection layer is formed in the same process as the fourth wiring layer,
The method for manufacturing a semiconductor device according to claim 12, wherein the third connection layer is connected to the third wiring layer.

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