JP2013247619A - Current control circuit and pll circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current control circuit that suppresses its output current fluctuation.SOLUTION: The current control circuit includes: a path where a switch PMOS transistor P2, a current source PMOS transistor P1, a current source NMOS transistor N1 and a switch NMOS transistor N2 are connected in series in this order between power supplies; a path where a drain of the switch PMOS transistor P2 is grounded via a drain of a cascode NMOS transistor N4 and a switch NMOS transistor N3 in this order; and a path where a source of the current source NMOS transistor N1 is connected to the power supply VDD via a drain of a cascode PMOS transistor P4 and a switch PMOS transistor P3 in this order. Since the voltage level of a drain voltage of the switch MOS transistors N3 and P3 determining a momentary current amount is limited by the cascode MOS transistors N4 and P4, the momentary current amount flowing to the power supplies can be suppressed.

Description

  The present invention relates to a current control circuit and a PLL circuit using the current control circuit.

Conventionally, as a charge pump circuit constituting a PLL circuit, for example, a charge pump circuit including a current control circuit has been proposed (see, for example, Patent Document 1).
As a charge pump circuit applied to the PLL circuit in this way, for example, a current control circuit 10 as shown in FIG. 4 has been proposed.
The current control circuit 10 shown in FIG. 4 includes a power supply VDD, a switch PMOS transistor P2 that operates as a switching unit, a current source PMOS transistor P1 that operates as a current source, a current source NMOS transistor N1 that also operates as a current source, and a switching unit. The switch NMOS transistor N2 that operates is connected in series in this order, and has a path in which the other end of the switch NMOS transistor N2 is grounded to GND. Further, the drain of the switch PMOS transistor P2 is connected to the drain of the switch NMOS transistor N3 through a path different from that of the current source PMOS transistor P1, and is connected to the GND, and the source of the current source NMOS transistor N1 is connected to the switch NMOS transistor N2. Includes a path connected to the drain of the switch PMOS transistor P3 and connected to the power supply VDD.

FIG. 4 also shows a control circuit PFD (Phase Frequency Detector) that controls each of the switch MOS transistors P2, N2, N3, and P3 constituting the current control circuit 10.
Further, a bias voltage Bias_P is input to the gate of the current source PMOS transistor P1, and a large-capacity stabilization capacitor C1 is connected between the power supply VDD and the gate of the current source PMOS transistor P1. Similarly, a bias voltage Bias_N is input to the gate of the current source NMOS transistor N1, and a large-capacity stabilization capacitor C2 is connected between the gate of the current source NMOS transistor N1 and GND.

A connection point between the current source PMOS transistor P1 and the current source NMOS transistor N1 is connected to the output terminal Tout, and an output current Iout is output therefrom.
An UP signal, which is a control signal for outputting current, is input from the control circuit PFD to the gates of the switch PMOS transistor P2 and the switch NMOS transistor N3, and output to the gates of the switch NMOS transistor N2 and the switch PMOS transistor P3. The DOWN signal, which is a control signal for drawing current from, is input from the control circuit PFD.

In the control circuit PFD, the output current Iout is controlled by controlling the UP signal to the switch PMOS transistor P2 and the switch NMOS transistor N3 and the DOWN signal to the switch NMOS transistor N2 and the switch PMOS transistor P3. Yes.
FIG. 5 shows a configuration of a high-frequency PLL (Phase-locked loop) circuit to which the current control circuit 10 of FIG. 4 is applied as a charge pump.

  As shown in FIG. 5, the PLL circuit 20 includes a crystal oscillator (XO) 1, an R frequency divider 2, a phase comparator (PFD: Phase Frequency Detector) 3, and a charge pump (CP: Charge Pump) 4. , An LPF (Loop Filter) 5, a voltage controlled oscillator (VCO) 6, and an N divider 7, and the output of the voltage controlled oscillator 6 is output as the output voltage Vout. Yes.

The R frequency divider 2 is a frequency divider for setting the oscillation frequency of the reference input signal (XO signal) generated by the crystal oscillator 1 as a reference frequency and reducing the reference input frequency to 1 / R. Similarly, the N frequency divider 7 is a frequency divider for reducing the frequency of the output signal Vout of the voltage controlled oscillator 6 to 1 / N.
The phase comparator 3 has two signals: an input reference signal obtained by dividing the reference frequency of the reference input signal by R, and an output signal of the N divider 7 obtained by dividing the frequency of the output signal Vout of the voltage controlled oscillator 6 by N. And a control signal (UP signal, DOWN signal) is output to the charge pump 4 according to the difference.

The charge pump 4 controls the output current Iout by outputting a current or drawing a current based on a control signal from the phase comparator 3.
The LPF 5 converts the output current Iout output from the charge pump 4 into a DC voltage (VCO control voltage).
The voltage controlled oscillator 6 generates a signal having a frequency proportional to the VCO control voltage converted by the LPF 5, supplies it to the output terminal 8 as an output signal Vout, and outputs it to the N divider 7.

  The UP signal from the phase comparator 3 is input to the switch PMOS transistor P2 and the switch NMOS transistor N3 of the current control circuit 10, and the DOWN signal from the phase comparator 3 is input to the switch NMOS transistor N2 and the switch PMOS transistor P3. The output current Iout of the current control circuit 10 is controlled according to the UP signal and the DOWN signal.

  That is, when the gain of the voltage controlled oscillator 6 is positive, when the phase of the output signal of the N frequency divider 7 as a comparison object is advanced with respect to the input reference signal from the R frequency divider 2, The phase comparator 3 outputs a DOWN signal to the charge pump 4. In response to the DOWN signal, the charge pump 4 draws a current from the LPF 5, lowers the VCO control voltage, and corrects so that the phase of the output signal Vout of the voltage controlled oscillator 6 is delayed.

Conversely, when the phase of the input reference signal is advanced with respect to the output signal of the N frequency divider 7, the UP signal is output to the charge pump 4. The charge pump 4 outputs the output current Iout according to the UP signal, raises the VCO control voltage, and corrects the phase of the output signal Vout of the voltage controlled oscillator 6 to advance.
Further, when the gain of the voltage controlled oscillator 6 is negative, the operation is the reverse of the above.

  As described above, when the PLL circuit 20 shown in FIG. 5 is configured using the current control circuit 10 shown in FIG. 4, the UP signal from the phase comparator 3 is applied to the gates of the switch PMOS transistor P2 and the switch NMOS transistor N3. The DOWN signal from the phase comparator 3 is input to the gates of the switch NMOS transistor N2 and the switch PMOS transistor P3.

  When the DOWN signal is at a low level and a low level UP signal is input, the switch NMOS transistor N3 is turned off and the switch PMOS transistor P2 is turned on by the falling edge of the UP signal, and the drain voltage of the switch PMOS transistor P2 is instantaneously changed. Charging up to near the power supply VDD voltage, the current source PMOS transistor P1 is switched on.

On the other hand, when the UP signal is at a high level and a high level DOWN signal is input, the rising edge of the DOWN signal turns off the switch PMOS transistor P3 and the switch NMOS transistor N2 to turn on the drain voltage of the switch NMOS transistor N2. Is instantaneously discharged from the power supply VDD voltage to GND.
When the UP signal is low and the DOWN signal is high and both current source MOS transistors P1 and N1 are on, the current source MOS transistors P1 and N1 designed to have the same current value are In balance, the output current Iout is not output.

As described above, the current control circuit 10 shown in FIG. 4 is a circuit having three states as the output current Iout. Therefore, the current control circuit 10 can also operate as the charge pump 4 of the PLL circuit 20.
Further, the switch NMOS transistor N3 of the current control circuit 10 in FIG. 4 detects the falling edge of the UP signal and is turned on from off, and the source of the current source PMOS transistor P1 is driven with a current driving force higher than that of the current source PMOS transistor P1. Immediately discharges the charge accumulated in the capacitor GND to turn off the UP-side current source PMOS transistor P1. Similarly, the switch PMOS transistor P3 detects the falling edge of the DOWN signal, switches from OFF to ON, and immediately charges the source of the current source NMOS transistor N1 with a current driving force higher than that of the current source NMOS transistor N1. Then, the current source NMOS transistor N2 on the DOWN side is turned off. As described above, the switch MOS transistors N3 and P3 play a role of making the trailing edge of the output current Iout more steep so as to suppress an excessive output current and approach an ideal output current pulse.

Japanese Patent Laid-Open No. 2007-11641

  When the PLL circuit 20 as shown in FIG. 5 is integrated, in the charge pump 4, the power supply voltage VDD line and the GND line are laid out as shown in FIG. 4 as inductance components L, vdd, L, and gnd. In addition, an inductance component is added by the wiring accompanying, and when a potential is directly applied via the electrode PAD, a larger inductance component is added by combining the wiring and a bonding wire.

As described above, the switch MOS transistors N3 and P3 cause a current more than the amount of current that can be passed by the current source MOS transistor to steeply fall due to the steep fall of the output current Iout. The power supply voltages VDD and GND are ringed by an amount corresponding to the product of the value and the inductance component value (L, vdd, L, gnd).
That is, the current control circuit 10 shown in FIG. 4 has large-capacity stabilization capacitors C1 and C2 connected to the gates of the UP-side and DOWN-side current source PMOS transistor P1 and current source NMOS transistor N1, respectively. Therefore, the displacement of the power supply voltage VDD or the GND voltage is transmitted to the gates of the current source MOS transistors P1 and N1 with a gain of 1, and the gate potentials of the current source MOS transistors P1 and N1 ring. As a result, the output current Iout will ring.

  Note that the amount of charge discharged and charged by the switch MOS transistors N3 and P3 described above includes the power supply voltage VDD, the intrinsic components of the MOS transistors added to the source side of the current source MOS transistors P1 and N1, and the wiring components due to the layout. Therefore, the higher the power supply voltage is used, the more the influence of ringing appears. Further, since the size of the current source MOS transistor increases as the output current amount increases, the intrinsic capacitance increases, and this also causes the influence of ringing to be more prominent.

  The output current ringing generated at the timing when the current source MOS transistor shifts from on to off is such that the charge pump 4 has an integral amount of output current as the phase difference compared by the PLL circuit 20 approaching the phase LOCK is closer. Since it is small, the influence of the output current fluctuation due to ringing appears to be relatively large, and the gain (time average value of the output current) Kcp of the charge pump 4 appears to fluctuate.

Thus, when the output current Iout of the current control circuit 10 rings, the accuracy of the output current Iout deteriorates. As a result, the current as designed does not output from the charge pump 4, resulting in inconvenience in system design.
For example, when the current control circuit 10 is used as the charge pump 4 of the PLL circuit 20, the gain (time average value of the output current) Kcp of the charge pump 4 varies and is proportional to the gain Kcp. The loop bandwidth ωc of the PLL circuit 20 changes. If the loop bandwidth fluctuates, there is a problem that the phase margin, which is a measure of system stability, also fluctuates.

  As an example, a PLL circuit 20 including a voltage-controlled oscillator 6 generates a LO signal (local oscillation signal) when an RF signal is converted into an IF signal by a MIXER in a reception RF reception system 30 as shown in FIG. When used as a local oscillator, the gain of the detuning frequency of the LO signal that is the output signal of the PLL 20 circuit (that is, the voltage controlled oscillator (VCO) 6) will fluctuate.

  FIG. 7 shows a spectrum diagram of the RF receiving system 30, where (a) is a frequency spectrum of an RF signal (desired wave: frequency fRF) and an interfering wave (frequency f1), and (b) is an LO signal (frequency). (fLO) shows the frequency spectrum, and (c) shows the IF signal (desired wave: frequency fIF = fRF−fLO) and the frequency spectrum of the jamming wave (frequency f1−fLO), respectively.

As shown in FIG. 7, the phase noise (phase noise) of the LO signal remains at the same ratio even after the frequency conversion, so that the interference wave adjacent to the RF signal is a large signal as shown in FIG. In this case, if the band of the interference wave (width of ωc) fluctuates and widens, the desired wave may be buried in the interference wave (see FIG. 7C).
Further, even if the current is reduced and the band is narrowed, the problem that the noise of the PLL circuit 20 increases and the problem that the lock-up time of the PLL circuit 20 becomes longer than the design value also occur.

That is, since the accuracy of the output current Iout of the current control circuit 10 plays an important role in system design, it is desirable to reduce fluctuations in the output current Iout of the current control circuit 10.
Therefore, the present invention has been made paying attention to the above-mentioned conventional unsolved problems, and is a current capable of reducing the ringing of the output current caused by the on / off operation of the MOS transistor constituting the current control circuit. The object is to provide a control circuit.

  In order to achieve the above object, a current control circuit according to claim 1 of the present invention includes a first transistor, a first current source, a first current source connected in series between a first power source and a second power source, Two current sources and a second transistor that operates complementarily to the first transistor, and is connected between a connection point of the first transistor and the first current source and the second power source, and A third transistor that operates complementarily to the first transistor, and is connected between the second current source and a connection point of the second transistor and the first power supply, and operates complementary to the second transistor. A current control circuit that controls a current output from an intermediate connection point of the first current source and the second current source by on / off control of each of the transistors, A first current control unit for controlling a current of the third transistor is inserted in a path to which the third transistor is connected between a connection point of the transistor and the first current source and the second power source; and A second current control unit for controlling the current of the fourth transistor is inserted in a path where the fourth transistor is connected between the connection point of the second transistor and the second current source and the first power source. It is characterized by that.

The current control circuit according to claim 2, wherein the first current control unit is interposed between the first transistor and the third transistor, and the second current control unit includes the second transistor and the second transistor. It is characterized by being interposed between four transistors.
The current control circuit according to claim 3 is characterized in that each of the first current control unit and the second current control unit is a transistor.

The current control circuit according to a fourth aspect is characterized in that each of the first current control unit and the second current control unit is a resistor.
The current control circuit according to claim 5, wherein the first current control unit is interposed between the third transistor and the second power source, and the second current control unit includes the fourth transistor and the second power source. It is characterized by being inserted between one power source.

The current control circuit according to a sixth aspect is characterized in that each of the first current control unit and the second current control unit is a resistor.
A PLL circuit according to a seventh aspect of the present invention includes a charge pump circuit including the current control circuit according to any one of the first to sixth aspects.
Furthermore, an RF reception system according to an eighth aspect of the present invention is characterized by including the PLL circuit according to the seventh aspect, and a mixer that mixes an RF signal and a local signal from the PLL circuit.

According to the present invention, since the instantaneous current amount can be reduced, ringing of the output current of the current control circuit can be suppressed. Therefore, when this current control circuit is used as a charge pump for a PLL circuit, the charge pump outputs an ideal current, and as a result, fluctuations in the loop bandwidth of the PLL circuit can be suppressed.
In addition, by configuring an RF reception system using a PLL circuit using such a current control circuit as a charge pump, it is possible to suppress a desired wave from being buried in an interference wave and realize a good RF reception system. be able to.

It is a block diagram which shows an example of the current control circuit in 1st Embodiment of this invention. It is a block diagram which shows an example of the current control circuit in 2nd Embodiment of this invention. It is a block diagram which shows an example of the current control circuit in 3rd Embodiment of this invention. It is a block diagram which shows an example of the conventional current control circuit. It is a system block diagram which shows an example of a high frequency PLL circuit. It is a block diagram which shows an example of RF receiving system. FIG. 7 is an example of a spectrum diagram in the RF reception system of FIG. 6.

Hereinafter, an example of the current control circuit of the present invention will be described with reference to the drawings.
In the current control circuit according to the present invention, the fluctuation of the output current of the current control circuit is reduced by reducing the instantaneous current flowing through the inductor.
First, the first embodiment will be described.
FIG. 1 shows an example of the current control circuit 11 according to the first embodiment.

The current control circuit 11 in the first embodiment further includes a cascode NMOS transistor N4 and a cascode NMOS transistor P4 in the conventional current control circuit 10 shown in FIG.
That is, as shown in FIG. 1, the current control circuit 11 in the first embodiment includes a power supply VDD, a switch PMOS transistor P2 that operates as switch means, a current source PMOS transistor P1 that operates as a current source, and a current source. A current source NMOS transistor N1 that operates as a switch and a switch NMOS transistor N2 that operates as a switch means are connected in series in this order, and the other end of the switch NMOS transistor N2 has a path grounded to GND. Further, the drain of the switch PMOS transistor P2 is connected to the drain of the cascode NMOS transistor N4 connected in cascode through a path different from that of the current source PMOS transistor P1, and is then grounded to GND in the order of the switch NMOS transistor N3 operating as a switch means. And the source of the current source NMOS transistor N1 are connected to the drain of a cascode-connected cascode PMOS transistor P4 through a path different from that of the switch NMOS transistor N2, and further operate as a switching means via the cascode PMOS transistor P4. And a path connected to the drain of the switch NMOS transistor N3 and connected to the power supply VDD.

  Further, a bias voltage Bias_P is input to the gate of the current source PMOS transistor P1, and a relatively large stabilization capacitor C1 is connected between the power supply VDD and the gate of the current source PMOS transistor P1. Similarly, a bias voltage Bias_N is input to the gate of the current source NMOS transistor N1, and a relatively large capacitor C2 is connected between the gate of the current source switch NMOS transistor N1 and GND.

A control signal (UP signal) from the control circuit PFD (phase comparator) is input to the gate of the switch PMOS transistor P2 and the gate of the switch NMOS transistor N3, and the gates of the switch PMOS transistor P3 and the switch NMOS transistor N2 are A control signal (DOWN signal) from the control circuit PFD (phase comparator) is input.
The power supply VDD voltage is applied to the gate of the cascode NMOS transistor N4, and the GND voltage is applied to the gate of the cascode PMOS transistor P4.

In the case of the current control circuit 11 having such a configuration, the switch PMOS transistor P2 is turned off and the switch NMOS transistors N3 and N4 are turned on by the rising signal of the UP signal from the control circuit PFD.
At this time, the voltage level of the drain voltage of the switch NMOS transistor N3 that determines the instantaneous current amount is limited by the cascode NMOS transistor N4. Therefore, the instantaneous current value is suppressed.

  Similarly, the switch NMOS transistor N2 is turned off and the switch PMOS transistors P3 and P4 are turned on by the rising signal of the DOWN signal from the control circuit PFD (phase comparator). At this time, the voltage level of the drain voltage of the switch PMOS transistor P3 that determines the instantaneous current amount is limited by the cascode PMOS transistor P4. Therefore, the instantaneous current value can be suppressed.

  Further, in the first embodiment, not only the instantaneous current can be suppressed, but also the current source PMOS is controlled by controlling the gate of the switch NMOS transistor N3 by inserting the cascode NMOS transistor N4 and the cascode PMOS transistor P4. By controlling the UP signal supplied to the source node of the transistor P1 and the gate of the switch PMOS transistor P3, the influence of clock feedthrough of the DOWN signal supplied to the source node of the current source NMOS transistor N1 can be reduced. There are advantages.

  Further, by inserting a cascode NMOS transistor N4 having a smaller transistor size than the switch NMOS transistor N3 and a cascode PMOS transistor P4 having a smaller size than the switch PMOS transistor P3, a current source PMOS transistor P1 and a current source NMOS transistor N1 are further provided. The source ground capacitance of the source node can be reduced. For this reason, the charge of the source node of the current source PMOS transistor P1 and the current source NMOS transistor N1 is reduced, and the discharge charge is reduced, which is also an advantage that leads to a reduction in instantaneous current.

  Here, in the first embodiment, the power supply VDD corresponds to the first power supply, the GND corresponds to the second power supply, the switch PMOS transistor P2 corresponds to the first transistor, and the current source PMOS transistor P1 corresponds to the first current. The source NMOS transistor N1 corresponds to the second current source, the channel NMOS transistor N2 corresponds to the second transistor, the switch NMOS transistor N3 corresponds to the third transistor, and the switch PMOS transistor P3 corresponds to the fourth transistor. It corresponds to a transistor. Further, the cascode NMOS transistor N4 corresponds to the first current control unit, and the cascode PMOS transistor P4 corresponds to the second current control unit.

Next, a second embodiment of the present invention will be described.
FIG. 2 is a circuit diagram showing an example of the current control circuit 12 in the second embodiment.
In the second embodiment, a resistor Rup and a resistor Rdw are inserted in place of the current source NMOS transistor N4 and the current source PMOS transistor P4 in FIG. 1 in the first embodiment. The resistor Rup corresponds to the first current control unit, and the resistor Rdw corresponds to the second current control unit.

In this way, by inserting the resistor Rup between the drain of the switch NMOS transistor N3 and the drain of the current source PMOS transistor P2, the drain voltage of the switch NMOS transistor N3 that determines the instantaneous current amount has a voltage level caused by the resistor Rup. It is suppressed. Therefore, the instantaneous current value can be suppressed.
Similarly, by inserting a resistor Rdw between the drain of the switch PMOS transistor P3 and the drain of the current source NMOS transistor N2, the drain voltage of the switch PMOS transistor P3 that determines the instantaneous current amount has a voltage level caused by the resistor Rdw. It is suppressed. Therefore, the instantaneous current value can be suppressed.

Next, a third embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing an example of the current control circuit 13 in the third embodiment.
In the third embodiment, in the conventional current control circuit 10 shown in FIG. 4, a resistor R1 is inserted between the source of the switch NMOS transistor N3 and GND, and the source of the switch PMOS transistor P3 and the power supply VDD are connected. A resistor R2 is inserted between them. The resistor R1 corresponds to the first current control unit, and the resistor R2 corresponds to the second current control unit.

  Thus, the resistors R1 and R2 are inserted into the source side of the switch NMOS transistor N3 and the source side of the switch PMOS transistor P3, respectively, and the current flowing through the switch NMOS transistor N3 and the switch PMOS transistor P3 due to the negative feedback effect is obtained. The ringing of the output current of the current control circuit 13 can also be suppressed by suppressing it and increasing the attenuation constant.

  As described above, since the current control circuits 11 to 13 in each of the above embodiments can suppress the instantaneous current value, the inductance component (as shown in FIG. 1 to FIG. 3 in the power supply voltage VDD line and the GND line). Even if (L, vdd, L, gnd) is added, ringing of the output current caused by this inductance component can be suppressed. That is, even when the current control circuits 11 to 13 are applied as a charge pump, the charge pump outputs an ideal current. Therefore, when the current control circuits 11 to 13 are applied as charge pumps constituting the PLL circuit, the charge pump outputs an ideal current, so that the loop bandwidth fluctuation of the PLL circuit can be suppressed, That is, an accurate PLL circuit can be realized.

  Further, since the ringing of the output current can be suppressed, when the current control circuits 11 to 13 are applied as the charge pump of the fractional PLL synthesizer, the linearity of the gain of the output current of the charge pump with respect to the phase difference to be compared. Therefore, ΔΣ noise shaping is also improved, and a reference spurious reduction effect of the comparison frequency period can be expected.

  In addition, since the performance of the PLL circuit can be improved in this way, the PLL circuit to which the current control circuit shown in FIG. 1 is applied as a charge pump is used in the RF receiving system of the receiving system as shown in FIG. By using it, it is possible to suppress a desired wave from being buried in an interference wave adjacent to the RF signal, and to realize a good RF receiving system.

10-13 Current control circuit P1 Current source PMOS transistor P2 Switch PMOS transistor P3 Switch PMOS transistor P4 Cascode PMOS transistor N1 Current source NMOS transistor N2 Switch NMOS transistor N3 Switch NMOS transistor N4 Cascode NMOS transistors R1, R2 Resistance Rup, Rdw Resistance

Claims (8)

A first transistor, a first current source, a second current source, and a second transistor operating in a complementary manner with the first transistor, which are connected in series between a first power source and a second power source; As well as
A third transistor connected between a connection point of the first transistor and the first current source and the second power supply and operating in a complementary manner with the first transistor;
A fourth transistor connected between a connection point of the second current source and the second transistor and the first power supply, and operating complementarily with the second transistor;
A current control circuit for controlling a current output from an intermediate connection point of the first current source and the second current source by on / off control of each transistor;
A first current control unit for controlling the current of the third transistor is inserted in a path where the third transistor is connected between the connection point of the first transistor and the first current source and the second power source. And a second current control unit for controlling the current of the fourth transistor in a path where the fourth transistor is connected between the connection point of the second transistor and the second current source and the first power source. A current control circuit characterized by being inserted. The first current control unit is interposed between the first transistor and the third transistor,
The current control circuit according to claim 1, wherein the second current control unit is interposed between the second transistor and the fourth transistor.   3. The current control circuit according to claim 2, wherein each of the first current control unit and the second current control unit is a transistor.   The current control circuit according to claim 2, wherein the first current control unit and the second current control unit are resistors. The first current control unit is interposed between the third transistor and the second power source,
The current control circuit according to claim 1, wherein the second current control unit is interposed between the fourth transistor and the first power source.   6. The current control circuit according to claim 5, wherein each of the first current control unit and the second current control unit is a resistor.   A PLL circuit comprising: a charge pump circuit including the current control circuit according to claim 1. A PLL circuit according to claim 7;
A mixer that mixes the RF signal with the local signal from the PLL circuit;
An RF receiving system comprising:

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