JP2013247245A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device which can mount a lot of semiconductor chips with high density at low cost.SOLUTION: A semiconductor device of a present embodiment comprises: a semiconductor chip 14a on which a rectangular connection pad 13a is formed on a chip surface; and a semiconductor chip 14b on which a rectangular connection pad 13b is formed on a chip surface. Long sides of the connection pad 13a are formed along a first direction at least in the semiconductor chip 14a. The connection pad 13a and the connection pad 13b are bonded to be opposite to each other and the semiconductor chip 14b is bonded so as to be shifted from the semiconductor chip 14a in the first direction so as to expose at least a part of the connection pad 13a. The connection pad 13a and the connection pad 13b are electrically connected so as to compose a semiconductor chip pair 16 by the first and second semiconductor chips 14a, 14b.

Description

  Embodiments described herein relate generally to a semiconductor device configured by stacking a plurality of thinly ground semiconductor chips.

  In a semiconductor device (module package) configured by stacking a plurality of semiconductor chips, (a) a plurality of semiconductor chips are mounted on a module wiring board having external connection terminals such as BGA (Ball Grid Array) balls formed on the back surface. A type in which the connection terminals (connection pads) of the semiconductor chip and the module wiring board are connected by bonding wires, and (b) BGA balls are formed on the back surface of a plurality of wiring boards on which the semiconductor chips are bump-connected. A type in which the semiconductor chips are stacked on the module wiring board, and the semiconductor chips are electrically connected by connection wiring (via plugs) embedded in vias formed on the peripheral edge of the wiring board. (C) The semiconductor chip and the wiring pattern are integrated. A type in which a plurality of units each including a covering mold resin and a via plug that penetrates the mold resin outside the semiconductor chip are stacked. A.

  However, in the conventional semiconductor device (module package), for example, in the type (a), when semiconductor chips of the same size are stacked like a memory module, a plurality of semiconductor chips are connected by bonding wires. It is necessary to stack the chips by shifting the chips, and there is a problem that the external dimensions of the large-capacity memory module in which many semiconductor chips are stacked are larger than the size of the semiconductor chip. In addition, as the number of chips to be stacked increases, the total shift amount increases, so the number of chips that can be stacked is limited due to the mechanical strength limitation of the packaging process, that is, the capacity of the memory module is limited. There was a problem. Further, for example, the types (b) and (c) have a problem that the module package becomes thick because a wiring board or wiring pattern is formed for each layer of the semiconductor chip. In addition, since it is necessary to form vias in the wiring board or mold resin and to form connection wirings (via plugs) therein, there is a problem that the manufacturing process is very complicated and the manufacturing cost is expensive.

JP-A-9-186289 Special table 2009-540606

  The present invention provides a semiconductor device capable of mounting a large number of semiconductor chips at a low cost at a high density.

  According to an aspect of the embodiment of the present invention, the semiconductor device includes first and second semiconductor chips each having a substantially rectangular connection pad formed on each first main surface, and at least in the first semiconductor chip, the first semiconductor chip includes the first and second semiconductor chips. The long sides of the connection pads are formed along a first direction, and the first and the second pads are arranged so that the connection pads of the first semiconductor chip and the connection pads of the second semiconductor chip face each other. The second semiconductor chip is bonded to the first main surfaces of the second semiconductor chip, and at least a part of the connection pads of the first semiconductor chip is exposed. The first semiconductor chip is bonded to the semiconductor chip while being displaced in the first direction, and the connection pad of the first semiconductor chip and the connection pad of the second semiconductor chip are electrically connected, and the first and Wherein a constituting the semiconductor chip pairs by two of the semiconductor chip is provided.

1 is an image diagram showing a structure of a semiconductor device according to Embodiment 1 of the present invention. FIG. 3 is an image diagram showing an arrangement of connection pads in the semiconductor chip of the semiconductor device according to the first embodiment of the invention. FIG. 6 is an image diagram showing a cross-sectional structure of a semiconductor device according to Example 2 of the invention. FIG. 6 is an image diagram showing a cross-sectional structure in another configuration example of a semiconductor device according to Example 2 of the invention. FIG. 6 is an image diagram showing a cross-sectional structure in still another configuration example of a semiconductor device according to Example 2 of the invention. FIG. 6 is an image diagram showing a cross-sectional structure in still another configuration example of a semiconductor device according to Example 2 of the invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an image diagram showing a structure of a semiconductor device according to Embodiment 1 of the present invention. Here, as an example, a case where two semiconductor chips having substantially the same size and substantially the same function, for example, memory chips, are stacked to form a large capacity module package is shown. FIG. 1A shows a cross-sectional structure of the module package, and FIG. 1B is a plan view of the positional relationship between the two semiconductor chips 14a and 14b as viewed from above the module package (in FIG. 1A, from the top of the drawing). As shown. Moreover, the dashed-dotted line AB of FIG.1 (b) has shown the position of the cross section shown to Fig.1 (a). Furthermore, in order to avoid the complexity of the drawing and clarify the positional relationship between the main components, the cross section of the sealing resin 19 is not hatched in FIG.

  The semiconductor device according to the first embodiment of the present invention includes a module wiring board 12 having an external connection terminal 11, a semiconductor chip 14a having a connection pad 13a, a semiconductor chip 14b having a connection pad 13b, a connection bump 15, and a semiconductor chip pair. 16, a bonding wire 18, and a sealing resin 19 formed so as to cover the semiconductor chip pair 16 and the bonding wire 18.

  The semiconductor chip pair 16 is bonded to one main surface of the module wiring board 12 (hereinafter referred to as “the surface of the module wiring board 12”), and the other main surface (hereinafter referred to as “the back surface of the module wiring board 12”). A BGA ball, which is the external connection terminal 11, is formed, and the semiconductor chip pair 16 and the external connection terminal 11 are electrically connected via a bonding wire 18. Further, the surface of the module wiring board 12, the semiconductor chip pair 16, and the bonding wire 18 are covered with a sealing resin 19 and are electrically and mechanically protected.

  The module wiring board 12 is provided with connection lands (not shown) for connecting the bonding wires 18 on the surface thereof. The connection lands are via plugs and module wirings embedded in vias penetrating the module wiring board 12. The external connection terminal 11 (BGA ball) is electrically connected by connection wiring formed on the front surface / back surface of the substrate 12.

  The connection pad 13a is formed on the chip surface (element formation surface) of the semiconductor chip 14a, and as shown in FIG. 1B, one side (hereinafter referred to as “reference side 20a” on the chip peripheral portion of the semiconductor chip 14a. Are arranged along the line.

  The connection pad 13a has a rectangular shape (for example, a width of 40 μm and a length of 100 μm), and its long side is formed along a direction orthogonal to the reference side 20a, and is closer to the reference side 20a (in FIG. 1). A bonding wire 18 is connected to the left side of the paper surface), and a connection bump 15 is connected to the other (right side of the paper surface in FIG. 1).

  Similarly, the connection pads 13b are formed on the chip surface (element formation surface) of the semiconductor chip 14b, and a plurality of connection pads 13b are arranged along the reference side 20b on the chip peripheral portion of the semiconductor chip 14b, and the long side thereof is the reference side 20b. The connection bumps 15 are connected to the side that is close to the reference side 20b (the left side in FIG. 1).

  For example, solder bumps are used as the connection bumps 15. After the semiconductor chips 14a and 14b are bonded, the connection bumps 15 are melted by heating or pressurization, and the connection pads 13a and the connection pads 14b are electrically connected. .

  The semiconductor chip pair 16 is configured by bonding the semiconductor chip 14a and the semiconductor chip 14b so that the front surfaces of the chips face each other with the insulating adhesive 17 interposed therebetween, and the chip back surface of the semiconductor chip 14a is attached to the surface of the module wiring board 12. It is mounted to adhere. Further, as shown in FIG. 1B, the semiconductor chip 14a and the semiconductor chip 14b are bonded so that the reference sides 20a and 20b are parallel, and the semiconductor chip 14b is at least one of the connection pads 13a of the semiconductor chip 14a. The portion (left side in FIG. 1 in FIG. 1) is bonded to the semiconductor chip 14a so as to be shifted by d in the direction perpendicular to the reference side 20a. As a result, the connection pad 13a of the semiconductor chip 14a and the connection pad 13b of the semiconductor chip 14b are bonded to face each other and are electrically connected by the connection bumps 15.

  Thus, since the connection bump 15 is used for electrical connection to the connection pad 13b of the second stage (semiconductor chip 14b) and no bonding wire is used, the thickness of the module package can be reduced. That is, in the connection using the bonding wire, the top position of the bonding wire needs to be set considerably higher than the upper surface of the semiconductor chip in order to obtain a sufficient manufacturing margin in the bonding process. In a normal case where the semiconductor chip 14b is connected by a bonding wire, the sealing resin 19 that electrically and mechanically protects the top position must be formed thicker. Conversely, the thickness of the sealing resin 19 can be reduced by the amount not connected to the second-stage semiconductor chip 14b by the bonding wire, and as a result, the thickness of the module package can be reduced.

  The size of the connection pads 13a and 13b and the shift amount d of the semiconductor chips 14a and 14b are the connection size and connection accuracy of the bonding wires 18, the size of the connection bumps 15, and the chip ends (reference sides) of the connection pads 13a and 13b. Determined by the distance from. For example, if the connection pads 13a and 13b have a width of 40 μm, a distance from the chip edge of 20 μm, and the connection bump 15 needs to have a size of 40 μm, the length of the connection pads 13a and 13b (pad long side) is The shift amount d between the semiconductor chips 14a and 14b is about 60 μm. Although depending on the combination of the above-described conditions, generally, the length of the connection pads 13a and 13b (pad long side) is at least about twice the size required for bonding (usually the pad width). is there.

  FIG. 2 is an image diagram showing a layout arrangement of connection pads on two semiconductor chips 14a and 14b of the semiconductor device according to the first embodiment of the present invention. Here, in order to simplify the drawing, each of the semiconductor chips 14a and 14b is shown in a plan view as viewed from the chip surface (element formation surface). In addition, the reference sides 20a and 20b are shown so as to be aligned below the paper surface. Furthermore, as an example, the case where six connection pads 13a and 13b (No. 1 pad to No. 6 pad) are formed is shown.

  As shown in FIG. 2, the layout arrangement of the connection pads 13a of the semiconductor chip 14a and the layout arrangement of the connection pads 13b of the semiconductor chip 14b are mutually inverted along the direction of the reference side when viewed from the respective chip surfaces. Are arranged. That is, as for the connection pads 13a of the semiconductor chip 14a, No. 1 pads to No. 6 pads are laid out in order from the left side to the right side of the drawing along the reference side 20a. On the other hand, as for the connection pad 13b of the semiconductor chip 14b, the No. 1 pad to the No. 6 pad are laid out in order from the right side to the left side of the drawing along the reference side 20b.

  Thus, by arranging the connection pads 13a and 13b in the layout, when the semiconductor chip 14a and the semiconductor chip 14b are bonded so that the chip surfaces face each other, the No. 1 pad to the No. 6 pad are connected correspondingly. Will come to be.

  For example, in the case of configuring a memory module, the semiconductor chip 14b having a layout arrangement that is reversed left and right is simply created by reversing the reticle mask used in the exposure process (PEP) during chip manufacture. It is possible to manufacture in exactly the same manufacturing process as the chip 14a. For this reason, it is not necessary to newly develop the semiconductor chip 14b, and the manufacturing cost is hardly affected. The ability to manufacture the semiconductor chip 14b without increasing the manufacturing cost is particularly effective when, for example, a large-capacity memory module is configured by stacking two or more semiconductor chip pairs as described later.

  According to the first embodiment, since a wiring board and a wiring pattern are not used for each of the stacked semiconductor chips 14a and 14b, high-density mounting in a semiconductor device can be realized at low cost.

  Further, according to the first embodiment, since no bonding wire is used for connection to the upper stage (second-stage semiconductor chip 14b), the package thickness of the semiconductor device can be reduced.

  In the first embodiment, the semiconductor chips 14a and 14b have the same size and the same function. However, the present invention is not limited to this, and the size and layout layout of the connection pads 13a and 13b are appropriate. For example, even semiconductor chips having different sizes and different functions can be applied in principle. In that case, the connection pad 13b of the semiconductor chip 14b only needs to have a size that allows connection bumps 15 to be connected.

  In the first embodiment, the semiconductor chip 14b is manufactured using the inverted data of the semiconductor chip 14a. However, the present invention is not limited to this, and the size and layout arrangement of the connection pads 13a and 13b are not limited thereto. If appropriate, it can also be produced in different ways.

  FIG. 3 is an image diagram showing a cross-sectional structure of the semiconductor device according to the second embodiment of the present invention. Here, as an example of mounting three or more semiconductor chips, a case where a module package is configured by two semiconductor chip pairs 16 and 36 having the same size is shown. Further, as in Example 1, the cross section of the sealing resin 19 is not hatched.

  The semiconductor device according to the second embodiment of the present invention includes a module wiring board 12 having an external connection terminal 11, semiconductor chip pairs 16 and 36, bonding wires 18 and 38, and semiconductor chip pairs 16 and 36 and bonding wires 18 and 38. A sealing resin 19 formed so as to cover is provided.

  Except for the semiconductor chip pair 36 and the bonding wire 38, the configuration and structure of each component, and the positional relationship and connection relationship with other components are the same as those in the first embodiment. Use the same sign as. The difference from the first embodiment is that the semiconductor chip pair 36 is stacked on the semiconductor chip pair 16 and is electrically connected to the external connection terminals 11 via bonding wires 38.

  That is, the chip back surface of the semiconductor chip 34 a of the semiconductor chip pair 36 is bonded to the chip back surface of the semiconductor chip 14 b of the semiconductor chip pair 16 to mount the semiconductor chip pair 36, and the connection formed on the semiconductor chip 34 a of the semiconductor chip pair 36. The pad 33a is connected to the connection pad 13a of the semiconductor chip pair 16 by a bonding wire 38. Further, the surface of the module wiring board 12, the semiconductor chip pairs 16 and 36, and the bonding wires 18 and 38 are covered with a sealing resin 19 and are electrically and mechanically protected.

  Similar to the connection pad 13a, the connection pad 33a is formed in a rectangular shape on the chip surface (element formation surface) of the semiconductor chip 34a, and a plurality of connection pads 33a are provided along one side (reference side) on the chip peripheral portion of the semiconductor chip 34a. Are arranged, bonding wires 38 are connected to the side closer to the reference side, and connection bumps 35 are connected to the other side.

  Similarly, the connection pads 33b are formed in a rectangular shape on the chip surface (element formation surface) of the semiconductor chip 34b, and a plurality of connection pads 33b are arranged along the reference side on the chip peripheral portion of the semiconductor chip 34b. Connection bumps 35 are connected.

  Similar to the semiconductor chip pair 16, the semiconductor chip pair 36 is configured by bonding the semiconductor chip 34 a and the semiconductor chip 34 b so that the surfaces of the chips face each other with the insulating adhesive 37 interposed therebetween. The difference from the semiconductor chip pair 16 is that the semiconductor chip pair 36 is bonded to the upper surface of the semiconductor chip pair 16 and that the connection pad 33a is connected to the connection pad 13a by a bonding wire 38.

  That is, as shown in FIG. 3, the semiconductor chip 34a and the semiconductor chip 34b are bonded so that their reference sides are parallel, and the semiconductor chip 34b is a semiconductor in which at least a part of the connection pad 33a of the semiconductor chip 34a is exposed. The chip 34a is bonded by being shifted by d in a direction perpendicular to the reference side. As a result, the connection pad 33a of the semiconductor chip 34a and the connection pad 33b of the semiconductor chip 34b are bonded to face each other, and these are electrically connected by the connection bumps 35. One end of the bonding wire 38 is connected to the exposed portion of the connection pad 34a, and the other end of the bonding wire 38 is connected to the connection pad 13a of the semiconductor chip 14a.

  Similarly to the semiconductor chip pair 16, the layout arrangement of the connection pads 33a of the semiconductor chip 34a and the layout arrangement of the connection pads 33b of the semiconductor chip 34b are mutually along the direction of the reference side when viewed from the respective chip surfaces. Inverted arrangement.

  The semiconductor chip pair 36 is bonded and laminated so that the chip back surface of the semiconductor chip 34a and the chip back surface of the semiconductor chip 14b of the semiconductor chip pair 16 overlap each other. For this reason, when the four semiconductor chips 14a, 14b, 34a, and 34b are stacked, the total chip shift amount may be 2d, and the total chip shift amount is less than the method of forming a module package by connecting only with ordinary bonding wires. And the external dimensions of the module package can be reduced. Compared to the normal method, the total chip shift amount can be reduced by d each time two semiconductor chips are stacked. Therefore, this is particularly effective when, for example, a large-capacity memory module in which many semiconductor chips are stacked is formed. is there.

  According to the second embodiment, not only the same effects as in the first embodiment can be obtained, but also high-density mounting can be realized at a lower cost in a semiconductor device in which more semiconductor chips such as a large-capacity memory module are stacked. be able to.

  Further, according to the second embodiment, since the chip shift amount is d every time two semiconductor chips are stacked, more semiconductor chips can be stacked and the package external dimensions of the semiconductor device can be kept small. it can.

  In the second embodiment, the stacked semiconductor chips have the same size and the same function. However, the present invention is not limited to this, and the size of the connection pads 13a to 33b is the same as the first embodiment. If the layout arrangement is appropriate, even semiconductor chips having different sizes and different functions can be applied in principle.

  In the second embodiment, the number of stacked semiconductor chips is four. However, the present invention is not limited to this, and is theoretically applicable when three or more semiconductor chips are stacked. Is applicable. For example, when three semiconductor chips are stacked and mounted, as shown in FIG. 4, the semiconductor chip 34a is bonded to the upper surface of the semiconductor chip pair 16, and the connection pads 33a and the connection pads 13a are bonded to the bonding wires. 38 may be connected.

  Furthermore, in the above-described second embodiment, the semiconductor chip pairs having the same size are stacked. However, the present invention is not limited to this, and for example, as shown in FIG. It is also possible to form a module package by adhering ordinary semiconductor chips 54 having different sizes and different functions to the uppermost upper surface. That is, the semiconductor chip 54 is bonded to the back surface of the semiconductor chip 14 b of the semiconductor chip pair 16, and the normal connection pads 53 of the semiconductor chip 54 are connected to the connection lands (on the surface of the module wiring board 12 by the bonding wires 58 ( (Not shown)), and the connection land and the external connection terminal 11 and / or the connection pad 13a of the semiconductor chip pair 16 may be electrically connected.

  Furthermore, in the above-described second embodiment, a module package is configured by stacking three or more semiconductor chips. However, the present invention is not limited to this, for example, as shown in FIG. The semiconductor chips 14a and 14b may be stacked. That is, the semiconductor chip pair 16 and the semiconductor chip 64 are bonded and mounted on the surface of the module wiring board 12, and the normal connection pads 63 of the semiconductor chip 64 are connected to the surface of the module wiring board 12 by the bonding wires 68. It is also possible to connect to a connection land (not shown) and electrically connect the connection land to the external connection terminal 11 and / or the connection pad 13a of the semiconductor chip pair 16.

  According to the first and second embodiments described above, a semiconductor device in which more semiconductor chips are mounted at a high density can be realized at a low cost.

  In the first and second embodiments, the external connection terminal 11 is a BGA ball. However, the present invention is not limited to this, and any connection terminal that can be formed on the back surface of the module wiring board 12 may be used. .

  Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

11, external connection terminal 12, module wiring boards 13a, 13b, 33a, 33b connection pads 14a, 14b, 34a, 34b semiconductor chip 15, 35 connection bumps 16, 36 semiconductor chip pair 17, 37 insulating adhesives 18, 38 Bonding wire 19, sealing resin 20a, 20b Reference side

Claims (5)

Each of the semiconductor chips has the same size as the first and second semiconductor chips, and each of these semiconductor chips has a long side with a short side at the peripheral edge of the first main surface. A plurality of substantially rectangular connection pads that are at least doubled are formed, and the long sides of the plurality of connection pads are formed along a first direction, and the plurality of connection pads are in the first direction. The layout arrangement of the plurality of connection pads of the first semiconductor chip and the layout arrangement of the plurality of connection pads of the second semiconductor chip are arranged along a second direction orthogonal to the first direction. The first main surface of the first semiconductor chip and the first semiconductor chip of the second semiconductor chip are formed so as to be reversed from each other along the second direction as viewed from the first main surface side. The first surface is bonded so as to face the main surface, and the first First and second semiconductors, wherein the second semiconductor chip is bonded to the first semiconductor chip while being displaced in the first direction so that at least a part of the connection pads of the semiconductor chip is exposed. Chip pair,
A connection bump connecting the connection pad of the first semiconductor chip and the connection pad of the second semiconductor chip;
A module substrate having an external connection terminal, the external connection terminal being electrically connected to the exposed connection pad of the first semiconductor chip via a bonding wire,
A second main surface of the first semiconductor chip pair opposite to the first main surface of the second semiconductor chip; and the first semiconductor chip of the second semiconductor chip pair of the first semiconductor chip. A semiconductor device, wherein a third main surface opposite to the main surface is bonded, and the first and second semiconductor chip pairs are stacked. First and second semiconductor chips each having a substantially rectangular connection pad formed on each first main surface;
At least in the first semiconductor chip, the long side of the connection pad is formed along the first direction, and the connection pad of the first semiconductor chip and the connection pad of the second semiconductor chip The first main surfaces of the first and second semiconductor chips are bonded to each other so that they face each other, and at least a part of the connection pads of the first semiconductor chip are exposed. Two semiconductor chips are bonded to the first semiconductor chip while being displaced in the first direction, and the connection pads of the first semiconductor chip and the connection pads of the second semiconductor chip are connected to each other. A semiconductor device characterized in that a semiconductor chip pair is constituted by the first and second semiconductor chips being electrically connected.   The first and second semiconductor chips each have a plurality of connection pads disposed along a second direction orthogonal to the first direction, and the plurality of connection pads of the first semiconductor chip. And the layout arrangement of the plurality of connection pads of the second semiconductor chip are formed so as to be inverted from each other along the second direction as viewed from the first main surface. The semiconductor device according to claim 2. A plurality of the semiconductor chip pairs,
The second main surface of the first semiconductor chip pair in the plurality of semiconductor chip pairs opposite to the first main surface in the second semiconductor chip, and the second of the second semiconductor chip pairs in the plurality of pairs. 4. The semiconductor device according to claim 2, wherein a first main surface of the first semiconductor chip is bonded to a third main surface opposite to the first main surface, and the first and second semiconductor chip pairs are stacked. The semiconductor device according to any one of the above.   The first and second semiconductors such that one side of the second semiconductor chip of the first semiconductor chip pair and one side of the first semiconductor chip of the second semiconductor chip pair overlap. The semiconductor device according to claim 1, wherein chip pairs are stacked.

Images