JP2013246693A - Control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control device that can improve accuracy of an electric power supply voltage while decreasing power consumption in a configuration in which a power source circuit employs two reference voltage generation circuits respectively featuring high accuracy and low power.SOLUTION: In an electronic control unit (ECU) 1, a power source circuit 6 is configured to be able to select any one of a reference voltage Vref1 generated by a high accuracy reference voltage generation circuit 8 and a reference voltage Vref2 generated by a low power reference voltage generation circuit 7 and generate a control power source VDD, and switches a reference voltage generation circuit so as to use the reference voltage Vref1 in a normal operation mode, and the reference voltage Vref2 in a sleep mode. The low power reference voltage generation circuit 7 is configured to be able to adjust a level of the reference voltage Vref2, and a central processing unit (CPU) 2 corrects the reference voltage Vref2 such that the reference voltage Vref2 stays at a predetermined level in the normal operation mode.

Description

  The present invention relates to a control device that includes a power supply circuit and can be executed by switching between a normal operation mode and a low power consumption mode.

  For example, a power supply circuit is mounted on an ECU (Electronic Control Unit) which is a vehicle-mounted control device, and the power supply circuit is required to have low power consumption and high accuracy. In particular, in a body control system that operates even when the vehicle engine is stopped, low power consumption is indispensable to prevent the battery from rising, but the power supply circuit itself is designed to suppress the operating current. Then, the circuit is easily affected by variations in temperature and elements, causing another problem that the accuracy of the power supply voltage is deteriorated.

  In order to solve such a problem, in Patent Document 1, in the first comparison circuit, when the detection voltage of the power source is compared with the first reference voltage generated by the high-accuracy reference voltage generation circuit, the detection voltage is used. In the second comparison circuit, compared with the second reference voltage generated by the low-power reference voltage generation circuit, in a region where the detected voltage exceeds the second reference voltage, the high-precision reference voltage generation circuit is output by the output signal of the second comparison circuit. Disclosed is a technique for reducing power consumption by stopping the operation.

JP 2001-296318 A

  However, in Patent Document 1, a high-precision reference voltage generation circuit is used in the former area, and the latter area is divided into an operation area where accuracy is required for the detected voltage and an operation area where accuracy is not required. Uses a low-power-consumption reference voltage generation circuit. Therefore, the high-accuracy reference voltage generation circuit is always operated in the operation area where accuracy is required, and the low-power reference voltage generation circuit is assumed to always operate, thereby reducing power consumption. However, there is room for improvement.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power source that further reduces power consumption in a configuration in which the power source circuit uses two reference voltage generation circuits each characterized by high accuracy and low power. It is an object of the present invention to provide a control device capable of improving voltage accuracy.

  According to the control device of the present invention, the power supply circuit selects either one of the first reference voltage generated by the high precision reference voltage generation circuit and the second reference voltage generated by the low power reference voltage generation circuit. The power supply can be generated and switched to use the first reference voltage in the normal operation mode and the second reference voltage in the low power consumption mode. The low power reference voltage generation circuit is configured to be able to adjust the level of the second reference voltage, and the correction unit corrects the second reference voltage to a predetermined level in the normal operation mode.

  With this configuration, the high-accuracy reference voltage generation circuit and the low-power reference voltage generation circuit can be switched and used in each of the normal operation mode and the low power consumption mode to reduce power consumption. In addition, a reference voltage generation circuit configured to reduce power consumption generally has low power supply voltage accuracy. Therefore, the correction means corrects the second reference voltage during the normal operation mode period in which the power supply circuit generates the power supply voltage based on the first reference voltage generated by the high-accuracy reference voltage generation circuit. It is also possible to improve the power supply voltage accuracy when the reference voltage generation circuit is used.

Functional block diagram showing the configuration of the ECU according to the first embodiment Diagram showing mainly the internal configuration of the low-power reference voltage generation circuit Sequence diagram showing state change of each part accompanying change in operation state of ECU The flowchart which shows the processing content when the operation state of ECU changes Flowchart showing correction processing of reference voltage Vref2 FIG. 4 is a partial equivalent diagram of the second embodiment (part 1). Partial equivalent diagram of FIG. 4 (part 2) 3 equivalent figure Partial equivalent diagram of FIG. 1 showing the third embodiment Equivalent to FIG. FIG. 9 equivalent diagram showing the fourth embodiment. 3 equivalent figure

(First embodiment)
Hereinafter, a first embodiment in which a control device of the present invention is applied to an ECU for vehicle control will be described. The ECU 1 (control device) includes a CPU 2 (correction means), a ROM 3 (correction means), a RAM 4, an A / D conversion circuit 5 (correction means), and a power supply circuit 6. The CPU 2, ROM 3, RAM 4 and A / D conversion circuit 5 are connected by an address bus and a data bus (actually a common bus). When the power supply circuit 6 generates the control power supply VDD based on the power supply + B supplied from the vehicle battery, the power supply circuit 6 supplies it to the CPU 2 and the like.

  The power supply circuit 6 includes two reference voltage generation circuits, a low power reference voltage generation circuit 7 and a high precision reference voltage generation circuit 8. As will be described in detail later, the low-power reference voltage generation circuit 7 generates a reference voltage Vref2 (second reference voltage) by dividing the power supply voltage + B with a voltage dividing resistor, for example, and adjusts the level of the reference voltage Vref2 It is configured to be possible. On the other hand, the high-accuracy reference voltage generation circuit 8 is composed of, for example, a band gap reference circuit or the like, and generates a reference voltage Vref1 (first reference voltage). These reference voltages Vref1 and Vref2 are alternatively selected via the selection circuit 9 and input to the power supply voltage generation circuit 10. The power supply voltage generation circuit 10 amplifies the input reference voltage with a predetermined amplification factor to generate a control power supply VDD (for example, 5V) and supplies it to each unit.

  The selection circuit 9 is composed of two analog switches 9a and 9b that are connected in common on the output terminal side, and these on / off controls are performed by the CPU 2. The power source + B is supplied to the low power reference voltage generation circuit 7 and the high precision reference voltage generation circuit 8 via P-channel MOSFETs 11 and 12, respectively. The on / off control of the P-channel MOSFETs 11 and 12 is also individually performed by the CPU 2.

  The reference voltage Vref2 generated and output by the low power reference voltage generation circuit 7 is configured such that the voltage level is adjusted by the correction circuit 13 (correction means), and control data is written and set in the correction circuit 13 by the CPU 2. . In FIG. 2, a low-power reference voltage generation circuit 7 includes 18 resistance elements 14a, 14b,..., 14r between the power source + B and the ground (FET 12 is omitted). A series circuit comprising: The resistance values of the power supply side resistance element 14a and the ground side resistance element 14r are set larger than those of the other resistance elements.

  From the common connection point of the resistance elements 14b and 14c to the common connection point of the resistance elements 14q and 14r, 16 switch circuits 15 (1), 15 (2),. One end of each of them is connected. The other ends of these switch circuits 15 are connected in common and serve as an output terminal of the low power reference voltage generation circuit 7.

  The correction circuit 13 is composed of a 16-bit control register, and the CPU 2 writes, for example, control data in which only one bit is “1”, so that the switch circuits 15 (1) to 15 (16 Only one of) is turned on. Thereby, the level of the reference voltage Vref2 is adjusted. The reference voltage Vref2 is given to the input terminal of the A / D conversion circuit 5, and the CPU 2 reads voltage data of the A / D converted reference voltage Vref2. Then, the CPU 2 determines control data to be output to the correction circuit 13 according to a result of comparing the voltage data with a reference value.

  In addition, the ECU 1 can switch the operation state between a normal operation mode and a sleep mode (low power consumption mode). In contrast to the normal operation mode in which the frequency of the clock signal supplied to the CPU 2 or the like is several M to several tens of MHz, for example, in the sleep mode, the frequency is lowered to, for example, several to several tens of kHz, Power consumption is reduced by stopping the supply itself. For this reason, the oscillation circuit that supplies the clock signal is configured to be capable of corresponding control (not shown because it is well known).

  Next, the operation of this embodiment will be described. As shown in FIG. 3A, as the operation state of the ECU 1 is switched between the sleep mode and the normal operation mode, the CPU 2 reduces the reference voltage used by the power supply circuit 6 to Vref2 and Vref1. Only one of the power reference voltage generation circuit 7 and the high precision reference voltage generation circuit 8 is operated. That is, in the sleep mode, the P-channel MOSFET 11 is turned on and the P-channel MOSFET 12 is turned off to operate the low power reference voltage generation circuit 7 (see (b)). For the selection circuit 9, the analog switch 9 a side is turned on, and the reference voltage Vref 2 is input to the power supply voltage generation circuit 9.

On the other hand, in the normal operation mode, the P-channel MOSFET 11 is turned off and the P-channel MOSFET 12 is turned on to operate the high-accuracy reference voltage generation circuit 8, and the selection circuit 9 is turned on on the analog switch 9b side to supply the reference voltage Vref1 as a power source. The voltage is input to the voltage generation circuit 9. When a request for entering the sleep mode is generated in the normal operation mode, the CPU 2 turns on the P-channel MOSFET 11 to operate the low power reference voltage generation circuit 7 and corrects the reference voltage Vref2, and then shifts to the sleep mode. (See FIG. 3C).
FIG. 3D shows a change in current consumption corresponding to the mode change in FIG. In the normal operation mode, the current consumption increases because the high-accuracy reference voltage generation circuit 8 is operated. In the sleep mode, the current consumption decreases because the low-power reference voltage generation circuit 7 is operated.

In FIG. 4, it is assumed that a “wake-up factor” that urges the transition from the state in which the ECU 1 is in the sleep mode to the normal operation mode has occurred (S1). Here, examples of the “wake-up factor” include the following.
When the ECU 1 is connected to the in-vehicle communication network as a communication node and data is transmitted from an ECU or the like as another communication node.
In the case where a predetermined change occurs in the target detected by various sensors in the ECU 1, for example, and an interrupt is generated for the CPU 2.
When the CPU 2 detects a level change of the input port to which the door switch is connected as the switch is turned on / off.

  When the “wake-up factor” occurs, for example, the CPU 2 operating with the low-speed clock signal (or the supply of the clock signal is resumed) turns on the P-channel MOSFET 12 on the high-precision reference voltage generation circuit 8 side (S2 ). Then, after waiting until the reference voltage Vref1 generated by the high-precision reference voltage generation circuit 8 is stabilized (S3: YES), the selection circuit 9 selects the high-precision reference voltage generation circuit 8 side (S4). Then, the P-channel MOSFET 11 on the low power reference voltage generation circuit 7 side is turned off (S5). Thereby, ECU1 transfers to normal operation mode.

In the normal operation mode, the CPU 2 determines whether or not a request for entering the sleep mode has occurred while executing a process to be executed during the mode (S6). Here, the “sleep input request” is, for example, an intrinsic request when an event to be processed in the ECU 1 does not occur for a predetermined time, or one of the communication nodes described above that controls the operation state of the ECU 1. For example, an external request by sending a command from a certain host controller.
When the “sleep request” is generated (S6: YES), the CPU 2 performs a correction process (correction sequence) of the reference voltage Vref2 (S7), and the selection circuit 9 selects the low power reference voltage generation circuit 7 side (S8). ). Then, when the P-channel MOSFET 12 on the high-accuracy reference voltage generation circuit 8 side is turned off (S9), a sleep input process is performed (S10, clock signal control, etc.).

  In FIG. 5, when the CPU 2 first turns on the P-channel MOSFET 11 and operates the low power reference voltage generation circuit 7 (S11), the level of the reference voltage Vref2 is A / D converted and read (S12). Here, an expected value for correcting the reference voltage Vref2 is stored in the ROM 3 in advance, and the CPU 2 compares the reference voltage Vref2 after A / D conversion with the expected value (S13), and the reference voltage Vref2 Is determined to be within the standard (S14). Specifically, for example, the expected value is 1.8 V corresponding to the reference voltage Vref1, and if it is within the range of 1.79 V to 1.81 V, it is within the standard. If the reference voltage Vref2 is within the standard (YES), the correction process is terminated.

  On the other hand, if the reference voltage Vref2 is not within the specification (S14: NO), the calculation is performed so that an optimum correction value is obtained according to the difference from the expected value (S15). When the correction circuit 13 determines which switch circuit 15 in the low power reference voltage generation circuit 7 is to be turned on (S16), the process returns to step S12. The above loop is repeated until “YES” is determined in step S14.

  As described above, according to this embodiment, the ECU 1 allows the power supply circuit 6 to select either the reference voltage Vref1 generated by the high-precision reference voltage generation circuit 8 or the reference voltage Vref2 generated by the low power reference voltage generation circuit 7. One of these is selected so that the control power supply VDD can be generated, and the reference voltage Vref1 is switched in the normal operation mode and the reference voltage Vref2 is switched in the sleep mode. The low power reference voltage generation circuit 7 is configured to be able to adjust the level of the reference voltage Vref2, and the CPU 2 corrects the reference voltage Vref2 to be a predetermined level in the normal operation mode.

  As a result, the high-accuracy reference voltage generation circuit 8 and the low-power reference voltage generation circuit 7 can be switched and used in each of the normal operation mode and the sleep mode, and the power consumption can be reduced. The low power reference voltage generation circuit 7 has a manufacturing variation of the resistance value of the resistance element 14 of about 20 to 30%. It also has a temperature characteristic of about 0.2% / ° C., and the resistance value fluctuates 2% at 10 ° C. and 10% at 50 ° C.

On the other hand, in a reference voltage generation circuit such as the high-accuracy reference voltage generation circuit 8, there is a case where the variation in output voltage is 1% or less including temperature characteristics. Therefore, the power supply circuit 6 corrects the reference voltage Vref2 within the normal operation mode period in which the power supply voltage VDD is generated based on the reference voltage Vref1 generated by the high-precision reference voltage generation circuit 8, so that variations can be reduced. It becomes possible to suppress to about 5%, and the accuracy of the power supply voltage can be improved. Thereby, for example, it is possible to prevent erroneous determination of ON / OFF input of the external switch in the sleep mode, data reception failure in communication, deterioration in A / D conversion accuracy, and the like, and the system reliability is also improved.
Further, since the CPU 2 corrects the reference voltage Vref2 only once before the transition from the normal operation mode to the sleep mode, the CPU 2 corrects the reference voltage Vref2 according to the operating environment immediately before the transition to the sleep mode, and is used in the sleep mode. The accuracy of the supplied power supply voltage VDD can be improved.

  The low power reference voltage generation circuit 7 has a series circuit of a plurality of resistance elements 14 connected between the input power source + B and the ground, one end connected in common, and the other end of each of the plurality of resistance elements 14. When the CPU 2 reads the voltage data of the reference voltage Vref2 A / D converted via the A / D conversion circuit 5 and determines the control data, the correction is made. One of the plurality of switch circuits 15 is alternatively turned on by writing the control data in a control register constituting the circuit 13. That is, when the low-power reference voltage generation circuit 7 is configured very simply by the resistance element 14 and the switch circuit 15, the CPU 2 can correct the reference voltage Vref2.

(Second embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described. In the second embodiment, the CPU 2 performs the correction process of the reference voltage Vref2 at a constant period in the normal operation mode (see FIG. 8D). That is, in FIG. 6, if “NO” is determined in the step S <b> 6, the process proceeds to a step S <b> 21 and it is determined whether or not the necessary correction time (a constant period) has elapsed. If the necessary correction time has not elapsed (NO), the process returns to step S6. If the necessary correction time has elapsed (YES), the correction sequence is executed (S7), and the process returns to step S6.

  If “YES” is determined in the step S6, the sleep sequence shown in FIG. 7 is executed (S22). This sleep sequence includes the steps S7 to S10 in the first embodiment. That is, immediately before the transition to the sleep mode, the correction sequence is executed once again (S7).

  As described above, according to the second embodiment, the CPU 2 periodically corrects the reference voltage Vref2 in the normal operation mode. As a result, in the correction sequence executed again when the sleep sequence is executed, it can be expected that the timing at which “YES” is determined in step S14 will be accelerated. It becomes possible to shift to the sleep mode.

(Third embodiment)
In the third embodiment, the voltage of the control power supply VDD in the normal operation mode is 5V as in the above embodiment, and the voltage of the control power supply VDD in the sleep mode is reduced to 3.3V. As shown in FIG. 9, by setting the reference voltage Vref2 generated by the low power reference voltage generation circuit 7 to 1.2V (adjusted by the correction circuit 13), the voltage of the control power supply VDD in the sleep mode is set to 3.3V. Set. In this case, the correction of the reference voltage Vref2 in step S14 is within the standard if it is within the range of 1.19V to 1.21V. As a result, the voltage of the control power supply VDD changes as shown in FIG.

  That is, since the CPU 2 is not required to operate at high speed in the sleep mode, there is no problem even if the voltage of the control power supply VDD is lowered. Since the voltage of the reference voltage Vref2 can be adjusted with high accuracy by the correction circuit 13, the control power supply voltage VDD is close to the minimum operable voltage when the minimum operable voltage of the circuit is about 3.1V, for example. 3.3V can be set. Thereby, power consumption can be reduced more.

(Fourth embodiment)
The fourth embodiment shows a case where the low power consumption mode includes two stages of a sleep mode and a standby mode. That is, in the sleep mode, the clock signal whose frequency is lower than that in the normal operation mode is supplied to the CPU 2 so that the CPU 2 operates. In the standby mode, the supply of the clock signal is stopped and the CPU 2 does not operate, and only the values of the internal registers of the CPU 2 and the data of the RAM 4 are held.

  In this case, the voltage of the control power supply VDD in the sleep mode is set to 5 V, which is the same as that in the normal operation mode, and the voltage of the control power supply VDD in the standby mode is reduced to 3.3V. As shown in FIG. 11, the reference voltage Vref2 generated by the low power reference voltage generation circuit 7 is switched to 1.8 V / 1.2 V by the correction circuit 13. As a result, according to the change of the operation mode, the voltage of the control power supply VDD changes as shown in FIG.

  As shown in FIG. 12C, when the wake-up from the standby or sleep mode and the reference voltage Vref2 is corrected in the normal operation mode, the correction is made with 1.8V as a reference (H). Similarly, in the correction sequence in FIG. 7: S7 when the sleep input request is generated and the mode is shifted to the sleep mode, correction is performed with 1.8V as a reference. On the other hand, in the correction sequence in FIG. 7: S7 when the standby input request is generated in the normal operation mode and the mode is shifted to the standby mode, correction is performed with 1.2V as a reference (L).

  In this case, as shown in FIG. 12D, the current consumption level in the sleep mode is between the normal operation mode and the standby mode. As described above, according to the fourth embodiment, it is possible to cope with the case where the low power consumption mode includes two stages of the sleep mode and the standby mode.

The present invention is not limited to the above-described embodiments, and the following modifications or expansions are possible.
You may change suitably the specific numerical value of each voltage.
The number of correction steps of the low power reference voltage generation circuit is not limited to 16 steps, and may be changed as appropriate according to individual design.
In the sleep sequence shown in FIG. 7, the correction sequence (S7) is not necessarily executed. It may be executed only when it is necessary to further improve the accuracy of the reference voltage Vref2 in the sleep mode.

Only the process of waking up periodically during the low power consumption mode and correcting the reference voltage Vref2 may be executed. For example, if 1 ms is required to wake up in a 1 s cycle and the correction process takes 1 ms, the power consumption is approximately 1/1000 compared to the case where the high-precision reference voltage generation circuit is continuously operated.
The specific configurations of the low-power reference voltage generation circuit and the high-precision reference voltage generation circuit are not limited to those illustrated, but the former is characterized by low power consumption and the latter is a voltage generation circuit characterized by high accuracy. I need it.
The correcting means may be constituted only by hardware logic.
The control device is not limited to an ECU, and can be applied to any microcomputer provided with a power supply circuit.

  In the drawings, 1 is an ECU (control device), 2 is a CPU (correction means), 3 is a ROM (correction means), 5 is an A / D conversion circuit (correction means), 6 is a power supply circuit, and 7 is a low power reference. A voltage generation circuit, 8 is a high-precision reference voltage generation circuit, and 13 is a correction circuit (correction means).

Claims (5)

In the control device (1) which includes the power supply circuit (6) and can be executed by switching between the normal operation mode and the low power consumption mode,
The power supply circuit selects either the first reference voltage generated by the high-precision reference voltage generation circuit (8) or the second reference voltage generated by the low power reference voltage generation circuit (7), Is configured to be able to generate
Switching to use the first reference voltage in the normal operation mode and the second reference voltage in the low power consumption mode,
The low power reference voltage generation circuit is configured to be capable of adjusting a level of the second reference voltage,
A control device comprising correction means (2, 3, 5, 13) for correcting the second reference voltage to a predetermined level in the normal operation mode.   The control device according to claim 1, wherein the correction unit performs the correction operation only once immediately before shifting from the normal operation mode to the low power consumption mode.   The control device according to claim 1, wherein the correction unit periodically performs the correction operation in the normal operation mode.   The said correction | amendment means adjusts the level of a said 2nd reference voltage so that the power supply voltage in the said low power consumption mode may be reduced rather than the power supply voltage in the said normal operation mode. The control apparatus in any one. The low power reference voltage generation circuit includes a series circuit of a plurality of resistance elements (14) connected between an input power source and a ground;
A plurality of switch circuits (15) each having one end connected in common and the other end connected to a common connection point of the plurality of resistance elements,
The correction means includes an A / D conversion circuit (5) for converting the second reference voltage A / D;
A CPU (2) for reading the A / D converted voltage data;
The control data is written by the CPU and comprises a control register (13) configured to selectively turn on any one of the plurality of switch circuits. 4. The control device according to any one of 4.

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