JP2013246425A - Display device and video output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate complexity of connection between a video output device and a display device in a case where a plurality of first to n-th videos obtained by dividing a one-frame video are transmitted from the video output device to the display device through a plurality of channels.SOLUTION: A display device can be connected to a video output device through first to n-th transmission channels (where, n is an integer of two or more). The display device transmits m-th group information on a plurality of pixels that belong to an m-th group when a plurality of pixels of a display part is grouped into first to n-th groups, to an m-th transmittance channel.

Description

  The present invention relates to video output and display.

  The number of pixels of the current High Definition television (HDTV) is 1920 × 1080 (so-called 2K1K), but the number of pixels is 4 times that of HDTV (so-called 4K2K) or 16 times the number of pixels. Several (so-called 8K4K) video standards (Super Hi-Vision SHV is one of them) have been proposed.

  In Patent Document 1, a plurality of video data obtained by dividing frame data of one frame (the number of pixels exceeds the number of pixels of HDTV) is divided into a plurality of channels (each channel is an HD-SDI standard). A configuration for transmitting data is disclosed.

JP 2009-130639 A

  As described above, when one frame video is transmitted from the video output device to the display device through a plurality of channels, the connection relationship between the video output device and the display device becomes complicated. An object of the present invention is to eliminate such complications.

  This display device is a display device that can be connected to the video output device via the first to n-th transmission lines, where n is an integer of 2 or more, where m is an integer of 1 to n, and the display unit The m-th group information regarding the plurality of pixels belonging to the m-th group when the plurality of pixels are grouped into the first to n-th groups is transmitted to the m-th transmission line.

  In this display device, a plurality of pixels belonging to the mth group may be configured to be gathered in the mth region when the display unit is divided into the first to nth regions.

  In the present display device, the m-th group information can also be configured as position designation data that designates the position of the m-th region in the display unit.

  In this display device, when the display unit is divided into a plurality of blocks each composed of n pixels, a plurality of pixels belonging to the m-th group may be dispersed in different blocks. .

  In the present display device, the m-th group information can also be configured as position designation data that designates the position of the m-th pixel in each block.

  In the present display device, the position designation data may be included in EDID (Extended Display identification Date).

  The display device may be configured to transmit a retry signal to the m-th transmission line when there is a problem with the input state from the m-th transmission line.

  In the present display device, when the above problem is not solved even after a retry signal is transmitted to the mth transmission path, a pseudo signal corresponding to the mth group can be generated by itself to perform fail-safe display.

  The video output device is a video output device that can be connected to the display device according to claim 1 via the first to n-th transmission lines, from the display device to the first to n-th transmission lines. The first to nth group information obtained via the first frame is divided into the first to nth video, and m is an integer from 1 to n, and the mth transmission line is used as the mth group information. The m-th video corresponding to is output.

  In the present video output device, the m-th video may be configured to include the number of pixels exceeding the video standard of high-definition television broadcasting.

  In the present video output device, the m-th video may be a 1 / n partial video having the same definition as the one-frame video.

  In the present video output device, the m-th video may be a whole video having a 1 / n definition of one frame video.

  In the present video output apparatus, the m-th transmission path may be configured to be HDMI (High-definition Multimedia Interface) standard.

  This video output device is configured to output the m-th video corresponding to the m-th group information again when a retry signal indicating that a problem has occurred in the input status of the m-th transmission path is received from the display device. You can also.

  According to the present invention, when one frame video is transmitted between the video output device and the display device through a plurality of channels, the troublesome connection between the video output device and the display device is eliminated.

1 is a schematic diagram illustrating a configuration of a display device of Example 1. FIG. 1 is a schematic diagram illustrating a configuration of a video output device according to Embodiment 1. FIG. FIG. 3 is a schematic diagram illustrating a connection state between the display device and the video output device according to the first embodiment. It is a schematic diagram which shows the content of the position designation data of Example 1. FIG. FIG. 3 is a schematic diagram illustrating functions of the video output device according to the first embodiment. It is a schematic diagram which shows the state of the display apparatus and video output device after FIG. It is a schematic diagram which shows the state which changed the connection relationship of FIG. It is a schematic diagram which shows the state which changed the connection relationship of FIG. It is a schematic diagram which shows the state at the time of the problem occurrence in a display apparatus. FIG. 3 is a schematic diagram illustrating a problem countermeasure (retry signal) of the display device according to the first embodiment. FIG. 3 is a schematic diagram illustrating fail-safe display of the display device according to the first embodiment. FIG. 6 is a schematic diagram illustrating a connection state between a display device and a video output device according to a second embodiment. It is a schematic diagram which shows the content of the position designation data of Example 2. FIG. 6 is a schematic diagram illustrating functions of a video output device according to a second embodiment. It is a schematic diagram which shows the state of the display apparatus and video output device after FIG. It is a schematic diagram which shows the state which changed the connection relationship of FIG. It is a schematic diagram which shows the state which changed the connection relationship of FIG. It is a schematic diagram which shows the modification of the display apparatus of Example 1-2. 6 is a schematic diagram illustrating a configuration of a display device according to Example 3. FIG. FIG. 6 is a schematic diagram illustrating a connection state between a display device and a video output device according to a third embodiment. It is a schematic diagram which shows the content of the position designation data of Example 3. It is a schematic diagram which shows the state of the display apparatus and video output apparatus after FIG. FIG. 10 is a schematic diagram illustrating a connection state between a display device and a video output device according to a fourth embodiment. It is a schematic diagram which shows the content of the position designation data of Example 4. FIG. 10 is a schematic diagram illustrating functions of a video output device according to a fourth embodiment. It is a schematic diagram which shows the state of the display apparatus and video output apparatus after FIG. It is a schematic diagram which shows the modification of the display apparatus of Example 3 * 4.

  The embodiment of the present invention will be described below with reference to FIGS.

[Example 1]
As shown in FIG. 1, the display device 1 according to the first embodiment includes an interface circuit IF, a memory R, a video processing circuit IPC, timing controllers TC1 to TC4, a gate driver GD and a source driver SD, and a display unit DPS. A liquid crystal panel LCP including the backlight BL. The liquid crystal panel LCP is, for example, a so-called 4K2K panel (ultra-high-definition liquid crystal panel) having horizontal 3840 pixels or 4096 pixels × vertical 2160 pixels, and the display unit DPS is divided into four regions AR1 to AR4. Note that an EDID (Extended Display Identification Date) that is display information is stored in the memory R (for example, EEPROM), and this EDID usually includes data indicating display items, timing characteristics, color characteristics, and corresponding resolution. ing.

  As shown in FIG. 2, the video output device 2 according to the first embodiment includes an interface circuit if and a video generation circuit igc. As shown in FIG. 3, the interface circuit IF of the display device 1 and the video output device. The two interface circuits if are connected by four transmission lines (channels, cables) T1 to T4. Each transmission path is, for example, the HDMI (High-definition Multimedia Interface) standard.

  Here, the EDID of the memory R of the display device 1 includes position specifying data Km for specifying the position of the area ARm (m is an integer of 1 to 4), and the interface circuit IF is included in the EDID. The position designation data Km is transmitted to the transmission line Tm. That is, the interface circuit IF transmits the position specifying data K1 specifying the position of the area AR1 to the transmission line T1, transmits the position specifying data K2 specifying the position of the area AR2 to the transmission line T2, and transmits the transmission line T3. Then, the position designation data K3 for designating the position of the area AR3 is transmitted, and the position designation data K4 for designating the position of the area AR4 is transmitted to the transmission line T4.

  As shown in FIG. 4, the position designation data Km designates the position of the area ARm by the coordinates of the display unit, and the area ARm designated by the position designation data Km is 2K × 1K pixels (mth Group). For example, K1 includes coordinates (X0, Y0) and coordinates (X1, Y1), and an area AR1 (consisting of 2K × 1K pixels that are the first group Gr1) is designated by K1. K2 includes coordinates (X1, Y0) and coordinates (X2, Y1), and an area AR2 (consisting of 2K × 1K pixels that are the second group Gr2) is designated by K2. The same applies to K3 and K4.

  The position designation data K1 to K4 are input to the interface circuit if of the video output device 2. Based on K1 to K4, the video generation circuit igc converts the frame video FIM (the number of pixels is 4K × 2K) into four partial videos IM1 to IM4 (the number of pixels) having the same definition as the FIM, as shown in FIG. Is divided into 2K × 1K) to generate video data D1 to D4 corresponding to the partial videos IM1 to IM4. Further, as shown in FIG. 6, the video generation circuit igc outputs corresponding video data D1 to D4 to the transmission paths T1 to T4 via the interface circuit if.

  The video data D1 to D4 are input to the video processing circuit IPC via the interface circuit IF. The video processing circuit IPC that has received the video data D1 to D4 and the timing controllers TC1 to TC4 cooperate to generate control signals (video signals and timing signals) corresponding to the areas AR1 to AR4, respectively, and output them to the gate driver GD. And output to the source driver SD.

  The gate driver GD and the source driver SD receive the control signal from the timing controller TC1 to drive each pixel in the area AR1, and receive the control signal from the timing controller TC2 to drive each pixel in the area AR2. In response to a control signal from the controller TC3, each pixel in the area AR3 is driven, and in response to a control signal from the timing controller TC4, each pixel in the area AR4 is driven. As a result, the display shown in FIG.

  According to the first embodiment, as shown in FIGS. 3 and 6 to 8, no matter how the connection relationship between the interface circuit IF of the display device 1 and the interface circuit if of the video output device 2 is changed, Regardless of how the display area is divided, the interface circuit IF receives video data D1 to D4 suitable for the display area division (pixel grouping of the display area), and correct display is performed. Therefore, the troublesome connection between the video output device and the display device when one frame video is transmitted between the video output device and the display device through a plurality of channels is eliminated.

  In the display device 1, when a problem occurs in the input status from one or more transmission paths, a retry signal indicating non-conformity of the video data format or defective line condition is transmitted to the transmission path in which the problem has occurred. . For example, as shown in FIGS. 9 and 10, when a problem occurs in the input status from the transmission line T3, a retry signal RT is transmitted to the transmission line T3. The video output device 2 receives the retry signal RT from the transmission line T3, performs initialization again, and outputs the video data D1 to D4 to the transmission lines T1 to T4.

  If the input state only needs to be resolved by retrying, but if it still does not resolve, as shown in FIG. 11, the display device 1 cooperates with the video processing circuit IPC and the timing controller TC3, the dummy control signal corresponding to the area AR3. DS (pseudo video signal and timing signal) is generated and output to the gate driver GD and the source driver SD to perform fail-safe display. In this way, even if a problem occurs in any of the transmission paths, the entire screen cannot be displayed (the entire display device is inoperable), and the cause of the problem (input failure) can be easily traced.

[Example 2]
In the EDID of the memory R of the display device 1 of the second embodiment shown in FIG. 12, the display unit DPS is divided into a large number of blocks each consisting of 4 pixels in 2 rows and 2 columns, as shown in FIG. Position designation data km for designating the position of the mth pixel (m is an integer of 1 to 4) in each block is included, and the interface circuit IF transmits the position designation data km included in the EDID to the transmission line Tm. Send to. That is, the interface circuit IF transmits the position designation data k1 that designates the position of the first pixel in each block to the transmission path T1, and the position that designates the position of the second pixel in each block to the transmission path T2. Position designation data k3 is transmitted, position designation data k3 for designating the position of the third pixel in each block is transmitted to the transmission path T3, and position for designating the position of the fourth pixel in each block to the transmission path T4 The designated data k4 is transmitted.

  As shown in FIG. 13, the position designation data k1 includes the first pixels (2K × 1K pixels including Pa1 to Pa4 and distributed throughout the display unit, the first The group Gr1) is designated. In addition, the position designation data k2 designates the second pixel (2K × 1K pixels including the Pb1 to Pb4 and distributed throughout the display unit, the second group Gr2) located in the second row and the first column of each block. To do. Further, the position designation data k3 designates the third pixel (2K × 1K pixels distributed in the entire display unit, including Pc1 to Pc4, the third group Gr3) located in the first row and the second column of each block. To do. Further, the position designation data k4 designates the fourth pixel (2K × 1K pixels including the Pd1 to Pd4 and distributed throughout the display unit, the fourth group Gr4) located in the second row and second column of each block. To do.

  The position designation data k1 to k4 are input to the interface circuit if of the video output device 2. Based on k1 to k4, the video generation circuit igc converts the frame video FIM (the number of pixels is 4K × 2K) into four whole videos im1 to im4 (the number of pixels) having a lower definition than the FIM, as shown in FIG. Is divided into 2K × 1K) to generate video data d1 to d4 corresponding to the (low definition) whole video im1 to im4. Further, as shown in FIG. 15, the video generation circuit igc outputs corresponding video data d1 to d4 to the transmission lines T1 to T4 via the interface circuit if.

  The video data d1 to d4 are input to the video processing circuit IPC via the interface circuit IF. The video processing circuit IPC that has received the video data d1 to d4 and the timing controllers TC1 to TC4 cooperate to generate control signals (video signals and timing signals) corresponding to the areas AR1 to AR4, respectively, and output them to the gate driver GD. And output to the source driver SD.

  The gate driver GD and the source driver SD receive the control signal from the timing controller TC1 to drive each pixel in the area AR1, and receive the control signal from the timing controller TC2 to drive each pixel in the area AR2. In response to a control signal from the controller TC3, each pixel in the area AR3 is driven, and in response to a control signal from the timing controller TC4, each pixel in the area AR4 is driven. As a result, the display shown in FIG.

  According to the second embodiment, as shown in FIGS. 12 and 15 to 17, no matter how the connection relationship between the interface circuit IF of the display device 1 and the interface circuit if of the video output device 2 is changed, Regardless of the pixel arrangement in the block, the interface circuit IF receives video data d1 to d4 suitable for the pixel arrangement (grouping of pixels in the display unit) in the block, and correct display is performed. Therefore, the troublesome connection between the video output device and the display device when one frame video is transmitted between the video output device and the display device through a plurality of channels is eliminated.

  Although the display device 1 according to the first and second embodiments includes four timing controllers, the present invention is not limited to this. For example, as shown in FIG. 18, only two timing controllers (TCA · TCB) may be provided. In this case, the gate driver GD and the source driver SD receive the control signal from the timing controller TCA to drive each pixel in the area AR1 and the area AR2, and receive the control signal from the timing controller TCB in the areas AR3 and AR4. Each pixel is driven.

Example 3
FIG. 19 is a configuration example of a display device including a 4K2K panel corresponding to Super Hi-Vision and the like, and FIG. 20 illustrates a connection example between the display device of FIG. 19 and the video output device 2.

  The EDID of the memory R of the display device 1 in FIG. 20 includes position specifying data Km that specifies the position of the area ARm (m is an integer of 1 to 16), and the interface circuit IF is included in this EDID. The position designation data Km is transmitted to the transmission line Tm.

  As shown in FIG. 21, the position designation data Km designates the position of the area ARm by the coordinates of the display unit, and the area ARm designated by the position designation data Km has 2K × 1K pixels (mth Group). For example, K1 includes coordinates (x0, y0) and coordinates (x1, y1), and an area AR1 (consisting of 2K × 1K pixels that are the first group Gr1) is designated by K1. K2 includes coordinates (x1, y0) and coordinates (x2, y1), and an area AR2 (consisting of 2K × 1K pixels that are the second group Gr2) is designated by K2. The same applies to K3 to K16.

  The position designation data K1 to K16 are input to the interface circuit if of the video output device 2. Based on K1 to K16, the video generation circuit igc converts the frame video (the number of pixels is 4K × 2K) into 16 partial videos having the same definition as the frame video (the number of pixels of each partial image is 2K × 1K). The video data D1 to D16 corresponding to the 16 partial videos are generated. Further, as shown in FIG. 22, the video generation circuit igc outputs corresponding video data D1 to D16 to the transmission paths T1 to T16 via the interface circuit if.

  The video data D1 to D16 are input to the video processing circuit IPC via the interface circuit IF. The video processing circuit IPC that has received the video data D1 to D16 and the timing controllers TC1 to TC16 cooperate to generate control signals (video signals and timing signals) corresponding to the areas AR1 to AR16, respectively, and output them to the gate driver GD. And output to the source driver SD.

  According to the display device 1 and the video output device 2 of the third embodiment, no matter how the connection relationship between the interface circuit IF of the display device 1 and the interface circuit if of the video output device 2 is changed, the display area Regardless of the division method, the interface circuit IF receives video data D1 to D16 suitable for the display area division (grouping of pixels of the display area), and correct display is performed. Therefore, the troublesome connection between the video output device and the display device when one frame video is transmitted between the video output device and the display device through a plurality of channels is eliminated.

Example 4
As shown in FIG. 24, the EDID of the memory R of the display device 1 (4K2K panel mounted) according to the fourth embodiment shown in FIG. 23 includes a display unit DPS having a large number of blocks each consisting of 16 pixels in 4 rows and 4 columns. Position designation data km for designating the position of the m-th pixel (m is an integer of 1 to 16) in each block when the block is divided, and the interface circuit IF includes the position designation data included in the EDID. km to the transmission line Tm. That is, the interface circuit IF transmits the position designation data k1 that designates the position of the first pixel in each block to the transmission path T1, and the position that designates the position of the second pixel in each block to the transmission path T2. The designated data k2 is transmitted. The same applies to the position designation data k3 to k16.

  As shown in FIG. 24, for example, the position designation data k1 is the first pixel located in the first row and the first column of each block (2K × 1K pixels including Pa1 to Pa4, distributed throughout the display unit, The first group Gr1) is designated. For example, the position designation data k2 designates the second pixel (2K × 1K pixels including the Pb1 to Pb4 and distributed throughout the display unit, the second group Gr2) located in the second row and the first column of each block. To do. For example, the position designation data k15 designates the 15th pixel (2K × 1K pixels distributed in the entire display unit, including Po1 to Po4, the 15th group Gr15) located in the third row and the fourth column of each block. To do. For example, the position designation data k16 designates the 16th pixel located in the 4th row and the 4th column of each block (2P × 1K pixels including the Pp1 to Pp4 and distributed throughout the display unit, the 16th group Gr16). To do.

  The position designation data k1 to k16 are input to the interface circuit if of the video output device 2. Based on k1 to k16, the video generation circuit igc generates a frame video FIM (the number of pixels is 4K × 2K) based on k1 to k16, and includes 16 entire frames having 1/16 the definition of FIM. The video images d1 to d16 corresponding to the (low definition) whole video images im1 to im16 are generated by dividing the video images im1 to im16 (the number of pixels is 2K × 1K). Further, as shown in FIG. 26, the video generation circuit igc outputs corresponding video data d1 to d16 to the transmission paths T1 to T16 via the interface circuit if.

  The video data d1 to d16 are input to the video processing circuit IPC via the interface circuit IF. The video processing circuit IPC that has received the video data d1 to d16 and the timing controllers TC1 to TC16 cooperate to generate control signals (video signals and timing signals) corresponding to the areas AR1 to AR16, respectively, and output them to the gate driver GD. And output to the source driver SD.

  Then, the gate driver GD and the source driver SD receive the control signals from the timing controllers TC1 to TC16 and drive the respective pixels in the corresponding areas AR1 to AR16, whereby the display as shown in FIG. 26 is obtained.

  Although the display device 1 according to the third and fourth embodiments includes 16 timing controllers, the present invention is not limited to this. For example, as shown in FIG. 27, the number of timing controllers may be four (TCa to TCd). In this case, the gate driver GD and the source driver SD receive the control signal from the timing controller TCa to drive the pixels in the areas AR1 to AR4, and receive the control signal from the timing controller TCb to receive the control signals from the areas AR5 to AR8. Each pixel is driven, each pixel in the areas AR9 to AR12 is driven in response to a control signal from the timing controller TCc, and each pixel in each of the areas AR13 to AR16 is driven in response to a control signal from the timing controller TCd.

  According to the display device 1 and the video output device 2 of the fourth embodiment, no matter how the connection relationship between the interface circuit IF of the display device 1 and the interface circuit if of the video output device 2 is changed, the pixels in the block Regardless of the arrangement method, the interface circuit IF receives video data d1 to d16 suitable for the pixel arrangement (grouping of pixels of the display unit) in the block, and correct display is performed. Therefore, the troublesome connection between the video output device and the display device when one frame video is transmitted between the video output device and the display device through a plurality of channels is eliminated.

  The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on known techniques and common general knowledge or combinations thereof are also included in the embodiments of the present invention. It is. In addition, the operational effects described in each embodiment are merely examples.

  The present invention is suitable, for example, for an ultra-high definition liquid crystal display device.

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Video | video output apparatus LCP Liquid crystal panel TC1-TC16 Timing controller T1-T16 Transmission path IF if Interface circuit K1-K16 Position designation data k1-k16 Position designation data R Memory

Claims (14)

A display device that can be connected to a video output device via the first to nth transmission lines, where n is an integer of 2 or more,
m is an integer of 1 to n, and m-th group information regarding a plurality of pixels belonging to the m-th group when the plurality of pixels of the display unit are grouped into the first to n-th groups is transmitted to the m-th transmission line. Display device.   The display device according to claim 1, wherein a plurality of pixels belonging to the mth group are gathered in the mth region when the display unit is divided into the first to nth regions.   The display device according to claim 2, wherein the m-th group information is position designation data for designating a position of an m-th area in the display unit. When the display unit is divided into a plurality of blocks each consisting of n pixels,
The display device according to claim 1, wherein a plurality of pixels belonging to the mth group are distributed in different blocks.   The display device according to claim 4, wherein the m-th group information is position designation data that designates the position of the m-th pixel in each block.   6. The display device according to claim 3, wherein the position designation data is included in an extended display identification date (EDID).   The display device according to claim 1, wherein a retry signal is transmitted to the mth transmission line when a problem occurs in an input state from the mth transmission line.   The display device according to claim 7, wherein if the problem is not solved even after a retry signal is transmitted to the m-th transmission path, a pseudo signal corresponding to the m-th group is generated by itself to perform fail-safe display. A video output device capable of being connected to the display device according to claim 1 via the first to nth transmission lines,
Based on the first to n-th group information obtained from the display device via the first to n-th transmission lines, the 1-frame video is divided into the first to n-th video,
A video output device that outputs m-th video corresponding to m-th group information to an m-th transmission line, where m is an integer from 1 to n.   The video output device according to claim 9, wherein the m-th video includes a number of pixels exceeding a video standard for high-definition television broadcasting.   The video output device according to claim 9, wherein the m-th video is a 1 / n partial video having the same definition as one frame video.   The video output device according to claim 9, wherein the m-th video is a whole video having a definition of 1 / n of one frame video.   The video output device according to claim 9, wherein the m-th transmission path is a high-definition multimedia interface (HDMI) standard.   10. The video output device according to claim 9, wherein when a retry signal indicating that a problem has occurred in the input status of the m-th transmission path is received from the display device, the m-th video corresponding to the m-th group information is output again.

Images