JP2013243289A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which prevents a short circuit between a control gate electrode and a memory gate electrode.SOLUTION: A semiconductor device manufacturing method comprises: performing an etching treatment by using a photoresist pattern as a mask, which covers a part of a silicon nitride film, covering a top face of a control gate, that extends to one side from an intermediate position in a gate length direction, and which exposes a part that extends to another side opposite to the one side form the intermediate position in the gate length direction to leave the part that extends to the one side and remove the part that extends to the other side thereby to expose the top face of the control gate electrode; and forming a cobalt silicide film on the exposed top face of the control gate electrode and on a surface of a memory gate electrode.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and in particular, can be suitably used for a method for manufacturing a semiconductor device including a flash memory having a split gate type MONOS structure.

  A flash memory is widely used as a nonvolatile semiconductor memory. One type of such flash memory is a flash memory employing a split gate type MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure. In a memory cell transistor of this type of flash memory, a memory gate electrode for operating the memory cell and a control gate electrode for selecting the memory cell are separated. The memory gate electrode is formed in a sidewall shape on the side wall of the control gate electrode with an insulating film holding charge interposed therebetween.

  Next, an example of the operation of this type of flash memory will be described. Writing is performed by a so-called SSI (Source Side Injection) method. That is, writing is performed by injecting hot lectron generated by accelerating electrons flowing from the drain region to the source region into an insulating film that retains electric charges located immediately below the memory gate electrode. By injecting hot electrons into the insulating film holding electric charge, the threshold voltage of the memory gate electrode is increased.

  On the other hand, erasure is performed by a band-to-band tunnel phenomenon (BTBT (Band To Band Tunneling) erasure). That is, erasing is performed by injecting holes generated in the vicinity of the end portion of the memory source region located immediately below the memory gate electrode into the insulating film that holds charges. The threshold voltage of the memory gate electrode raised by hot electron injection is lowered by hole injection.

  Reading is performed by applying a voltage between the threshold voltage of the memory gate electrode in the written state and the threshold voltage of the memory gate electrode in the erased state to the memory gate electrode as the threshold voltage. Or whether it is in the erased state. Patent Documents 1, 2, and 3 are documents disclosing a flash memory having a split gate type MONOS structure.

JP 2011-2222938 A JP 2011-103401 A JP 2010-67645 A

  However, the above-described split gate type MONOS structure flash memory has the following problems.

  In a write operation of a flash memory, a voltage of about 1V is normally applied to the control gate electrode, and a voltage of about 11V is applied to the memory gate electrode. For this reason, a potential difference of about 10 V is generated between the control gate electrode and the memory gate electrode via an insulating film such as an ONO film, and a breakdown voltage exceeding 10 V is generated between the control gate electrode and the memory gate electrode. Is required. In order to ensure this withstand voltage, a structure (SiNCAP structure) in which the upper surface of the control gate electrode is covered with a silicon nitride film is proposed in the flash memory of the MONOS structure disclosed in Patent Document 1.

  On the other hand, in the case of a flash memory with a split gate type MONOS structure, the control gate electrode and the memory gate electrode are silicided to control the array, thereby reducing the resistance and the read access time is affected by the RC time constant. It is necessary to be at a level that will not be affected. In order to increase the operation speed of the flash memory by reducing the resistance of the control gate electrode, there is a method of forming a metal silicide on the control gate electrode. The metal silicide is formed in a self-aligned manner by reacting the metal and silicon.

  This method is called the salicide method. However, in the flash memory described above, the SiNCAP structure is adopted, and the upper surface of the control gate electrode is covered with the silicon nitride film, so that metal silicide cannot be formed.

  Conventionally, in order to avoid short-circuiting of the above-described wirings (a wiring including a control gate electrode and a wiring including a memory gate electrode), a structure that is not silicided has been adopted by applying a SINCAP structure only to the control gate electrode. . Then, the influence of the RC time constant caused by the structure that is not silicided is avoided by shortening the length of the wiring including the control gate electrode (array crossing length).

  On the other hand, if the silicon nitride film covering the upper surface of the control gate electrode is eliminated, the metal silicide formed on the control gate electrode and the metal silicide formed on the memory gate electrode are connected when forming the metal silicide. Therefore, it is assumed that an electrical short circuit occurs.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the method for manufacturing a semiconductor device according to an embodiment, of the first coating films covering the upper surface of the control gate electrode, the first coating film extending from the middle position in the gate length direction to the one side. By covering the portion and performing etching using the photoresist pattern that exposes the second portion of the first coating film extending from the middle position in the gate length direction to the other side opposite to the one side as a mask, A step of removing the second portion leaving the first portion of the first coating film and exposing the upper surface of the control gate electrode; and a metal on a predetermined surface including the exposed upper surface of the control gate electrode and the surface of the memory gate electrode Forming a silicide film.

  According to the method of manufacturing a semiconductor device according to the embodiment, it is possible to prevent the control gate electrode and the memory gate electrode from being electrically short-circuited.

FIG. 3 is a diagram showing a manufacturing flow of the semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a plan view showing a process performed after the process shown in FIG. 11 in the same embodiment. FIG. 13 is a cross sectional view taken along a cross sectional line XIII-XIII shown in FIG. 12 in the same embodiment. FIG. 13 is a cross sectional view taken along a cross sectional line XIV-XIV shown in FIG. 12 in the same embodiment. FIG. 6 is a diagram for explaining the operation of the memory cell transistor in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on a comparative example. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16. It is sectional drawing which shows the process performed after the process shown in FIG. 12 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the same embodiment. FIG. 27 is a plan view showing a step performed after the step shown in FIG. 26 in the same embodiment. FIG. 28 is a cross sectional view taken along a cross sectional line XXVIII-XXVIII shown in FIG. 27 in the same embodiment. FIG. 28 is a cross sectional view taken along a cross sectional line XXIX-XXIX shown in FIG. 27 in the same embodiment. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in the same embodiment.

Embodiment 1
A method for manufacturing a semiconductor device having a flash memory will be described first with reference to the flowchart shown in FIG. In step S1, a polysilicon film to be a control gate electrode of the memory cell transistor is formed. Next, in step S2, a silicon nitride film is formed so as to cover the polysilicon film. Next, in step S3, the control gate electrode of the memory cell transistor is formed by patterning the silicon nitride film and the polysilicon film.

  Next, in step S4, a memory gate electrode is formed on the side wall of the control gate electrode. Next, in step S5, a memory drain region is formed by implanting impurities of a predetermined conductivity type using a predetermined photoresist pattern as a mask. Next, in step S6, the silicon nitride film on the control gate electrode is partially removed by performing an etching process using the photoresist pattern as a mask. Next, in step S7, a metal silicide film is formed on the exposed surface of the control gate electrode and the surface of the memory gate electrode. Thus, the main part of the memory cell transistor in the semiconductor device including the flash memory cell is formed.

  Next, an example of a method for manufacturing the semiconductor device will be specifically described. As shown in FIG. 2, by forming an element isolation insulating film TB from the main surface of the semiconductor substrate SB to a predetermined depth, the element formation region includes a memory cell transistor region TRR in which a memory cell transistor is formed. A memory cell region MCR and a region (not shown) in which peripheral circuits are formed are defined. 2 to 9, the memory cell region MCR shows a cross-sectional structure in the word line direction WLD and a cross-sectional structure in a direction SLD substantially orthogonal to the word lines.

  Next, a gate oxide film GZ is formed on the surface of the semiconductor substrate SB in the memory cell region MCR by performing a thermal oxidation process. Next, a polysilicon film TS to be a control gate electrode or the like is formed so as to cover the gate oxide film GZ by, for example, chemical vapor deposition. Next, a TEOS (Tetra Ethyl Ortho Silicate glass) film TE is formed so as to cover the polysilicon film TS by, for example, chemical vapor deposition. Next, the silicon nitride film CP is formed so as to cover the TEOS film TE, for example, by chemical vapor deposition.

  Next, a predetermined photolithography process is performed to form a resist pattern (not shown) for patterning the control gate electrode. Next, using the photoresist pattern as a mask. A control gate electrode CG (see FIG. 3) is formed by etching the silicon nitride film CP and the polysilicon film TS. Thereafter, the photoresist pattern is removed, and the silicon nitride film CP covering the control gate electrode CG is exposed as shown in FIG.

  Next, by repeating the oxidation process, the nitridation process, etc., as shown in FIG. 4, an ONO film TZ made of a laminated film of a silicon oxide film, a silicon nitride film and a silicon oxide film is formed so as to cover the control gate electrode CG. It is formed. Next, as shown in FIG. 5, a doped polysilicon film DTS is formed so as to cover the ONO film TZ, for example, by chemical vapor deposition.

  Next, an anisotropic etching process is performed on the entire surface of the doped polysilicon film DTS to leave a portion of the doped polysilicon film DTS located on the side wall of the control gate electrode CG as shown in FIG. The portion of the doped polysilicon film DTS located on the upper surface of the control gate electrode CG is removed. Thus, a sidewall doped polysilicon film SWD is formed on the side wall of the control gate electrode CG.

  Next, as shown in FIG. 7, among the sidewall doped polysilicon films SWD formed on the both side walls of the control gate electrode CG, the sidewalls formed on the side wall located on one side in the gate length direction. A photoresist pattern PR1 is formed covering the doped polysilicon film SWD and exposing the sidewall doped polysilicon film SWD formed on the other side wall opposite to the one side. Next, the exposed sidewall doped polysilicon film SWD is removed by performing etching using the photoresist pattern PR1 as a mask, and the remaining sidewall doped polysilicon film SWD removes the memory gate electrode MG. Is formed.

  At this time, in the peripheral circuit region PER, the photoresist pattern PR1 is formed so as to cover the silicon nitride film CP located on the polysilicon film TS serving as the gate electrode with the TEOS film TE interposed therebetween. The photoresist pattern PR1 is also formed so as to cover a region where a capacitor is formed (not shown) and a region where a contact portion is formed (not shown).

  Next, after the photoresist pattern PR1 is removed, as shown in FIG. 8, the memory cell region MCR is covered while the peripheral circuit region PER is exposed, and a region (not shown) in which a capacitor is formed and a contact are formed. Photoresist pattern PR2 is formed so as to expose a region (not shown) where the portion is to be formed. Next, the silicon nitride film CP is removed by performing a predetermined etching process using the photoresist pattern PR2 as a mask. Thereafter, the photoresist pattern PR2 is removed.

  Next, as shown in FIG. 9, a photoresist pattern PR3 for patterning the gate electrode is formed in the peripheral circuit region PER. At this time, the photoresist pattern PR3 is formed so as to cover the memory cell region MCR and the region (not shown) in which the capacitor is formed.

  Next, by performing a predetermined etching process on the polysilicon film TS using the photoresist pattern PR3 as a mask, the polysilicon film TS to be a gate electrode is patterned. Next, after the photoresist pattern PR3 is removed, the patterned polysilicon film TS is oxidized to form a side wall oxide film SOF (see FIG. 10). At this time, an oxide film SOFM (see FIG. 10) is formed on the surface of the semiconductor substrate SB exposed in the memory cell region MCR.

  Next, as shown in FIG. 10, in the memory cell region MCR, a photoresist pattern PR4 that exposes a region to be a drain is formed. At this time, the peripheral circuit region PER is formed so as to cover the patterned polysilicon film TS and a region (not shown) in which a capacitor is formed. A memory drain region MDR is formed by implanting impurities of a predetermined conductivity type using the photoresist pattern PR4 as a mask. Next, the exposed silicon nitride film CP is removed by performing an etching process using the photoresist pattern PR4 as a mask. At this time, since the oxide film SOFM is formed on the surface of the semiconductor substrate SB, it is possible to prevent the surface of the semiconductor substrate SB from being etched (penetrated) when the silicon nitride film CP is removed. Thereafter, the photoresist pattern PR4 is removed.

  Next, a memory source region MSR (see FIG. 11) is formed by implanting impurities of a predetermined conductivity type using the memory gate electrode MG and the like as a mask. Next, an insulating film (not shown) such as an oxide film is formed so as to cover the control gate electrode CG, the memory gate electrode MG, and the like, and the entire surface of the insulating film is subjected to anisotropic etching to thereby control the control gate. A sidewall insulating film SWZ (see FIG. 11) is formed on the sidewall of the electrode CG and the sidewall of the memory gate electrode MG.

  Next, for example, a cobalt film (not shown) is formed so as to cover the exposed portion of the semiconductor substrate SB, the memory gate electrode MG, the control gate electrode CG, and the like. Next, by performing heat treatment at a predetermined temperature, the silicon and cobalt in the polysilicon films of the control gate electrode CG and the memory gate electrode MG are caused to react with each other, and the silicon and cobalt of the semiconductor substrate SB are reacted with each other. To form a cobalt silicide film MSL (not shown). Thereafter, the unreacted cobalt film is removed to expose the cobalt silicide film MSL as shown in FIG. Thus, the memory cell transistor MCTR is formed.

  At this time, the silicon nitride film CP is left on the upper surface of the control gate electrode CG on the memory gate electrode MG side. As a result, the cobalt silicide film MSL formed on the surface of the control gate electrode CG and the cobalt silicide film MSL formed on the memory gate electrode MG are connected, and the control gate electrode CG and the memory gate electrode MG are electrically connected. Can be prevented from being short-circuited.

  Thereafter, as shown in FIGS. 12, 13, and 14, an interlayer insulating film SZ (see FIG. 13) is formed so as to cover memory cell transistor MCTR and the like. Next, a contact hole CH exposing the surface of the cobalt silicide film MSL located in the memory drain region MDR and a surface of the cobalt silicide film MSL formed in the polysilicon film TS1 located in the contact region are formed in the interlayer insulating film SZ. Is formed as a contact hole CH that exposes.

  Next, metal plugs PLA and PLB are formed in the contact hole CH. Next, a wiring MA electrically connected to the metal plug PLA and a wiring MB electrically connected to the metal plug PLB are formed. Thereafter, if necessary, a multilayer wiring structure (not shown) including an upper layer wiring is formed. Thus, the main part of the semiconductor device provided with the flash memory is formed.

  Next, the operation of the memory cell transistor MCTR in the semiconductor device described above will be described. In FIG. 15, when performing write, erase, and read operations, the voltage is applied to the source region (memory source region) SR, the memory gate electrode MG, the control gate electrode CG, and the drain region (memory drain region) DR, respectively. An example of a voltage value is shown.

  First, in writing, for example, 6V is applied to the source region SR, 11V is applied to the memory gate electrode MG, 1.0V is applied to the control gate electrode CG, and 0.8V is applied to the drain region DR. At this time, hot lectron generated by accelerating electrons flowing from the drain region to the source region is injected into the ONO film holding charge, which is located immediately below the memory gate electrode. As hot electrons are injected into the ONO film, the threshold voltage of the memory gate electrode rises.

  On the other hand, in erasing, for example, 5 V is applied to the source region, −6 V is applied to the memory gate electrode, and 0 V is applied to the control gate electrode and the drain region. At this time, holes generated in the vicinity of the end portion of the memory source region located immediately below the memory gate electrode are injected into the ONO film that holds charges. The threshold voltage of the memory gate electrode raised by hot electron injection is lowered by injecting holes into the ONO film.

  In reading, the voltage applied to the memory gate electrode is an intermediate voltage between the threshold voltage of the memory gate electrode in the written state and the threshold voltage of the memory gate electrode in the erased state. For example, 0V is applied to the memory gate electrode, 0V is applied to the source region, 1.5V is applied to the control gate electrode, and 1.5V is applied to the drain region. At this time, whether it is in the writing state or the erasing state is determined depending on whether or not a current flows.

  In the memory cell transistor MCTR described above, the silicon nitride film CP is left on the upper surface of the control gate electrode CG on the memory gate electrode MG side, so that the control gate electrode CG is formed when the cobalt silicide film MSL is formed. And the memory gate electrode MG can be prevented from being electrically short-circuited, and the operation speed of the flash memory can be improved. This will be described with a comparative example.

  In the semiconductor device according to the comparative example, first, the state shown in FIG. 16 is obtained through the same steps as those shown in FIGS. By patterning a polysilicon film (not shown) or the like, a control gate electrode CGC is formed on the surface of the semiconductor substrate SBC with the gate oxide film GZC interposed. On the upper surface (entire surface) of the control gate electrode CGC, the silicon nitride film CPC is left with the TEOS film TEC interposed.

  An ONO film and a doped polysilicon film (both not shown) are formed so as to cover the control gate electrode CG and the like. Using the photoresist pattern PR1C as a mask, the doped polysilicon film portion and the ONO film portion located on one side wall of the control gate electrode CG are removed. A memory gate electrode MGC is formed on the other side wall of the control gate electrode by the portion of the doped polysilicon film left with the ONO film TZC interposed.

  Next, as shown in FIG. 17, a memory drain region MDRC is formed by implanting impurities of a predetermined conductivity type using the photoresist pattern PR4C as a mask. Thereafter, photoresist pattern PR4C is removed. Next, a memory source region MSRC (see FIG. 18) is formed by implanting impurities of a predetermined conductivity type using the memory gate electrode MGC or the like as a mask. Next, an insulating film (not shown) such as an oxide film is formed so as to cover the control gate electrode CGC, the memory gate electrode MGC, and the like, and the entire surface of the insulating film is subjected to anisotropic etching to thereby control the control gate. Sidewall insulating films SWZC (see FIG. 18) are formed on the side walls of the electrode CGC and the memory gate electrode MGC.

  Next, a cobalt film (not shown) is formed so as to cover the exposed portion of the semiconductor substrate SB, the memory gate electrode MGC, the control gate electrode CGC, and the like. Next, by performing a heat treatment at a predetermined temperature, the silicon in the polysilicon film of the control gate electrode CGC reacts with cobalt, and the silicon of the semiconductor substrate SBC reacts with cobalt to react with cobalt silicide. A film MSLC (see FIG. 18) is formed. Thereafter, the unreacted cobalt film is removed, thereby exposing the cobalt silicide film MSLC as shown in FIG. Thus, the main part of the memory cell transistor of the semiconductor device according to the comparative example is formed.

  In the memory cell transistor of the semiconductor device according to the comparative example, since the silicon nitride film CPC is left so as to cover the entire upper surface of the control gate electrode CGC, no cobalt silicide film is formed on the upper surface of the control gate electrode CGC. . For this reason, in the memory cell transistor adopting the SINCAP structure, the operation speed of the memory cell transistor is affected.

  On the other hand, if the silicon nitride film CPC covering the upper surface of the control gate electrode CGC is eliminated, the cobalt silicide formed on the control gate electrode CPC and the cobalt silicide formed on the memory gate electrode MGC are formed when forming cobalt silicide. Will be connected to each other, resulting in an electrical short circuit.

  On the other hand, in the semiconductor device described above, the silicon nitride film CP located on the memory gate electrode MG side remains in the silicon nitride film CP covering the entire upper surface of the control gate electrode CG, so that the memory gate electrode A portion of the silicon nitride film CP located on the side opposite to the MG side is removed.

  Thereby, when the cobalt silicide film MSL is formed, the connection of the cobalt silicide film is prevented by the remaining silicon nitride film CP, and the control gate electrode CG and the memory gate electrode MG are electrically connected. It is possible to prevent short circuit. Then, a cobalt silicide film MSL is formed on the upper surface portion of the control gate electrode CG from which the silicon nitride film CP has been removed, and the resistance value of the control gate electrode CG can be lowered.

  As a result, even in the case of a memory cell transistor adopting a SINCAP structure as a memory cell transistor of the flash memory, the operation of the flash memory while preventing the control gate electrode CG and the memory gate electrode MG from being electrically short-circuited. Speed can be improved. In addition, a breakdown voltage between the control gate electrode CG and the memory gate electrode MG can be ensured.

Embodiment 2
In the above-described semiconductor device, the case where the silicon nitride film on the control gate electrode is removed by applying the photoresist pattern when forming the memory drain region and the like has been described. Here, a case will be described in which the silicon nitride film is removed by applying a photoresist pattern for forming an element formed in the peripheral circuit region.

  2 and 3, the control gate electrode CG is patterned in the memory cell transistor region TRR in which the memory cell transistors in the memory cell region MCR are formed, as shown in FIG. The In the region MCNR where the contact portion is formed in the memory cell region MCR, it is made of the same layer as the polysilicon film forming the control gate electrode CG, and the pattern of the polysilicon film TS1 serving as the contact portion is formed.

  On the other hand, in the region CAR in which the capacitor is formed in the peripheral circuit region PER, the pattern of the polysilicon film TS2 which is made of the same layer as the polysilicon film forming the control gate electrode CG and which is one electrode ER of the capacitor is formed. In the region PCNR in which the contact portion is formed in the peripheral circuit region PER, it is made of the same layer as the polysilicon film forming the control gate electrode CG, and the pattern of the polysilicon film TS3 serving as the contact portion is formed. On the upper surface of the control gate electrode CG, the silicon nitride film CP is left with the TEOS film TE interposed therebetween. Further, the silicon nitride film CP is also left on the upper surface of the pattern of the polysilicon films TS1, TS2, and TS3 with the TEOS film TE interposed therebetween. The TEOS films TE are all films made of the same layer, and the silicon nitride films CP are all films made of the same layer.

  Next, as shown in FIG. 20, it is left on the upper surface of the control gate electrode CG as a resist pattern for removing the silicon nitride film CP left on the upper surface of the pattern of the polysilicon films TS1, TS2, and TS3. A photoresist pattern PR5 partially covering the silicon nitride film CP is formed. Next, the exposed silicon nitride film CP is removed by performing an etching process using the photoresist pattern PR5 as a mask. Then, the exposed TEOS film TE is removed by removing the silicon nitride film. Thereafter, the photoresist pattern PR5 is removed.

  Next, as shown in FIG. 20, an ONO film TZ is formed so as to cover the patterns of the control gate electrode CG and the polysilicon films TS1, TS2, and TS3. Next, a doped polysilicon film DTS is formed so as to cover the ONO film TZ. Next, as shown in FIG. 22, a photoresist pattern PR6 for patterning the portion of the doped polysilicon film DTS that covers the polysilicon film TS2 serving as one electrode of the capacitor as the other electrode is formed.

  Next, by performing an etching process using the photoresist pattern PR6 as a mask, as shown in FIG. 23, a portion of the doped polysilicon film DTS located on the side wall of the control gate electrode CG (sidewall doped polysilicon) Film SWD), portions located on the sidewalls of the polysilicon films TS1, TS3 (sidewall-doped polysilicon film SWD) and portions covering the polysilicon film TS2 (doped polysilicon film DTS1), leaving other portions Removed. Thereafter, the photoresist pattern PR6 is removed.

  Next, as shown in FIG. 24, the portion of the doped polysilicon film DTS left on one side wall of the doped polysilicon film DTS left on both side walls of the control gate electrode CG is used as the memory gate electrode. A photoresist pattern PR7 is formed for leaving the portion of the doped polysilicon film covering the polysilicon film TS2 as the other electrode.

  Next, an exposed portion of the doped polysilicon film DTS is removed by performing an etching process using the photoresist pattern PR7 as a mask. Thereafter, the photoresist pattern PR7 is removed. Thereafter, in the same manner as described above, a memory drain region MDR and a memory source region MSR are formed in the memory cell transistor region TRR by implanting impurities of a predetermined conductivity type (see FIG. 25).

  Next, an insulating film (not shown) such as an oxide film is formed so as to cover the control gate electrode CG, the memory gate electrode MG, etc., and anisotropic etching is performed on the entire surface of the insulating film, thereby forming FIG. As shown in FIG. 18, sidewall insulating films SWZ (see FIG. 18) are formed on the sidewalls of the control gate electrode CG and the memory gate electrode MG. At this time, the side wall insulating film SWZ is also formed on the side wall of the pattern of the polysilicon film TS1 serving as the contact portion. In the peripheral circuit region PER, the sidewall insulating film SWZ is formed on the sidewall of the capacitor, and the sidewall insulating film SWZ is also formed on the sidewall of the pattern of the polysilicon film TS3 serving as the contact portion.

  Next, a cobalt film (not shown) is formed so as to cover the exposed portion of the semiconductor substrate SB, the memory gate electrode MG, the control gate electrode CG, and the like. Next, by performing heat treatment at a predetermined temperature, the silicon in the polysilicon film of the control gate electrode CG reacts with cobalt, and the silicon of the semiconductor substrate SB reacts with cobalt to form cobalt silicide. A film MSL is formed (see FIG. 26). Thereafter, the unreacted cobalt film is removed to expose the cobalt silicide film MSL as shown in FIG.

  At this time, the cobalt silicide film MSL is also formed on the upper surface of the polysilicon film TS1 serving as a contact portion. Further, in the peripheral circuit region PER, a cobalt silicide film MSL is formed on the upper surface of the doped polysilicon film DTS1 that becomes the other electrode of the capacitor, and a cobalt silicide film MSL is also formed on the upper surface of the polysilicon film TS3 that becomes the contact portion. Is done. In the step of forming the cobalt silicide film, as already described, it is possible to prevent the cobalt silicide film from being connected by the portion of the silicon nitride film CP remaining on the control gate electrode CG.

  Thereafter, the main part of the semiconductor device is formed through steps similar to those shown in FIGS. The structure of the memory cell transistor and the contact portion in the memory cell region MCR is as described with reference to FIGS. Here, the structure of the capacitor in the peripheral circuit region and the contact portion of the capacitor will be briefly described.

  As shown in FIG. 27, FIG. 28 and FIG. 29, in the capacitor in the peripheral circuit region, a capacitor including an electrode formed from the polysilicon film TS1, an electrode formed from the ONO film TZ and the doped polysilicon film DTS1 is formed. Has been. The electrode formed from the polysilicon film TS1 is electrically connected to the wiring MC1 through the metal plug PLC1. The electrode formed from the doped polysilicon film DTS1 is electrically connected to the wiring KC2 through the metal plug PLC2. Note that the cross-sectional structures of the regions PCNR shown in FIGS. 19 to 26 correspond to the cross-sectional line XXVI (PCNR) -XXVI (PCNR) shown in FIG.

  In the semiconductor device described above, when the capacitor and the contact portion are formed in the peripheral circuit region, a photoresist pattern for removing the silicon nitride film CP is used as one of the silicon nitride films CP located on the upper surface of the control gate electrode CG. A photoresist pattern PR3 that also exposes the portion is formed. Thereby, a part of the upper surface of the control gate electrode CG can be exposed without adding a new photomask, and the cobalt silicide film MSL can be formed on the exposed upper surface of the control gate electrode CG.

  On the other hand, the silicon nitride film CP left on the upper surface of the control gate electrode CG can prevent the control gate electrode CG and the memory gate electrode MG from being electrically short-circuited as described above. In addition, a breakdown voltage between the control gate electrode CG and the memory gate electrode MG can be ensured.

Embodiment 3
In the first embodiment, it is stated that the surface of the semiconductor substrate may be etched (penetrated) when part of the silicon nitride film located on the upper surface of the control gate electrode is removed. It has been described that the oxide film formed on the surface of the semiconductor substrate by the side wall oxidation contributes to the prevention of the penetration. Here, a method for more effectively preventing the penetration will be described.

  A photoresist pattern PR1 exposing a part of the silicon nitride film CP located on the upper surface of the control gate electrode CG is formed through the same steps as those shown in FIGS. Is done. Next, a memory drain region MDR is formed by implanting impurities of a predetermined conductivity type using the photoresist pattern PR1 as a mask.

  Next, as shown in FIG. 31, an organic antireflection film ARB is formed by coating so as to cover the photoresist pattern PR1 and the surface of the semiconductor substrate SB. At this time, the organic antireflection film ARB is applied and formed so that the film thickness (film thickness A) of the organic antireflection film ARB covering the surface of the semiconductor substrate SB (memory drain region MDR) is silicon nitride. It becomes thicker than the film thickness (film thickness B) of the organic antireflection film ARB covering the surface of the film CP.

  Next, as shown in FIG. 32, the entire surface of the organic antireflection film ARB is etched to expose the surface of the silicon nitride film CP. At this time, since the film thickness A is thicker than the film thickness B, the surface of the semiconductor substrate SB (memory drain region MDR) is covered with the organic antireflection film ARB.

  Next, the exposed silicon nitride film CP is removed by performing an etching process using the photoresist pattern PR1 and the organic antireflection film ARB as a mask. At this time, since the surface of the semiconductor substrate SB (memory drain region MDR) is covered with the organic antireflection film ARB, the memory drain region MDR can be reliably prevented from penetrating. Thereafter, the organic antireflection film ARB and the photoresist pattern PR1 are removed.

  Next, through a process similar to the process shown in FIG. 11, a cobalt silicide film (not shown) is formed on the exposed surface of the control gate electrode CG, the surface of the memory gate electrode MG, and the like. Thereafter, the main part of the semiconductor device is formed through a process similar to the process shown in FIG.

  In the semiconductor device described above, the following effects are obtained in addition to the effects described in the first embodiment. That is, when removing a part of the silicon nitride film CP located on the upper surface of the control gate electrode CG, the surface of the semiconductor substrate SB (memory drain region MDR) is covered with the organic antireflection film ARB. Thereby, it is possible to reliably prevent the memory drain region MDR from penetrating through the etching process. As a result, the operation of the memory cell transistor can be stabilized.

  Although the organic antireflection film ARB has been described as an example of the film for protecting the surface of the semiconductor substrate when the silicon nitride film is etched, the present invention is not limited to the organic antireflection film, and other coating systems may be used. You may apply the film | membrane of. In the above-described manufacturing method of each semiconductor device, the cobalt silicide film has been described as an example of the metal silicide film. However, the present invention is not limited to the cobalt silicide film, and other metal silicide films may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  SB semiconductor substrate, MCR memory cell region, TRR memory cell transistor region, PER peripheral circuit region, CAR capacitor region, PCNR contact region, PE capacitor, WLD word line direction, SLD direction orthogonal to word line, GZ gate oxide film, CG Control gate electrode, TZ ONO film, MG memory gate electrode, MSR memory source region, SR source region, MDR memory drain region, DR drain region, MCTR memory cell transistor, TB trench isolation insulating film, TS polysilicon film, TS1 polysilicon Film, TS2 polysilicon film, TS3 polysilicon film, TE TEOS film, CP silicon nitride film, DTS doped polysilicon film, DTS1 doped polysilicon film, SWD sidewall Doped polysilicon film, SWZ sidewall insulating film, MSL cobalt silicide film, SZ1 first interlayer insulating film, CH contact hole, PLA, PLB, PLC metal plug, ZF insulating film, MA, MB, MC wiring, PR1, PR2 , PR3, PR4, PR5 Photoresist pattern, ARB Organic antireflection film.

Claims (6)

Forming a conductor portion including a control gate electrode on the surface of a predetermined region of the semiconductor substrate, the first coating film for preventing silicidation covering the upper surface;
Forming a memory gate electrode on a side wall located on one side of a gate length direction intersecting a direction in which the control gate electrode extends among both side walls of the control gate electrode;
Of the first coating film that covers the upper surface of the control gate electrode, covers the first portion of the first coating film that extends from the middle position in the gate length direction to the one side, and the gate length Forming a photoresist pattern that exposes the second portion of the first coating film extending from the middle position in the direction to the other side opposite to the one side;
Performing an etching process using the photoresist pattern as a mask, removing the second portion leaving the first portion of the first coating film, and exposing the upper surface of the control gate electrode;
And a step of forming a metal silicide film on a predetermined surface including the exposed upper surface of the control gate electrode and the surface of the memory gate electrode. The step of forming the memory gate electrode includes a step of forming a sidewall-like conductive film on the both side walls of the control gate electrode,
The step of forming the photoresist pattern covers a sidewall-like conductive film located on the one side wall among the sidewall-like conductive films formed on the both side walls of the control gate electrode. Including the step of forming
The step of forming the memory gate electrode is performed by performing an etching process using the photoresist pattern as a mask to remove the sidewall-like conductive film located on the other side wall, and on the one side wall. The method of manufacturing a semiconductor device according to claim 1, comprising a step of using the side wall-like conductive film positioned as the memory gate electrode. After the photoresist pattern is formed, a predetermined material is applied so as to cover the surface of the photoresist pattern, the second portion of the first coating film, and a predetermined region of the semiconductor substrate. 2 forming a coating film;
A step of removing a portion of the second coating film that covers the second portion of the first coating film,
The step of exposing the upper surface of the control gate electrode includes the step of exposing the second portion of the exposed first coating film in a state where a surface of a predetermined region of the semiconductor substrate is covered with the second coating film. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed.   The method of manufacturing a semiconductor device according to claim 3, wherein the second coating film includes an organic antireflection film. The step of forming the conductor portion includes
Forming a first electrode of a capacitor comprising the same layer as the control gate electrode, wherein a third coating film comprising the same layer as the first coating film covers the upper surface;
Forming a contact portion made of the same layer as the control gate electrode, wherein a fourth coating film made of the same layer as the first coating film covers an upper surface,
The step of forming the photoresist pattern includes the step of forming the photoresist pattern so as to expose the third coating film located on the upper surface of the first electrode and the fourth coating film of the contact portion. Including
Exposing the upper surface of the control gate electrode includes removing the third coating film and the fourth coating film;
Covering the upper surface of the control gate electrode, the first electrode, and the contact portion exposed by removing the second portion, the third coating film, and the fourth coating film of the first coating film A step of forming a conductive film with a predetermined insulating film interposed therebetween,
Forming another photoresist pattern so as to cover a portion of the conductive film covering the first electrode, and to expose a portion covering the control gate electrode and a portion covering the contact portion;
Etching is performed on the conductive film using the other photoresist pattern as a mask to form a portion of the conductive film covering the first electrode as a second electrode of the capacitor, and on both sides of the control gate electrode Forming a sidewall-like conductive film on the wall,
The step of forming the memory gate electrode includes removing the side wall-like conductive film located on the other side wall from the side wall-like conductive films located on both side walls of the control gate electrode. A step of using the sidewall-like conductive film located on the one side wall as the control gate electrode,
The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the metal silicide film includes a step of forming the metal silicide film on a surface of the second electrode and a surface of the contact portion.   The method of manufacturing a semiconductor device according to claim 1, wherein the metal silicide film includes a cobalt silicide film.

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