JP2013243276A - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that allows downsizing the semiconductor device and simultaneously forming a plurality of resistance elements having different resistance values, and to provide the semiconductor device manufactured by the method.SOLUTION: A method of manufacturing a semiconductor device includes: a step of forming, on a substrate, a resist having a first opening and a second opening having a narrower width than the first opening; a spatter deposition step of simultaneously forming, by spatter deposition, a first resistance element and a second resistance element in a portion exposed by the first opening and a portion exposed by the second opening of the substrate, respectively; a step of removing the resist after the spatter deposition step; and a step of forming metal layers on both sides of the first resistance element and on both sides of the second resistance element after the removal of the resist. The second resistance element has a narrower width than the first resistance element, and the second resistance element has a thinner film thickness than the first resistance element.

Description

  The present invention relates to a method for manufacturing a semiconductor device having a resistance element used for an analog integrated circuit, for example, and a semiconductor device manufactured by the manufacturing method.

  Patent Document 1 discloses a semiconductor device having a thin film resistance element. This semiconductor device uses a tungsten silicide film formed on an insulating film as a thin film resistance element. The tungsten silicide film is processed into a desired shape to obtain a desired resistance value. Photolithography and etching are used for processing the tungsten silicide film.

JP 63-272064 A

  In the semiconductor device disclosed in Patent Document 1, when a resistive element having a high resistance value is formed on a substrate, it is necessary to increase the length of the resistive element. Therefore, there is a problem that the resistance element occupies a large area of the substrate and the semiconductor device cannot be reduced in size.

  In order to form a high-resistance resistance element with a small area, it is conceivable to form the resistance element using a material different from that of the low-resistance resistance element. In this case, the number of steps for forming the resistance element is increased, and there is a problem that the cost is increased.

  The present invention has been made to solve the above-described problems, and provides a semiconductor device manufacturing method and a semiconductor device in which a semiconductor device can be miniaturized and a plurality of resistance elements having different resistance values can be simultaneously formed. For the purpose.

  In the method of manufacturing a semiconductor device according to the present invention, a step of forming a resist having a first opening and a second opening having a narrower width than the first opening on the substrate, and the first opening of the substrate are exposed. A sputter film forming step in which the first resistance element and the second resistance element are simultaneously formed on the portion and the portion exposed by the second opening by sputter film formation; and a step of removing the resist after the sputter film formation step; And a step of forming metal layers on both ends of the first resistance element and on both ends of the second resistance element after removing the resist, the second resistance element having a width wider than that of the first resistance element. The second resistance element is narrow and has a thickness smaller than that of the first resistance element.

  In another method of manufacturing a semiconductor device according to the present invention, a step of forming a resist having a first opening and a second opening having a width narrower than the first opening on a substrate, and a gas atmosphere containing nitrogen, By reactive sputtering film formation using any one of Ta, Cr, TaSi, or WSi as a sputtering target, the first exposed portion and the second exposed portion of the substrate are exposed to the first opening, respectively. A reactive sputter film forming step of simultaneously forming the resistance element and the second resistance element; and a step of removing the resist after the reactive sputter film formation step, wherein the second resistance element is the first resistance element It is characterized by a higher nitridation rate.

  A semiconductor device according to the present invention includes a substrate, a first resistance element formed on the substrate by nitriding any one of Ta, Cr, TaSi, or WSi, and the first resistance element A second resistance element having a width narrower than that of the first resistance element, which is formed on the substrate with a material having a higher nitridation rate than the first resistance element. It is provided with.

  According to the present invention, the semiconductor device can be downsized and a plurality of resistance elements having different resistance values can be formed simultaneously.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing in the 2-2 line of FIG. It is sectional drawing after forming the patterned resist. It is sectional drawing after sputtering film-forming. It is a graph which shows the relationship between the line width of a resistive element, and a film thickness. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the 7-7 line | wire of FIG. It is sectional drawing after forming the patterned resist. It is sectional drawing after reactive sputter film-forming. It is a graph which shows the relationship between the sheet resistance and line width of TaN formed into a film by reactive sputtering. It is a graph which shows the relationship between the relative film thickness and line width of TaN formed into a film by reactive sputtering. It is a top view of the semiconductor device which concerns on Embodiment 3 of this invention. It is a graph which shows the relationship between the resistivity of a resistive element, and a resistance temperature coefficient.

Embodiment 1 FIG.
FIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device includes a substrate 10 made of a compound semiconductor such as GaAs. A first resistance element 12 is formed of NiCr on the substrate 10. The first resistance element 12 has a width X1 and a length Y1. Metal layers 14 and 16 are formed on both ends of the first resistance element 12.

  A second resistance element 22 is formed of NiCr on the substrate 10. The second resistance element 22 has a width X2 and a length Y2. The second resistance element 22 is formed narrower and longer than the first resistance element 12 so that the resistance value is higher than that of the first resistance element 12. The width X2 of the second resistance element 22 is about 2 μm. Metal layers 24 and 26 are formed on both ends of the second resistance element 22. The first resistance element 12, the second resistance element 22, and the metal layers 14, 16, 24, and 26 are covered with a passivation film 30. 2 is a cross-sectional view taken along line 2-2 of FIG. The second resistance element 22 is thinner than the first resistance element 12.

  A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. First, a patterned resist is formed on the substrate 10. FIG. 3 is a cross-sectional view after the patterned resist is formed. The resist 50 is patterned to form a first opening 50a and a second opening 50b narrower than the first opening 50a in the resist 50. The film thickness of the resist 50 is desirably 1.0 μm or more.

  Next, sputtering film formation is performed. FIG. 4 is a cross-sectional view after sputtering film formation. In this step, the first resistance element 12 and the second resistance element 22 are simultaneously formed in the portion exposed by the first opening 50a and the portion exposed by the second opening 50b of the substrate 10 by sputtering of NiCr. This process is called a sputter film forming process.

  The resist 50 is removed after the sputter film forming step. Thereby, the NiCr layer 52 formed on the resist 50 is lifted off. After the resist 50 is removed, metal layers 14 and 16 serving as wirings are formed on both ends of the first resistance element 12. At the same time, metal layers 24 and 26 to be wirings are formed on both ends of the second resistance element 22. Finally, the passivation film 30 is formed by the CVD method, thereby completing the semiconductor device shown in FIG.

  By the way, sputter film formation is a film formation method in which metal particles are isotropically incident on a substrate. Therefore, it is possible to form a film having isotropic properties. In isotropic film formation, the opening width of the resist (the line width of the resistance element, the same applies hereinafter) is made narrow so that the metal particles incident obliquely to the substrate collide with the resist and the metal particles reaching the substrate The number can be reduced. On the other hand, when the opening width of the resist is wide, many metal particles incident obliquely with respect to the substrate can reach the substrate.

  Therefore, the film thickness of the resistance element formed in a place where the resist opening width is narrow can be made thinner than the film thickness of the resistance element formed in a place where the resist opening width is wide. That is, it is possible to increase the thickness of the resistor element having a large line width and reduce the thickness of the resistor element having a small line width.

  In the method for manufacturing a semiconductor device according to the first embodiment of the present invention, since the resistance element is formed by sputtering film formation, the thickness of the resistance element can be freely controlled by changing the opening width of the resist. Specifically, since the film thickness of the second resistance element 22 can be made thinner than the film thickness of the first resistance element 12, it is possible to increase the resistance without forming the second resistance element 22 longer. Thereby, the semiconductor device can be miniaturized.

  Further, as the resist film thickness is increased, the number of metal particles that reach the substrate during the sputtering film formation can be reduced. In Embodiment 1 of the present invention, since the film thickness of the resist 50 is 1.0 μm or more, the second resistance element 22 having a line width of 2 μm can be formed sufficiently thin. In addition, when it is desired to form the second resistance element 22 further thinly without changing the line width, the resist 50 may be thickened.

  FIG. 5 is a graph showing the relationship between the line width and film thickness of the resistance element. As the film thickness, a relative film thickness normalized with the film thickness when the line width is 50 μm as 1 is shown. When the resistance element is formed by sputtering film formation, the film thickness decreases as the line width of the resistance element decreases. On the other hand, when the resistance element is formed by vapor deposition that is not isotropic, the correlation between the line width and the film thickness of the resistance element is low. Therefore, it is necessary to employ sputter deposition as the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

  According to the method of manufacturing a semiconductor device according to the first embodiment of the present invention, the first resistance element 12 and the second resistance element 22 are formed at the same time in one sputter film formation step. Compared to the case where the two-resistance element 22 is formed in a separate process, the cost is low. Moreover, since the 1st resistive element 2 and the 2nd resistive element 22 can be formed with the same material, it is low-cost compared with the case where a several material is used.

  In the sputter deposition process, NiCr is sputter deposited, but other metal materials may be used. The dimensions of the first resistance element 12 and the second resistance element 22 and the film thickness of the resist 50 are not particularly limited to the above values. The substrate 10 may be formed of a material other than the compound semiconductor. On the substrate 10, not only the resistance element but also other elements may be formed. For example, when a matching circuit is formed on the substrate 10, a transistor, a capacitor, an inductor, and the like are formed in addition to the resistance element.

Embodiment 2. FIG.
FIG. 6 is a plan view of the semiconductor device according to the second embodiment of the present invention. The description will focus on the differences from the first embodiment. The first resistance element 100 is made of TaN. The second resistance element 102 is also made of TaN. The second resistance element 102 has a higher nitridation rate than the first resistance element 100.

  7 is a cross-sectional view taken along line 7-7 in FIG. The second resistance element 102 is formed to be narrower than the first resistance element 100. The film thicknesses of the first resistance element 100 and the second resistance element 102 are substantially the same.

  Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, a patterned resist is formed on a substrate. FIG. 8 is a cross-sectional view after the patterned resist is formed. The resist 50 is patterned to form a first opening 50a and a second opening 50b narrower than the first opening 50a in the resist 50.

  Next, reactive sputtering film formation is performed. In this step, reactive sputtering film formation using Ta as a sputtering target is performed in a gas atmosphere containing nitrogen. By this reactive sputtering film formation, the first resistance element 100 and the second resistance element 102 are simultaneously formed in the portion exposed by the first opening 50a and the portion exposed by the second opening 50b of the substrate 10, respectively. The substance that collides with the sputtering target is not particularly limited, but, for example, argon is used. This process is referred to as a reactive sputter film forming process. FIG. 9 is a cross-sectional view after reactive sputter deposition.

  The resist 50 is removed after the reactive sputter deposition process. After removing the resist 50, metal layers 14 and 16 are formed on both ends of the first resistance element 100, and metal layers 24 and 26 are formed on both ends of the second resistance element 102. Finally, a passivation film 30 is formed by CVD, thereby completing the semiconductor device shown in FIG.

  When TaN is formed by reactive sputtering, the nitridation rate of the formed Ta depends on the opening width of the resist 50. Specifically, the nitridation rate of Ta increases as the opening width of the resist 50 becomes narrower. This is because nitrogen molecules are present at equal density at each location on the substrate, and the amount of Ta supplied is reduced at locations where the resist opening width is narrow, so the nitriding rate of Ta increases at this location. It is done.

  FIG. 10 is a graph showing the relationship between the sheet resistance and the line width of TaN formed by reactive sputtering. From this figure, it can be seen that the sheet resistance increases as the line width decreases. FIG. 11 is a graph showing the relationship between the relative film thickness and the line width of TaN deposited by reactive sputtering. From this figure, it can be seen that the film thickness is almost constant even if the line width changes. From the data of FIGS. 10 and 11, it can be seen that the sheet resistance increases as the line width decreases, not because the film thickness decreases, but because the nitriding rate of Ta increases.

  As described above, in the second embodiment of the present invention, since the line width of the second resistance element 102 is formed narrower than the line width of the first resistance element 100, the nitridation rate of the second resistance element 102 is set to the first resistance element 100. The nitridation rate can be higher. Therefore, the second resistance element 102 can be increased in resistance without increasing the length. Thereby, the semiconductor device can be miniaturized. In addition, since the first resistance element 100 and the second resistance element 102 are formed simultaneously in one reactive sputtering film forming step, a semiconductor device can be manufactured at low cost.

  The second embodiment of the present invention is characterized in that a resistance element is formed by reactive sputtering film formation on a substrate exposed in a resist opening. Various modifications are possible as long as this characteristic is not lost. For example, the material of the resistance elements 100 and 102 is not limited to TaN. The first resistance element 100 only needs to be formed on the substrate 10 by nitriding any one of Ta, Cr, TaSi, and WSi. The second resistance element 102 is formed by nitriding the same resistance material as the first resistance element 100 and formed on the substrate 10 with a material having a higher nitriding rate than the first resistance element 100. That's fine. In this case, any one of Ta, Cr, TaSi, or WSi is a sputtering target. In addition, at least the same deformation as that of the first embodiment is possible.

Embodiment 3 FIG.
FIG. 12 is a plan view of the semiconductor device according to the third embodiment of the present invention. The difference from the second embodiment will be mainly described. The first resistance element 150 and the second resistance element 152 are connected to form one resistance element 154. The width X2 of the second resistance element 152 is narrower than the width X1 of the first resistance element 150.

  The first resistance element 150 has a positive resistance temperature coefficient, and the second resistance element 152 has a negative resistance temperature coefficient. In the case of having a positive resistance temperature coefficient, the resistance value increases as the temperature increases, and in the case of a negative resistance temperature coefficient, the resistance value decreases as the temperature increases.

  A first metal layer 156 is formed on a part of the first resistance element 150. A second metal layer 158 is formed on part of the second resistance element 152. The first metal layer 156 and the second metal layer 158 function as wirings at both ends of the resistance element 154. The resistance temperature coefficient of the resistance element 154 is a value between 10 ppm / K and −10 ppm / K.

  A resistance element 166 in which the first resistance element 160 and the second resistance element 162 are connected via the metal layer 164 is formed in parallel with the resistance element 154. The width X4 of the second resistance element 162 is narrower than the width X3 of the first resistance element 160. The first resistance element 160 has a positive resistance temperature coefficient, and the second resistance element 162 has a negative resistance temperature coefficient.

  A first metal layer 168 is formed on a part of the first resistance element 160. A second metal layer 170 is formed on part of the second resistance element 162. The first metal layer 168 and the second metal layer 170 function as wirings at both ends of the resistance element 166. The resistance temperature coefficient of the resistance element 166 is a value between 10 ppm / K and −10 ppm / K.

  In the semiconductor device manufacturing method according to the third embodiment of the present invention, a resistor element is formed by depositing TaN by reactive sputtering, as in the second embodiment. By adjusting the resist opening width, the first resistance elements 150 and 160 having a large width and the second resistance elements 152 and 162 having a small width are formed.

  After the reactive sputter deposition, the resist is removed, and one end of the first resistance element 150 and one end of the second resistance element 152 are formed so that the first resistance element 150 and the second resistance element 152 form one resistance element 154. Metal layers 156 and 158 are formed, respectively. Similarly, metal layers 168 and 170 are formed on one end of the first resistance element 160 and one end of the second resistance element 162 so that the first resistance element 160 and the second resistance element 162 form one resistance element 166. To do. At the same time, a metal layer 164 is also formed.

  Here, it will be described that the first resistance elements 150 and 160 have a positive resistance temperature coefficient, and the second resistance elements 152 and 162 have a negative resistance temperature coefficient. FIG. 13 is a graph showing the relationship between the resistivity of the resistance element and the resistance temperature coefficient. This graph shows a result of forming a plurality of resistance elements having different resistivity by changing the N2 / Ar flow rate ratio in reactive sputtering film formation for forming TaN, and obtaining the resistance temperature coefficient of each resistance element.

  From this graph, a resistive element having a high resistivity of approximately 1.7E-4 [Ω · cm] or more has a negative resistance temperature coefficient, and a resistivity of approximately 1.5E-4 [Ω · cm] or less is low. It can be seen that the resistive element has a positive resistance temperature coefficient. Therefore, by forming a resistance element having a high resistivity and a resistance element having a low resistivity, a resistance element having a negative resistance temperature coefficient and a resistance element having a positive resistance temperature coefficient can be formed. In the third embodiment of the present invention, when a resistance element is formed by reactive sputter deposition, the resistivity can be freely controlled by changing the opening width of the resist. The first resistance elements 150 and 160 and the second resistance elements 152 and 162 having a negative resistance temperature coefficient were formed.

  In general, the resistance value of the resistance element is preferably independent of temperature. Specifically, the resistance temperature coefficient of the resistance element is preferably between 10 ppm / K and −10 ppm / K. However, since the temperature coefficient of resistance of a resistive element formed of a thin film depends greatly on the material, there are problems such as limiting the material of the resistive element or requiring precise control of the material composition in order to satisfy the above conditions. There was a profit.

  However, in the semiconductor device according to the third embodiment of the present invention, a resistance element having a positive resistance temperature coefficient and a resistance element having a negative resistance element are connected directly or via a metal layer, so that the entire resistance element is obtained. The resistance temperature coefficient can be made close to zero. Therefore, it is possible to easily form a resistance element that is stable with respect to temperature without the above disadvantages.

  The semiconductor device manufacturing method and the semiconductor device according to the third embodiment of the present invention can be modified at least as much as the first and second embodiments.

  DESCRIPTION OF SYMBOLS 10 Board | substrate, 12 1st resistance element, 14, 16, 24, 26 Metal layer, 22 2nd resistance element, 30 Passivation film, 50 Resist, 50a, 50b Opening, 100 1st resistance element, 102 2nd resistance element, 150 , 160 First resistance element, 152, 162 Second resistance element, 154, 166 Resistance element

Claims (9)

Forming a resist having a first opening and a second opening having a narrower width than the first opening on the substrate;
A sputter film forming step of simultaneously forming a first resistance element and a second resistance element by sputtering film formation on the portion exposed by the first opening and the portion exposed by the second opening of the substrate, respectively;
Removing the resist after the sputter deposition step;
Forming metal layers on both ends of the first resistance element and on both ends of the second resistance element after removing the resist,
The method of manufacturing a semiconductor device, wherein the second resistance element is narrower than the first resistance element, and the second resistance element is thinner than the first resistance element.   The method of manufacturing a semiconductor device according to claim 1, wherein in the sputtering film forming step, NiCr is formed by sputtering. Forming a resist having a first opening and a second opening having a narrower width than the first opening on the substrate;
By reactive sputtering film formation using any one of Ta, Cr, TaSi or WSi as a sputtering target in a gas atmosphere containing nitrogen, a portion exposed by the first opening of the substrate and the second opening A reactive sputter film forming step of simultaneously forming the first resistance element and the second resistance element on the exposed portions,
Removing the resist after the reactive sputter film forming step,
The method of manufacturing a semiconductor device, wherein the second resistance element has a nitridation rate higher than that of the first resistance element.   The method of manufacturing a semiconductor device according to claim 3, further comprising: forming metal layers on both ends of the first resistance element and on both ends of the second resistance element. Forming a metal layer on one end of the first resistance element and one end of the second resistance element so that the first resistance element and the second resistance element form one resistance element,
The first resistance element has a positive temperature coefficient of resistance;
The method of manufacturing a semiconductor device according to claim 3, wherein the second resistance element has a negative resistance temperature coefficient. A substrate,
A first resistance element formed on the substrate by nitriding any one of Ta, Cr, TaSi, or WSi;
The first resistance element is formed by nitriding the same resistance material as that of the first resistance element, and is formed on the substrate with a material having a higher nitridation rate than the first resistance element. A semiconductor device comprising: a two-resistance element. Metal layers formed on both ends of the first resistance element;
The semiconductor device according to claim 6, further comprising a metal layer formed on both ends of the second resistance element. A first metal layer formed on a part of the first resistance element;
A second metal layer formed on a part of the second resistance element,
The first resistance element has a positive resistance temperature coefficient, the second resistance element has a negative resistance temperature coefficient;
The semiconductor device according to claim 6, wherein the first resistance element and the second resistance element are connected directly or via a metal layer to form one resistance element.   The semiconductor device according to claim 8, wherein the resistance temperature coefficient of the resistance element is a value between 10 ppm / K and −10 ppm / K.

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