JP2013236016A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2013236016A
JP2013236016A JP2012108721A JP2012108721A JP2013236016A JP 2013236016 A JP2013236016 A JP 2013236016A JP 2012108721 A JP2012108721 A JP 2012108721A JP 2012108721 A JP2012108721 A JP 2012108721A JP 2013236016 A JP2013236016 A JP 2013236016A
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semiconductor
support substrate
substrate
semiconductor substrate
adhesive layer
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Akira Hirao
章 平尾
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Fuji Electric Co Ltd
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PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device including a peeling process of a support substrate where the peeling treatment is properly conducted without causing problems even when some of an adhesive layer protrude from a proper adhesion region of the adhesion layer when a semiconductor wafer and the support substrate, which are bonded through the adhesion layer, are separated from each other after required process treatment is done.SOLUTION: A manufacturing method of a semiconductor device includes: a second process where light from an ultraviolet light lamp 10 is radiated to an adhesion layer 3 from the support substrate 2 side and a support substrate 2 is peeled from the semiconductor wafer 1 after process treatment, in which a thickness of a semiconductor wafer 1 is reduced from a rear surface and a required semiconductor element function region is formed on the rear surface, is done; and a third process where the adhesion layer 3 remaining on the semiconductor wafer 1 is peeled and removed in immersion treatment using a peeling liquid.

Description

本発明は、半導体装置の製造方法に関し、特には、基板の厚さを薄くするために、半導体基板の表面に支持基板を貼付して裏面を研削した後、支持基板を剥離するプロセスを好適に含む製造方法の改良に関する。   The present invention relates to a method for manufacturing a semiconductor device, and in particular, in order to reduce the thickness of the substrate, a process of peeling the support substrate after attaching the support substrate to the surface of the semiconductor substrate and grinding the back surface is preferable. It relates to the improvement of the manufacturing method including.

コンピュータや通信機器の主要部分には設計された機能を奏するための電子回路が配設される。この電子回路内には、多数のトランジスタや抵抗などの単機能の電子デバイスが1チップの半導体基板上に集積された、集積回路(以降、IC)が複数搭載されることが多くなってきている。これらのICのうち、単機能電子デバイスとしてパワー半導体装置を含むものをパワーICと称している。そのようなパワー半導体装置の一つに絶縁ゲート型バイポーラトランジスタ(以降、IGBT)が知られている。   An electronic circuit for performing a designed function is disposed in a main part of the computer or communication device. In this electronic circuit, a plurality of integrated circuits (hereinafter referred to as ICs) in which a large number of single-function electronic devices such as transistors and resistors are integrated on a one-chip semiconductor substrate are often mounted. . Among these ICs, those including a power semiconductor device as a single-function electronic device are called power ICs. As one of such power semiconductor devices, an insulated gate bipolar transistor (hereinafter, IGBT) is known.

このIGBTは、MOSFETの高速スイッチング特性および電圧駆動特性と、バイポーラトランジスタの低オン電圧特性とを併有する半導体デバイスであり注目されている。その応用範囲は、汎用インバータ、ACサーボ、無停電電源(UPS)またはスイッチング電源などの産業分野から、電子レンジ、炊飯器またはストロボなどの民生機器分野へと拡大してきている。さらに適用分野の拡大のため、IGBTは、市場からよりいっそうの低損失化を求められている。このIGBTの低損失化や高効率化を図る手段の一つとして、半導体基板の厚さを、設計耐圧が得られる範囲または製造プロセスの許容範囲内で、できる限り薄くする方法がある。   This IGBT is attracting attention because it is a semiconductor device that has both high-speed switching characteristics and voltage drive characteristics of MOSFETs and low on-voltage characteristics of bipolar transistors. The range of applications has expanded from industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), or switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobes. Further, in order to expand application fields, IGBTs are required to further reduce loss from the market. As one means for reducing the loss and increasing the efficiency of the IGBT, there is a method of reducing the thickness of the semiconductor substrate as much as possible within a range where a design withstand voltage can be obtained or within an allowable range of a manufacturing process.

このような半導体基板の厚さをできるかぎり薄くすることに関する従来の方法を以下説明する。一般に半導体基板の厚さを薄くすると、半導体ウエハの機械的強度が低下し、製造プロセスでウエハ割れが多く発生するようになり、ハンドリング(取り扱い)が困難になる。この問題の解決のために、半導体ウエハを薄くした後の機械的強度を補強するために、薄くする前に、予め半導体ウエハを石英ガラス基板などの支持基板に接着し、接着していない側の半導体ウエハ面(裏面)を研削して半導体ウエハを薄化する方法が知られている。この方法について、具体的に説明する。   A conventional method relating to reducing the thickness of the semiconductor substrate as much as possible will be described below. In general, when the thickness of the semiconductor substrate is reduced, the mechanical strength of the semiconductor wafer is reduced, and many wafer cracks occur in the manufacturing process, making handling (handling) difficult. In order to solve this problem, in order to reinforce the mechanical strength after thinning the semiconductor wafer, the semiconductor wafer is bonded to a supporting substrate such as a quartz glass substrate in advance before thinning, A method of thinning a semiconductor wafer by grinding the semiconductor wafer surface (back surface) is known. This method will be specifically described.

図8は、半導体ウエハを薄化する従来の方法を示し、同図(a)から同図(g)は製造工程順に示した半導体ウエハの要部製造工程断面図である。支持基板としては石英ガラス基板51を用いる。この石英ガラス基板51の直径は半導体ウエハ54直径よりも0.1mm〜1mm程度大きい。   FIG. 8 shows a conventional method for thinning a semiconductor wafer, and FIGS. 8A to 8G are sectional views of the principal steps of manufacturing the semiconductor wafer shown in the order of the manufacturing steps. A quartz glass substrate 51 is used as the support substrate. The diameter of the quartz glass substrate 51 is about 0.1 mm to 1 mm larger than the diameter of the semiconductor wafer 54.

半導体ウエハ54の表面側に接着剤53を塗布する(同図(a))。その際、この半導体ウエハ54の表面側にある、図示しない各種拡散層や、表面側電極、制御電極などの表面側機能層の凹凸を保護するために、厚めに接着剤53を塗布する(10μm〜30μm程度)。石英ガラス基板51を半導体ウエハ54に接着剤53を介して同軸に対向させて貼り付ける(同図(b))。熱を加えた状態で圧着61することで半導体ウエハ54と石英ガラス基板51とを固着する(同図(c))。   An adhesive 53 is applied to the surface side of the semiconductor wafer 54 (FIG. 1A). At this time, in order to protect the unevenness of various diffusion layers (not shown) on the surface side of the semiconductor wafer 54 and surface side functional layers such as surface side electrodes and control electrodes, a thick adhesive 53 is applied (10 μm). ˜30 μm). The quartz glass substrate 51 is attached to the semiconductor wafer 54 so as to be coaxially opposed to each other through the adhesive 53 ((b) in the figure). The semiconductor wafer 54 and the quartz glass substrate 51 are fixed to each other by pressing 61 in a state where heat is applied ((c) in the figure).

つぎに、半導体ウエハ54の裏面56(同図(c))をバックグラインド(研削された厚さ57)して薄膜半導体ウエハ58とした後、研削後の薄膜半導体ウエハ58の裏面59をフッ硝酸溶液でスピンエッチングして、研削による加工歪みを除去する。その後、薄膜半導体ウエハ58の裏面59に所要の拡散層(図示せず)と、その拡散層上に裏面側主電極(図示せず)を形成する(同図(d))。   Next, the back surface 56 (FIG. 5C) of the semiconductor wafer 54 is back-ground (the ground thickness 57) to form a thin film semiconductor wafer 58, and then the back surface 59 of the thin film semiconductor wafer 58 after grinding is subjected to hydrofluoric acid. Spin-etch with solution to remove processing distortion caused by grinding. Thereafter, a required diffusion layer (not shown) is formed on the back surface 59 of the thin film semiconductor wafer 58, and a back side main electrode (not shown) is formed on the diffusion layer (FIG. 4D).

つぎに、薄膜半導体ウエハ58の裏面59をUVテープ60(紫外線照射で剥離できる接着テープ)に貼りつける。その後、石英ガラス基板51側から接着剤53の表面にレーザ62を照射して、石英ガラス基板51と接着剤53の接着力を弱める(同図(e))。石英ガラス基板51を外す。薄膜半導体ウエハ58上に残留した接着剤53を有機系の薬品にて除去する(同図(f))。その後、薄膜半導体ウエハ58を一点鎖線64で示す箇所(スクライブライン)で切断する(同図(g))(特許文献1)。   Next, the back surface 59 of the thin film semiconductor wafer 58 is attached to a UV tape 60 (an adhesive tape that can be peeled off by ultraviolet irradiation). After that, the surface of the adhesive 53 is irradiated with a laser 62 from the quartz glass substrate 51 side to weaken the adhesive force between the quartz glass substrate 51 and the adhesive 53 ((e) in the figure). The quartz glass substrate 51 is removed. The adhesive 53 remaining on the thin film semiconductor wafer 58 is removed with an organic chemical (FIG. 5F). Thereafter, the thin film semiconductor wafer 58 is cut at a portion (scribe line) indicated by a one-dot chain line 64 ((g) in the figure) (Patent Document 1).

また、別の文献には、半導体ウエハの表面に半導体素子の表面側素子構造部を作製する。表面側素子構造部が形成された面に支持基板を接着する。半導体ウエハ裏面の研削を行い基板厚さを薄くする。半導体ウエハ裏面に機能領域を形成する。接着層に紫外線を照射して半導体ウエハから支持基板を剥離させる。このようにして半導体ウエハを薄くするプロセスを行って半導体ウエハ割れを防ぐことのできる方法についての記載がある(特許文献2)。半導体基板に半導体ウエハを接着するための接着剤の粘着強度を、剥離時に低下させるために紫外線照射する際に、紫外線の光源に紫外線ランプを用いることが開示されている文献もある(特許文献3)。また、半導体ウエハと支持基板とを接着する接着剤が半導体ウエハの外周部にはみ出す状況の記載がある(特許文献4)。   In another document, a surface element structure portion of a semiconductor element is formed on the surface of a semiconductor wafer. A support substrate is bonded to the surface on which the surface-side element structure portion is formed. Grind the backside of the semiconductor wafer to reduce the substrate thickness. A functional region is formed on the back surface of the semiconductor wafer. The support substrate is peeled from the semiconductor wafer by irradiating the adhesive layer with ultraviolet rays. There is a description of a method capable of preventing the semiconductor wafer from cracking by performing the process of thinning the semiconductor wafer in this way (Patent Document 2). There is also a document disclosing use of an ultraviolet lamp as an ultraviolet light source when irradiating with ultraviolet light in order to reduce the adhesive strength of an adhesive for bonding a semiconductor wafer to a semiconductor substrate at the time of peeling (Patent Document 3). ). In addition, there is a description of a situation in which an adhesive that bonds the semiconductor wafer and the support substrate protrudes to the outer periphery of the semiconductor wafer (Patent Document 4).

特開2005−129653号公報(図8)Japanese Patent Laying-Open No. 2005-129653 (FIG. 8) 特開2004−140101号公報(要約)JP 2004-140101 A (summary) 特開2005−150453号公報(要約)JP 2005-150453 A (summary) 特開2005−114306号公報(図2、0013段落)JP 2005-114306 A (FIG. 2, paragraph 0013)

前記特許文献1に記載の方法は、半導体ウエハ54と支持基板51とを、一旦、接着剤53を介して接合し裏面研削および所要のプロセス処理を半導体ウエハ54の露出面に施した後、半導体ウエハ54から支持基板51を剥がすために、透明な支持基板51側からUVレーザまたは赤外レーザ光を照射して接着剤53の接合を弱める方式である。しかしながら、このレーザ方式の場合、光の照射領域の範囲が狭いので、レーザ光を走査して照射範囲をひろげて接着剤の塗膜全体に照射する必要がある。半導体ウエハと支持基板に挟まれた平坦な接着剤塗膜の領域へのレーザ光の走査により、照射した平坦な範囲の塗膜領域のみの接着剤の粘着性が低下して剥がし易くなるにすぎない。従って、図9に示すように、半導体ウエハ54と支持基板51とを圧着により貼り合わせる場合、接着剤53が半導体ウエハ54や支持基板51の側面にはみ出した状態のはみ出し塗膜40が形成されるが、このはみ出し塗膜40は平坦な接着剤塗膜の延長上には無いので、はみ出た接着剤の面にはレーザ照射が適切に行われず、半導体ウエハから支持基板が剥がれ難いといった問題が生じることがある。   In the method described in Patent Document 1, the semiconductor wafer 54 and the support substrate 51 are once bonded together via an adhesive 53, and backside grinding and necessary process processing are performed on the exposed surface of the semiconductor wafer 54. In order to peel off the support substrate 51 from the wafer 54, a UV laser or infrared laser light is irradiated from the transparent support substrate 51 side to weaken the bonding of the adhesive 53. However, in the case of this laser system, since the range of the light irradiation region is narrow, it is necessary to scan the laser beam to widen the irradiation range and irradiate the entire adhesive coating film. Laser scanning of the flat adhesive coating area sandwiched between the semiconductor wafer and the support substrate only reduces the adhesive tackiness of the irradiated flat area and makes it easy to peel off. Absent. Therefore, as shown in FIG. 9, when the semiconductor wafer 54 and the support substrate 51 are bonded together by pressure bonding, the protruding coating film 40 in a state where the adhesive 53 protrudes from the side surfaces of the semiconductor wafer 54 and the support substrate 51 is formed. However, since the protruding coating 40 is not on the extension of the flat adhesive coating, the surface of the protruding adhesive is not properly irradiated with laser, and there is a problem that the support substrate is difficult to peel off from the semiconductor wafer. Sometimes.

本発明は、前述のような問題点を考慮してなされたものであり、本発明の目的は、接着層を介して貼付された半導体ウエハと支持基板を、所要のプロセス処理後に、半導体ウエハと支持基板を相互に分離する際に、接着層の適正な接着領域からはみ出した接着層があっても、支障なく適正に剥離処理を行うことができる支持基板の剥離工程を含む半導体装置の製造方法を提供することである。   The present invention has been made in consideration of the above-described problems, and an object of the present invention is to provide a semiconductor wafer and a supporting substrate attached via an adhesive layer, a semiconductor wafer, A method for manufacturing a semiconductor device including a support substrate peeling process capable of appropriately performing a peeling process without any trouble even when there is an adhesive layer protruding from an appropriate adhesion region of the adhesive layer when the support substrates are separated from each other Is to provide.

前述した発明の目的を達成するために、本発明では、一方の主面に所要の半導体素子機能領域を作製するプロセス処理を経た半導体基板を、紫外線透過性の支持基板に、紫外光照射処理および剥離液への浸漬処理によりそれぞれ剥離可能な接着層を介して前記一方の主面を接合面として貼付する第1工程、前記半導体基板を他方の主面から減厚し該他方の主面に所要の半導体素子機能領域を形成するプロセス処理を施した後、前記支持基板側から紫外光ランプを前記接着層に照射して、前記半導体基板から前記支持基板を剥離する第2工程、前記半導体基板に残った接着層を剥離液への浸漬処理で剥離し除去する第3工程とを備える半導体装置の製造方法とする。前記第2工程を、前記半導体基板を他方の主面から減厚し該減厚した面に所要の半導体素子機能領域を形成するプロセス処理を施した後、該所要の半導体素子機能領域を形成した面にダイシングテープを貼付し、その後、前記接着層に、前記支持基板側から紫外光ランプを照射して、前記半導体基板から前記支持基板を剥離する工程とすることも好ましい。前記紫外光ランプが、水銀ランプ、エキシマランプ、キセノンランプ、LEDランプのいずれかであることが好適である。前記紫外光ランプの波長は、400nm以下の光、特に250nm以下が好ましい。前記支持基板の材質が石英ガラス、サファイアガラス、テンパックス(登録商標)ガラス、アルカリフリーガラスから選ばれるいずれかのガラスであることが好ましい。前記支持基板は前記半導体基板の直径よりも0.1mm〜1mm程度大きい方が好ましい。また、前記接着層が、半導体基板と支持基板との接合面および前記支持基板の側面に跨って塗布されている場合にも本発明のメリットが得られる。   In order to achieve the object of the invention described above, in the present invention, a semiconductor substrate that has undergone a process treatment for producing a required semiconductor element functional region on one main surface is converted into an ultraviolet light radiating treatment and an ultraviolet transmissive support substrate. A first step of attaching the one main surface as a bonding surface through an adhesive layer that can be peeled off by immersing in a stripping solution, reducing the thickness of the semiconductor substrate from the other main surface and providing the other main surface A second step of peeling the support substrate from the semiconductor substrate by irradiating the adhesive layer with an ultraviolet lamp from the support substrate side after performing the process for forming the semiconductor element functional region of A semiconductor device manufacturing method comprising: a third step of peeling and removing the remaining adhesive layer by immersing in a stripping solution. In the second step, the semiconductor substrate is reduced in thickness from the other main surface, and a required semiconductor element functional region is formed on the reduced surface, and then the required semiconductor element functional region is formed. It is also preferable to apply a dicing tape on the surface, and then irradiate the adhesive layer with an ultraviolet lamp from the support substrate side to peel the support substrate from the semiconductor substrate. The ultraviolet lamp is preferably a mercury lamp, an excimer lamp, a xenon lamp, or an LED lamp. The wavelength of the ultraviolet lamp is preferably 400 nm or less, particularly 250 nm or less. The material of the support substrate is preferably any glass selected from quartz glass, sapphire glass, Tempax (registered trademark) glass, and alkali-free glass. The support substrate is preferably larger by about 0.1 mm to 1 mm than the diameter of the semiconductor substrate. The merit of the present invention can also be obtained when the adhesive layer is applied across the bonding surface between the semiconductor substrate and the support substrate and the side surface of the support substrate.

本発明によれば、接着層を介して貼付された半導体基板と支持基板を、所要のプロセス処理後に、半導体基板と支持基板を相互に剥離する際に、接着層の適正な接着領域からはみ出した接着層があっても、支障なく適正に剥離処理を行うことができる支持基板の剥離工程を含む半導体装置の製造方法を提供することができる。   According to the present invention, when a semiconductor substrate and a support substrate pasted via an adhesive layer are peeled from each other after a required process, the semiconductor substrate and the support substrate protruded from an appropriate adhesive region of the adhesive layer. Even if there is an adhesive layer, a method for manufacturing a semiconductor device including a support substrate peeling process capable of appropriately performing a peeling process without hindrance can be provided.

本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その1)である。It is process process sectional drawing (the 1) of the semiconductor substrate for demonstrating the manufacturing method of the semiconductor device processed thinly to the extent which requires the support substrate concerning this invention. 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その2)である。It is process process sectional drawing (the 2) of the semiconductor substrate for demonstrating the manufacturing method of the semiconductor device processed thinly to the extent which requires the support substrate concerning this invention. 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その3)である。It is process process sectional drawing (the 3) of the semiconductor substrate for demonstrating the manufacturing method of the semiconductor device processed thinly to the extent which requires the support substrate concerning this invention. 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その4)である。FIG. 10 is a process cross-sectional view of a semiconductor substrate for explaining a method of manufacturing a semiconductor device processed to be thin enough to require a support substrate according to the present invention (part 4); 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その5)である。It is process process sectional drawing (the 5) of the semiconductor substrate for demonstrating the manufacturing method of the semiconductor device processed thinly to the extent which requires the support substrate concerning this invention. 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その6)である。FIG. 11 is a process cross-sectional view (No. 6) of a semiconductor substrate for describing a method for manufacturing a semiconductor device processed to be thin enough to require a support substrate according to the present invention; 本発明にかかる、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図(その7)である。It is process process sectional drawing (the 7) of the semiconductor substrate for demonstrating the manufacturing method of the semiconductor device processed thinly to the extent which requires the support substrate concerning this invention. 従来の、支持基板を必要とする程度に薄く加工される半導体装置の製造方法を説明するための半導体基板のプロセス工程断面図である。It is process process sectional drawing of the semiconductor substrate for demonstrating the manufacturing method of the conventional semiconductor device processed thinly to the extent which requires a support substrate. 図8に示す従来の半導体装置の製造方法における問題点を説明するための半導体基板の断面図である。It is sectional drawing of the semiconductor substrate for demonstrating the problem in the manufacturing method of the conventional semiconductor device shown in FIG.

以下、本発明の半導体装置の製造方法にかかる実施例について、図面を参照して詳細に説明する。本明細書および添付図面においては、nまたはpを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、nやpに付す+および−は、それぞれ相対的に不純物濃度が高いまたは低いことを意味する。なお、以下の実施例の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。また、実施例で説明される添付図面は、見易くまたは理解し易くするために正確なスケール、寸法比で描かれていない。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。
<実施例1>
本発明の半導体装置の製造方法について、半導体ウエハ(以降、半導体ウエハを半導体基板とすることもある)厚100μm以下の半導体デバイスの製造方法を以下説明する。ウエハプロセスへの投入当初から100μm厚の薄い半導体基板面に、ただちに層や膜を堆積または付着させる加工を行うと、熱膨張係数の違いに起因して、半導体基板に生じる反りが大きくなり易い。半導体基板に反りが大きいと、その程度によっては半導体基板の割れや半導体基板の吸着装置の異常(エラー等)を起こすおそれがある。
Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is relatively high or low, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In addition, the accompanying drawings described in the embodiments are not drawn to an accurate scale and dimensional ratio for easy understanding and understanding. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
<Example 1>
Regarding the method for manufacturing a semiconductor device of the present invention, a method for manufacturing a semiconductor device having a thickness of 100 μm or less as a semiconductor wafer (hereinafter, the semiconductor wafer may be used as a semiconductor substrate) will be described below. When a process of immediately depositing or adhering a layer or film on a thin semiconductor substrate surface having a thickness of 100 μm from the beginning of the wafer process is performed, warpage generated in the semiconductor substrate tends to increase due to a difference in thermal expansion coefficient. If the semiconductor substrate is warped, depending on the degree, the semiconductor substrate may be cracked or the semiconductor substrate adsorption device may be abnormal (error, etc.).

このため、仕上がりの半導体基板厚100μm以下の厚さの薄い半導体デバイスを製造するウエハプロセスであっても、プロセスへ投入する当初の半導体基板の厚さは、例えば600μm以上の厚い半導体基板を用いる。そして、半導体基板の厚さを100μmに減厚するプロセスをできるだけ後の工程で行うようにすることが好ましい。プロセスの当初は、厚い半導体基板の状態で、一方の主面(おもて面とする)側に所要の半導体機能領域を形成するプロセスを一通り施す。この半導体基板の他方の主面(裏面とする)側に必要な半導体機能領域を形成するために、半導体基板の裏面側を研削して所定の厚さに減厚する。その際、半導体基板を薄くした後のウエハ強度を補強するために、予めおもて面側に所要の前記プロセスを終えた前述の半導体基板を石英ガラス基板などの熱膨張係数が小さい支持基板におもて面側を接合面として貼付する。   For this reason, even in a wafer process for manufacturing a thin semiconductor device having a finished semiconductor substrate thickness of 100 μm or less, a thick semiconductor substrate having an initial thickness of 600 μm or more is used, for example. It is preferable that the process of reducing the thickness of the semiconductor substrate to 100 μm is performed in the later steps as much as possible. At the beginning of the process, a process of forming a required semiconductor functional region on one main surface (referred to as the front surface) side is performed in a thick semiconductor substrate state. In order to form a necessary semiconductor functional region on the other main surface (back surface) side of the semiconductor substrate, the back surface side of the semiconductor substrate is ground and reduced to a predetermined thickness. At that time, in order to reinforce the wafer strength after the semiconductor substrate is thinned, the above-mentioned semiconductor substrate having been subjected to the required process on the front side in advance is changed to a support substrate having a low thermal expansion coefficient such as a quartz glass substrate. Affix the front side as the joint surface.

その後、接合していない側の半導体基板面(裏面)を研削して半導体基板を薄化することにより、薄化処理工程の際に、ウエハ割れが生じ難い方法が採られる。支持基板としては、前述の石英ガラス(シリカガラス)の他に、紫外線透過性、耐熱性や耐化学薬品性の良好な安定したガラスやガラスセラミックスガラス、セラミックスであれば、使用することができる。例えば、耐熱性の高いテンパックス(登録商標)ガラスなどのホウケイ酸ガラス、サファイアガラス(アルミナ系ガラス)、また、強度、耐熱性の良好なガラスセラミックスなども使用することができる。   Thereafter, the semiconductor substrate surface (back surface) on the non-bonded side is ground to thin the semiconductor substrate, thereby adopting a method in which wafer cracking hardly occurs during the thinning process. As the support substrate, in addition to the above-mentioned quartz glass (silica glass), any stable glass, glass ceramic glass, or ceramics having good ultraviolet transmittance, heat resistance, and chemical resistance can be used. For example, borosilicate glass such as Tempax (registered trademark) glass having high heat resistance, sapphire glass (alumina glass), glass ceramics having good strength and heat resistance, and the like can be used.

以下、薄型の半導体基板(例えば仕上がり厚さ100μm)を用いたIGBTなどのパワーデバイスを製造する場合について説明する。IGBTの場合、半導体基板の表面側とはエミッタ電極、ゲート電極、MOSゲート構造などのデバイス表面構造(半導体機能領域)が形成される面であり、裏面側とは、コレクタ層およびコレクタ電極が形成される面とする。   Hereinafter, a case where a power device such as an IGBT using a thin semiconductor substrate (for example, a finished thickness of 100 μm) is manufactured will be described. In the case of an IGBT, the surface side of the semiconductor substrate is a surface on which a device surface structure (semiconductor functional region) such as an emitter electrode, a gate electrode, and a MOS gate structure is formed, and the back side is formed of a collector layer and a collector electrode The surface to be used.

厚さ650μmのFZ−n型半導体基板のおもて面側に、よく知られた公知のプロセスによりエミッタ電極、ゲート電極、MOSゲート構造などの半導体機能領域(図示せず)の形成工程を一通り終了させる。この半導体基板1の裏面側の形成工程にはいる前に、前述の半導体機能領域を有する半導体基板1の表面側に、紫外線(UV光)に透明な支持基板2を、接着層3を介してズレの無いように圧着する(図1)。支持基板2は、厚さが0.1mm〜1mm 程度であればよく、半導体基板1と略同径の石英ガラス基板であればよい。   A semiconductor functional region (not shown) such as an emitter electrode, a gate electrode, and a MOS gate structure is formed on the front side of a 650 μm thick FZ-n type semiconductor substrate by a well-known process. End the street. Before entering the formation process on the back surface side of the semiconductor substrate 1, a support substrate 2 transparent to ultraviolet rays (UV light) is provided on the front surface side of the semiconductor substrate 1 having the above-described semiconductor functional region via an adhesive layer 3. Crimp so that there is no gap (Fig. 1). The support substrate 2 may have a thickness of about 0.1 mm to 1 mm, and may be a quartz glass substrate having substantially the same diameter as the semiconductor substrate 1.

この支持基板2を接着層3を介して圧着することについて、詳細に説明する。支持基板2としては、前述と同様の石英ガラスの他にテンパックス(登録商標)ガラスやサファイアガラスのように照射紫外線波長を効率よく透過するガラス、また、前述のように紫外線透過性、耐熱性や耐化学薬品性の良好な安定したガラスセラミックスガラス、セラミックスを用いることもできる。接着層3はスピンコーターを用いて、スピンナー(図示せず)上に半導体基板1を、前述の半導体機能領域側を上にして吸着させた後、スピンナーを回転させながら接着剤溶液を滴下し接着層塗膜を形成する。   The pressure bonding of the support substrate 2 via the adhesive layer 3 will be described in detail. As the support substrate 2, in addition to quartz glass similar to that described above, glass that efficiently transmits the irradiation ultraviolet wavelength, such as Tempax (registered trademark) glass and sapphire glass, and ultraviolet transmittance and heat resistance as described above. In addition, stable glass ceramic glass or ceramic having good chemical resistance can be used. The adhesive layer 3 is adhered by adhering the semiconductor substrate 1 on a spinner (not shown) using a spin coater, dropping the adhesive solution while rotating the spinner, and adsorbing the semiconductor substrate 1 with the semiconductor functional region side facing up. A layer coating is formed.

このような接着層3の形成に用いる接着剤としては、シンナーやアミン系のような有機系の剥離液への浸漬により溶解する性質を有し、かつUV光を照射することにより接着力を低下させて剥離可能な性質を有するものが望ましい。   The adhesive used to form such an adhesive layer 3 has the property of being dissolved by immersion in an organic stripping solution such as thinner or amine, and the adhesive strength is reduced by irradiation with UV light. It is desirable to have a peelable property.

さらに、接着層3を剥離する過程では、表面側に半導体機能領域が形成された半導体基板1が剥離液に接触することになるので、特に表面側の半導体機能領域の、特に最表面のパッシベーション膜であるポリイミド膜が溶解または膨潤しない性質の剥離液とする必要がある。   Further, in the process of peeling the adhesive layer 3, the semiconductor substrate 1 having the semiconductor functional region formed on the surface side comes into contact with the stripping solution. It is necessary to use a stripping solution that does not dissolve or swell the polyimide film.

その後、電気炉などで所要のポストベーク処理(200〜300℃程度、1時間)により接着塗膜中の溶剤を飛ばし、接着層3とする。前述の接着層塗膜の形成の際、半導体基板1の半導体機能領域の最表面の凹凸を吸収して平坦面にする必要があるので、接着層塗膜の厚さを5〜40μm程度となるように接着剤溶液の粘度とスピンナー回転数を適宜予め求めておくことが望ましい。圧着については、支持基板2を上にして半導体基板1と支持基板2との中心軸を一致させるような位置合わせを行い、真空中で加熱(200〜300℃程度)しながら接着層3を挟んで圧着する。この圧着により接着層3の厚さがさらに薄くなるが、半導体機能領域の最表面の凹凸の段差を無くして平坦にする程度の接着層厚さは維持する。図11に示すように、圧着により圧着面から半導体基板の側面にはみ出た接着層塗膜は支持基板や半導体基板の側面に付着する。このような側面にはみ出た接着層塗膜が発生するため、従来、はみ出した接着層塗膜には紫外波長光レーザが確実に照射されず、後工程での支持基板と半導体基板との剥離が確実に行えないという問題となっていたのである。   Thereafter, the solvent in the adhesive coating film is removed by a required post-baking process (about 200 to 300 ° C., 1 hour) in an electric furnace or the like to obtain an adhesive layer 3. When forming the above-mentioned adhesive layer coating film, it is necessary to absorb the irregularities on the outermost surface of the semiconductor functional region of the semiconductor substrate 1 to make it flat, so that the thickness of the adhesive layer coating film is about 5 to 40 μm. Thus, it is desirable to obtain the viscosity of the adhesive solution and the spinner rotation number as appropriate in advance. For crimping, the alignment is performed so that the central axes of the semiconductor substrate 1 and the support substrate 2 coincide with each other with the support substrate 2 facing up, and the adhesive layer 3 is sandwiched while being heated in a vacuum (about 200 to 300 ° C.). Crimp with. Although the thickness of the adhesive layer 3 is further reduced by this pressure bonding, the thickness of the adhesive layer is maintained so as to be flattened by eliminating the uneven step on the outermost surface of the semiconductor functional region. As shown in FIG. 11, the adhesive layer coating film that protrudes from the pressure-bonded surface to the side surface of the semiconductor substrate by pressure bonding adheres to the side surface of the support substrate or the semiconductor substrate. Since such an adhesive layer coating that protrudes from the side surface occurs, conventionally, the protruding adhesive layer coating is not reliably irradiated with an ultraviolet wavelength laser, and the support substrate and the semiconductor substrate are separated in a later step. The problem was that it could not be done reliably.

本発明ではこの問題を紫外線波長のレーザ光ではなく、紫外線波長を効率的に含むUVランプを用いることにより、解消するものである。すなわち、UVランプは、位相が揃い単一波長というコヒーレント性を有するレーザと異なり、照射方向が光源から放射状に広がるので、前述のように半導体基板の側面にはみ出た接着層塗膜部分にも充分照射され、そのはみ出た塗膜部分の接着力も低下させ剥離させることができるからである。   In the present invention, this problem is solved by using a UV lamp that efficiently includes an ultraviolet wavelength instead of a laser beam having an ultraviolet wavelength. In other words, the UV lamp, unlike the laser having the same phase and coherent properties of a single wavelength, radiates in a radial direction from the light source, so that it is sufficient for the adhesive layer coating portion protruding from the side surface of the semiconductor substrate as described above. It is because the adhesive force of the coating film portion that has been irradiated and protruded can be reduced and peeled off.

以上説明した実施例によれば、前述のように、半導体基板1の側面に圧着による接着層塗膜のはみ出しがあっても、後工程での支持基板2と半導体基板1との剥離が確実に行えないという問題が解消されるので、側面に接着層塗膜のはみ出しがある状態であっても、支障なく次工程に進めることができる。   According to the embodiment described above, as described above, even if the adhesive layer coating film protrudes from the side surface of the semiconductor substrate 1 by pressure bonding, the separation between the support substrate 2 and the semiconductor substrate 1 in the subsequent process is ensured. Since the problem that it cannot be performed is solved, even if the adhesive layer coating film protrudes from the side surface, the process can proceed to the next step without any trouble.

すなわち、半導体基板1に支持基板2を接着層3を介して貼り付けたものをバックグラインド装置(図示せず)に設置して半導体基板1の裏面を研削して所定の厚さ(100μm)に減厚する(図2)。研削面を、エッチングを含む処理液で清浄化する。清浄化した半導体基板1の裏面に、リンをドーズ量1×1011〜1×1013cm-2、加速エネルギー5MeVで、イオン注入する(図示せず)。続いて、同じ裏面からボロンをドーズ量1×1013〜1×1015cm-2、加速エネルギー50KeVでイオン注入する。その後、半導体基板1裏面にレーザを照射してアニールによるイオン注入層の活性化をおこない、バッファ層となるn+層およびコレクタ層となるp+層を形成する(図示せず)。 That is, a semiconductor substrate 1 bonded with a support substrate 2 via an adhesive layer 3 is placed in a back grinding apparatus (not shown) and the back surface of the semiconductor substrate 1 is ground to a predetermined thickness (100 μm). The thickness is reduced (FIG. 2). The ground surface is cleaned with a processing solution including etching. Phosphorus is ion-implanted into the cleaned back surface of the semiconductor substrate 1 at a dose of 1 × 10 11 to 1 × 10 13 cm −2 and an acceleration energy of 5 MeV (not shown). Subsequently, boron is ion-implanted from the same back surface at a dose of 1 × 10 13 to 1 × 10 15 cm −2 and an acceleration energy of 50 KeV. Thereafter, the back surface of the semiconductor substrate 1 is irradiated with a laser to activate the ion implantation layer by annealing to form an n + layer serving as a buffer layer and a p + layer serving as a collector layer (not shown).

次に、半導体基板1の裏面に、例えばアルミニウム、チタン、ニッケルおよび金などの複数の金属を蒸着し、コレクタ電極となる裏面電極4を形成する(図3)。半導体基板1の裏面に耐熱性、耐薬品性のあるダイシングテープ5を貼り付け、搬送性を確保するためにダイシングテープ5にリング状のダイシングフレーム6を取り付ける(図4)。支持基板2側からUVランプ10によって紫外波長光を接着層に照射し、半導体基板1の表面側と支持基板2との間に介在する接着層3の接着力を弱めて支持基板2を剥離させる(図5)。その際、接着層3に照射される紫外波長光は、半導体基板1との間よりも、光源により近い支持基板2と接着層との間の接着力をより低下させるので、支持基板2を剥離させると、接着層3は半導体基板1の表面に残り易い。この接着層3を溶解させるために、常温〜80℃にした剥離液に半導体基板1を浸漬するか半導体基板1の上部から剥離液を吹き付ける。浸漬時間は、接着層の量や剥離液の温度によっても変わってくるが、1〜30分程度である(図6)。   Next, a plurality of metals such as aluminum, titanium, nickel, and gold are vapor-deposited on the back surface of the semiconductor substrate 1 to form a back electrode 4 that serves as a collector electrode (FIG. 3). A dicing tape 5 having heat resistance and chemical resistance is attached to the back surface of the semiconductor substrate 1, and a ring-shaped dicing frame 6 is attached to the dicing tape 5 in order to ensure transportability (FIG. 4). The UV layer 10 irradiates the adhesive layer with ultraviolet wavelength light from the support substrate 2 side, weakens the adhesive force of the adhesive layer 3 interposed between the surface side of the semiconductor substrate 1 and the support substrate 2, and peels the support substrate 2. (FIG. 5). At this time, the ultraviolet wavelength light applied to the adhesive layer 3 lowers the adhesive force between the support substrate 2 and the adhesive layer closer to the light source than between the semiconductor substrate 1, so that the support substrate 2 is peeled off. As a result, the adhesive layer 3 tends to remain on the surface of the semiconductor substrate 1. In order to dissolve the adhesive layer 3, the semiconductor substrate 1 is immersed in a stripping solution at room temperature to 80 ° C. or the stripping solution is sprayed from the upper part of the semiconductor substrate 1. The immersion time varies depending on the amount of the adhesive layer and the temperature of the stripping solution, but is about 1 to 30 minutes (FIG. 6).

ダイシングテープ5の材質として、耐化学薬品性のあるポリオレフィン製(PO)のものやポリエチレンテレフタレート製(PET)のものが望ましい。UVランプ10としては、水銀ランプやエキシマランプ、キセノンランプ等が好ましい。また、UVランプ10の照度として5J/cm2以上のものであれば短時間で処理が完了する。半導体基板1の表面に残った接着層3を除去する剥離液としては、シンナーやアミン系などの有機溶液が好ましい。 The material of the dicing tape 5 is preferably made of a chemical resistant polyolefin (PO) or polyethylene terephthalate (PET). As the UV lamp 10, a mercury lamp, excimer lamp, xenon lamp or the like is preferable. If the illuminance of the UV lamp 10 is 5 J / cm 2 or more, the processing is completed in a short time. As the stripper for removing the adhesive layer 3 remaining on the surface of the semiconductor substrate 1, an organic solution such as thinner or amine is preferable.

そして、半導体基板1の表面から接着層の残渣を除去した半導体基板1をダイシング装置に取り付け、ダイシング装置のダイシングブレードソー7の高速回転により、ダイス状にカッティングを行ってチップ化を実施すれば(図7)、半導体デバイス(IGBT)チップの完成である。   Then, the semiconductor substrate 1 from which the adhesive layer residue has been removed from the surface of the semiconductor substrate 1 is attached to a dicing apparatus, and the dicing blade saw 7 of the dicing apparatus is cut into a dice shape to form chips (see FIG. FIG. 7), the completion of a semiconductor device (IGBT) chip.

従来のUVレーザの接着層への照射による支持基板の離脱方式では、半導体基板と支持基板から接着層がはみ出ている場合、レーザの焦点距離等の影響により、はみ出し塗膜40に確実に照射できず、半導体基板54から支持基板51の離脱が正常に行えない場合があった(図9)。これらの問題を解決するため、光の焦点距離に関係なく基板全面に比較的均一な照度で照射可能な水銀ランプやエキシマランプ、キセノンランプ等のUVランプの照射方式を用いることによって、半導体基板や支持基板の側壁にはみ出し塗膜40が付着した状態でも、UV光源が接着層全体に照射されるため、半導体基板から支持基板の離脱が簡単に行われるようになる。   In the conventional method of detaching the support substrate by irradiating the adhesive layer of the UV laser, when the adhesive layer protrudes from the semiconductor substrate and the support substrate, it is possible to reliably irradiate the protruding coating film 40 due to the influence of the focal length of the laser or the like. In some cases, the support substrate 51 cannot be normally detached from the semiconductor substrate 54 (FIG. 9). In order to solve these problems, by using an irradiation method of a UV lamp such as a mercury lamp, an excimer lamp, or a xenon lamp that can irradiate the entire surface of the substrate with a relatively uniform illuminance regardless of the focal length of light, a semiconductor substrate or Even when the protruding coating film 40 is attached to the side wall of the support substrate, the UV light source is irradiated on the entire adhesive layer, so that the support substrate can be easily detached from the semiconductor substrate.

1 半導体基板
2 支持基板
3 接着層
4 金属膜
5 ダイシングテープ
6 ダイシングフレーム
7 ダイシングブレードソー
10 UVランプ
40 はみ出し塗膜

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Support substrate 3 Adhesion layer 4 Metal film 5 Dicing tape 6 Dicing frame 7 Dicing blade saw 10 UV lamp 40 Extrusion coating film

Claims (6)

一方の主面に所要の半導体素子機能領域を作製するプロセス処理を経た半導体基板を、紫外線透過性の支持基板に、紫外光照射処理および剥離液への浸漬処理によりそれぞれ剥離可能な接着層を介して前記一方の主面を接合面として貼付する第1工程、前記半導体基板を他方の主面から減厚し、該減厚した面に所要の半導体素子機能領域を形成するプロセス処理を施した後、前記支持基板側から紫外光ランプを前記接着層全面に照射して、前記半導体基板から前記支持基板を剥離する第2工程、前記半導体基板に残った接着層を剥離液への浸漬処理で剥離し除去する第3工程とを備えることを特徴とする半導体装置の製造方法。 A semiconductor substrate that has undergone a process process for producing a required semiconductor element functional region on one main surface is placed on an ultraviolet transmissive support substrate through an adhesive layer that can be peeled off by an ultraviolet light irradiation process and an immersion process in a stripping solution. A first step of pasting the one main surface as a bonding surface, and performing a process of reducing the thickness of the semiconductor substrate from the other main surface and forming a required semiconductor element functional region on the reduced surface , A second step of irradiating the entire surface of the adhesive layer with an ultraviolet lamp from the support substrate side to peel the support substrate from the semiconductor substrate; peeling the adhesive layer remaining on the semiconductor substrate by a dipping process in a stripping solution; And a third step of removing the semiconductor device. 前記第2工程を、前記半導体基板を他方の主面から減厚し、該減厚した面に所要の半導体素子機能領域を形成するプロセス処理を施した後、該所要の半導体素子機能領域を形成した面にダイシングテープを貼付し、その後、前記支持基板側から紫外光ランプを前記接着層に照射して、前記半導体基板から前記支持基板を剥離する工程とすることを特徴とする請求項1記載の半導体装置の製造方法。 In the second step, the semiconductor substrate is reduced in thickness from the other main surface, and a required semiconductor element functional region is formed on the reduced surface, and then the required semiconductor element functional region is formed. The dicing tape is affixed to the finished surface, and thereafter the adhesive substrate is irradiated with an ultraviolet lamp from the side of the support substrate to separate the support substrate from the semiconductor substrate. Semiconductor device manufacturing method. 前記紫外光ランプが、水銀ランプ、エキシマランプ、キセノンランプのいずれかであることを特徴とする請求項2記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein the ultraviolet lamp is any one of a mercury lamp, an excimer lamp, and a xenon lamp. 前記支持基板の材質が石英ガラス、耐熱ガラス、耐化学薬品性ガラスから選ばれるいずれかのガラスであることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, wherein a material of the support substrate is any glass selected from quartz glass, heat-resistant glass, and chemical-resistant glass. 5. 前記支持基板が前記半導体基板と略同径であることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the support substrate has substantially the same diameter as the semiconductor substrate. 前記接着層が、半導体基板と支持基板との接合面および前記支持基板の側面に跨って塗布されていることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置の製造方法。

6. The method of manufacturing a semiconductor device according to claim 1, wherein the adhesive layer is applied across a bonding surface between the semiconductor substrate and the support substrate and a side surface of the support substrate. .

JP2012108721A 2012-05-10 2012-05-10 Manufacturing method of semiconductor device Pending JP2013236016A (en)

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Cited By (4)

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JP2016046321A (en) * 2014-08-20 2016-04-04 富士電機株式会社 Manufacturing method and manufacturing apparatus of semiconductor device
JP2018538684A (en) * 2015-11-20 2018-12-27 アールエフエイチアイシー コーポレイション Semiconductor-on-diamond wafer mounting for device processing
WO2019039432A1 (en) * 2017-08-25 2019-02-28 東京エレクトロン株式会社 Substrate processing method, computer storage medium and substrate processing system
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016046321A (en) * 2014-08-20 2016-04-04 富士電機株式会社 Manufacturing method and manufacturing apparatus of semiconductor device
JP2018538684A (en) * 2015-11-20 2018-12-27 アールエフエイチアイシー コーポレイション Semiconductor-on-diamond wafer mounting for device processing
US11404300B2 (en) 2015-11-20 2022-08-02 Rfhic Corporation Mounting of semiconductor-on-diamond wafers for device processing
WO2019039432A1 (en) * 2017-08-25 2019-02-28 東京エレクトロン株式会社 Substrate processing method, computer storage medium and substrate processing system
JPWO2019039432A1 (en) * 2017-08-25 2020-08-27 東京エレクトロン株式会社 Substrate processing method, computer storage medium, and substrate processing system
CN110739259A (en) * 2018-07-18 2020-01-31 英飞凌科技股份有限公司 Support table, support table assembly, processing device and method thereof

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