JP2013232267A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing an increase in a circuit scale.SOLUTION: A semiconductor device of the present invention includes: electric fuses F1 and F2 that are connected in series and can electrically be disconnected; a disconnection circuit 11 that, when the electric fuses F1 and F2 are selected as disconnection objects, passes a current through each of the electric fuses F1 and F2 separately so as to disconnect them; and a read circuit 12 that generates a switching signal for controlling a control object on the basis of the disconnection states of the electric fuses F1 and F2.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a memory circuit using an electric fuse.

  In recent years, in a semiconductor device, a nonvolatile storage means that can retain stored information even when the power is turned off has become an indispensable element. For example, a fuse that stores information irreversibly by cutting an element is known as a nonvolatile storage unit.

  This fuse is used for relief of defective memory cells in a semiconductor memory device. A semiconductor memory device has a redundant memory cell (redundant circuit) that relieves a defect of a memory cell generated in a manufacturing process in order to improve yield and reduce chip cost. By replacing the memory cell with a redundant memory cell, the defect of the memory cell is relieved. A fuse is used to store information such as an address specifying the defective memory cell.

  The fuse memorizes information according to its cutting state, so if a disconnection failure occurs, such as insufficient cutting or a fuse that has been disconnected once again during actual operation, the stored information is misrecognized, The circuit may malfunction. If switching to a redundant memory cell is not performed due to a defective fuse disconnection, the defective memory cell cannot be relieved and the yield decreases.

  A solution to such a problem is disclosed in Patent Document 1. FIG. 6 is a configuration diagram of a fuse cutting / reading circuit disclosed in Patent Document 1. In FIG. The fuse cutting / reading circuit shown in FIG. 6 includes a plurality of electrical fuses 100a and 100b that can be electrically disconnected, a selector 101 that selects the plurality of electrical fuses 100a and 100b according to a selection signal, and a plurality of selected plurality of electrical fuses. A cutting circuit 102 that cuts the electric fuses 100a and 100b by flowing a current and a switching signal generation circuit 103 that generates a switching signal based on the cutting states of the plurality of electric fuses 100a and 100b are provided.

  Accordingly, Patent Document 1 discloses that the fuse cutting / reading circuit shown in FIG. 6 prevents malfunction due to defective cutting of the fuse.

JP 2007-172720 A

  However, in the fuse cutting / reading circuit of the related technique shown in FIG. 6, it is necessary to provide a latch circuit and two transistors for each of the electric fuses 100a and 100b connected in parallel. More specifically, transistors N3 and N5 and a latch circuit 104a need to be provided for the electric fuse 100a, and transistors N4 and N6 and a latch circuit 104b need to be provided for the electric fuse 100b. Therefore, the fuse cutting / reading circuit of the related technology has a problem that the circuit scale increases.

  A semiconductor device according to one embodiment of the present invention includes a plurality of electrical fuses that are connected in series and can be electrically disconnected, and each of the plurality of electrical fuses when the plurality of electrical fuses is selected as a cutting target. A cutting circuit that individually cuts the current by passing a current; and a control signal generation circuit that generates a control signal for controlling a control target based on a cutting state of the plurality of electric fuses.

  A semiconductor device according to an aspect of the present invention includes a plurality of first electrical fuses that are connected in series and can be electrically disconnected, and a plurality of second electrical fuses that are connected in series and can be electrically disconnected. When a plurality of first electric fuses are selected as a cutting target, a first cutting circuit that cuts each of the plurality of first electric fuses by flowing a current individually and the plurality of second electric fuses to be cut A second cutting circuit for cutting each of the plurality of second electric fuses by flowing a current individually, and a selection signal among the plurality of first electric fuses and the plurality of second electric fuses. And a control signal generation circuit that generates a control signal for controlling a control target based on the cutting state of any one of the plurality of electrical fuses selected based on the above.

  With the circuit configuration as described above, an increase in circuit scale can be suppressed.

  According to the present invention, a semiconductor device capable of suppressing an increase in circuit scale can be provided.

It is a figure which shows the structural example of the semiconductor device concerning Embodiment 1 of this invention. 3 is a timing chart showing an operation of the semiconductor device according to the first exemplary embodiment of the present invention; It is a figure which shows the structural example of the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the layout structure of the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the structural example of the semiconductor device concerning Embodiment 3 of this invention. It is a figure which shows the structure of the fuse cutting / reading circuit of related technology.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

Embodiment 1
FIG. 1 is a diagram illustrating a configuration example of a fuse cutting / reading circuit (semiconductor device) 1 according to a first embodiment of the present invention. The fuse cutting / reading circuit 1 according to the present embodiment has two electric fuses (eFUSE) connected in series, and when any one of the two electric fuses is cut, the fuse cutting / reading circuit 1 is cut. A switching signal (control signal) indicating that the operation has been performed is output. Since the fuse cutting / reading circuit 1 according to the present embodiment only needs to include one set of a common latch circuit and transistor for each of the two electric fuses, an increase in circuit scale can be suppressed. This will be specifically described below.

  The fuse cutting / reading circuit 1 shown in FIG. 1 is provided as a part of a semiconductor memory device that stores desired information in a memory cell, for example. The semiconductor memory device further includes a memory cell array in which a plurality of memory cells are arranged in a lattice pattern, and a switching circuit. The memory cell array has a plurality of word lines arranged in the row direction and a plurality of bit lines arranged in the column direction, and the memory cells are arranged at positions where the word lines and the bit lines intersect. For example, when a predetermined potential is applied to a word line selected from a plurality of word lines and a bit line selected from the plurality of bit lines, writing / reading of desired information is performed. Is called.

  The memory cell array has a normal cell region and a redundant cell region. The normal cell area is an area for storing information by a memory cell having no defect, and the redundant cell area is an area for replacing and repairing a defective cell (defective memory cell) in the normal cell area. Memory cells in the normal cell region are referred to as normal cells (normal memory cells), and memory cells in the redundant cell region are referred to as redundant cells (redundant memory cells). For example, when a defective cell is detected in the normal cell region, it is replaced with a redundant cell in bit line units.

  The switching circuit switches the defective cell in the normal cell region to the redundant cell in the redundant cell region based on the switching signal from the fuse cutting / reading circuit 1. For example, the switching circuit replaces a defective cell with a redundant cell and relieves the defective cell by switching a connection between a driving circuit for writing / reading and a bit line of the memory cell array. That is, the switching circuit switches the bit line of the address indicated by the switching signal to the bit line of the redundant cell.

  As will be described later, the fuse cutting / reading circuit 1 has a plurality of electric fuses connected in series as an irreversible storage element, and cuts a plurality of electric fuses and reads out the cutting status and outputs a switching signal. Generate. The electric fuse is a fuse that can be electrically cut by applying a voltage and flowing a current, and is formed of a metal such as Al or Cu, for example. The plurality of electrical fuses is also a nonvolatile storage unit that stores a switching signal (defective cell information) for replacing a defective cell with a redundant cell depending on the cut state. For example, the switching information is a defective cell address (defective address).

  That is, the fuse cutting / reading circuit 1 individually stores a plurality of electrical fuses connected in series according to an input data signal, stores switching information, and reads and latches the switching information according to the cutting state of the electrical fuse. And output to the switching circuit as a switching signal. The switching signal is a signal for specifying a defective memory cell and switching to a redundant cell, and is also a control signal for controlling a switching circuit and a memory cell array that are control targets.

  Next, the configuration and operation of the fuse cutting / reading circuit 1 shown in FIG. 1 will be described in detail. The fuse cutting / reading circuit 1 includes electrical fuses F1 and F2, a cutting circuit 11, and a reading circuit (control signal generation circuit) 12.

  The electrical fuses F1 and F2 are storage elements that store whether or not to switch a defective cell to a redundant cell. The electrical fuses F1 and F2 are provided for each relief unit. In other words, the electrical fuses F1 and F2 are provided for each redundant cell that relieves a defective cell. For example, the electrical fuses F1 and F2 are provided for each bit line (1 bit) of the memory cell array. Then, a selector (not shown) selects the electrical fuses F1 and F2 corresponding to the defective cell from among the plurality of electrical fuses F1 and F2 based on a data signal (selection signal) supplied from outside. For example, the data signal is an address of a defective cell. Hereinafter, only one set of the electrical fuses F1 and F2 corresponding to a certain defective cell among the plurality of electrical fuses F1 and F2 will be described.

  The cutting circuit 11 is a circuit that cuts the electric fuses F1 and F2 selected as the cutting target by passing a current. The cutting circuit 11 includes transistors TR3, TR4, and TR5. In the present embodiment, a case where the transistors TR3 and TR5 are N-channel MOS transistors and the transistor TR4 is a P-channel MOS transistor will be described as an example.

  In the transistor TR3, a source is connected to a ground voltage terminal (hereinafter referred to as a ground voltage terminal GND) to which a ground voltage GND is supplied from a power supply, a drain is connected to one end of the electric fuse F1 via a node N1, and a gate is connected. The data signal described above is supplied. In the transistor TR4, a source is connected to a power supply voltage terminal (hereinafter referred to as a power supply voltage terminal VDD1) to which a power supply voltage VDD1 is supplied from a power supply, and a drain is connected to the other end of the electric fuse F1 and one end of the fuse F2. Is supplied with a data signal. In the transistor TR5, the source is connected to the ground voltage terminal GND, the drain is connected to the other end of the electric fuse F2, and the data signal is supplied to the gate.

  The procedure for cutting the electrical fuses F1, F2 by the cutting circuit 11 will be described with reference to the timing chart of FIG. The cutting circuit 11 cuts off the electric fuses F1 and F2 by individually supplying current. Note that, when the electric fuse is cut, transistors TR1 and TR2 of the readout circuit 12 described later are both turned off. The power supply voltage VDD1 only needs to be supplied to the power supply voltage terminal VDD1 only when the electric fuse is cut.

  First, according to the data signal, an L level voltage is applied to the gate of the transistor TR3, an L level voltage is applied to the gate of the transistor TR4, and an H level voltage is applied to the gate of the transistor TR5. Thereby, the transistors TR4 and TR5 are turned on and the transistor TR3 is turned off. As a result, a current flows from the power supply voltage terminal VDD1 to the ground voltage terminal GND through the transistor TR4, the electric fuse F2, and the transistor TR5, so that the electric fuse F2 is cut.

  Next, an H level voltage is applied to the gate of the transistor TR3, an L level voltage is applied to the gate of the transistor TR4, and an L level voltage is applied to the gate of the transistor TR5 by the data signal. Thereby, the transistors TR3 and TR4 are turned on and the transistor TR5 is turned off. As a result, a current flows from the power supply voltage terminal VDD1 to the ground voltage terminal GND through the transistor TR4, the electric fuse F1, and the transistor TR3, so that the electric fuse F1 is cut.

  In this way, the electric fuses F1 and F2 connected in series are disconnected. The first electric fuse (F2) is cut in synchronization with the rising edge of the clock signal (CLOCK), and the second electric fuse (F1) is cut in synchronization with the falling edge of the clock signal. As a result, all the electrical fuses (F1, F2) can be cut using only one cycle of the clock signal. Thereby, the user can use the fuse cutting / reading circuit 1 as one macro without being aware of cutting each of the plurality of electric fuses.

  The readout circuit 12 outputs a switching signal based on the cut state of the electrical fuses F1, F2. That is, the reading circuit 12 reads and latches the cut state of the electric fuses F1 and F2, and outputs the latched state as a switching signal. Read circuit 12 includes transistors TR1 and TR2, inverters INV1 and INV2, and a latch circuit LAT1. In this embodiment, a case where the transistors TR1 and TR2 are P-channel MOS transistors will be described as an example.

  In the transistor TR1, a source is connected to a power supply voltage terminal (hereinafter referred to as a power supply voltage terminal VDD2) to which a power supply voltage VDD2 is supplied from a power supply, a drain is connected to an input terminal of the inverter INV1, and the data signal described above is connected to a gate. Supplied. In the transistor TR2, the drain is connected to the node N1, the source is connected to the input terminal of the inverter INV1, and the data signal is supplied to the gate. The output terminal of the inverter INV1 is connected to the data input terminal of the latch circuit LAT1. The data output terminal of the latch circuit LAT1 is connected to the input terminal of the inverter INV2. The output of the inverter INV2 is supplied as a switching signal to a switching circuit (not shown).

  When the read circuit 12 reads the cut state of the electric fuses F1, F2, an L level voltage is applied to the gates of the transistors TR1, TR2, TR3 by the data signal, and an H level is applied to the gates of the transistors TR4, TR5. Is applied. Thereby, the transistors TR1, TR2, and TR5 are turned on, and the transistors TR3 and TR4 are turned off.

  For example, when no defect occurs in the normal cell, neither of the electric fuses F1 and F2 is cut. Therefore, a current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND through the transistors TR1 and TR2, the electric fuses F1 and F2, and the transistor TR5. Thereby, the voltage level of the input terminal of the inverter INV1 becomes L level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (H level). Therefore, the output of the inverter INV2, that is, the switching signal becomes L level.

  On the other hand, when a defect occurs in the normal cell, both the electric fuses F1 and F2 are cut. Therefore, no current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND via the transistors TR1 and TR2, the electrical fuses F1 and F2, and the transistor TR5. As a result, the voltage at the input terminal of the inverter INV1 becomes H level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (L level). Therefore, the output of the inverter INV2, that is, the switching signal becomes H level.

  As described above, when a defect does not occur in the normal cell, the switching signal indicates the L level, and when a defect occurs in the normal cell, the switching signal indicates the H level.

  In addition, even when both of the electric fuses F1 and F2 are cut when a defect occurs in the normal cell, one of them may re-adhere for some reason. Alternatively, when a defect occurs in a normal cell, one of the electric fuses F1 and F2 that should be cut may not be cut for some reason. Even in such a case, if any one of them is disconnected, no current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND via the transistors TR1 and TR2, the electrical fuses F1 and F2, and the transistor TR5. As a result, the voltage at the input terminal of the inverter INV1 becomes H level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (L level). Therefore, the output of the inverter INV2, that is, the switching signal becomes H level. Thus, even when there is a disconnection failure in one of the electric fuses F1 and F2, it can continue to operate normally, so that reliability is improved.

  As described above, the fuse cutting / reading circuit 1 according to the present embodiment has the two electric fuses F1 and F2 connected in series, and any one of the two electric fuses F1 and F2 is cut. If it is, a switching signal indicating that it is disconnected is output. Since the fuse cutting / reading circuit 1 according to the present embodiment only needs to include one set of a common latch circuit and a transistor for each of the two electric fuses F1 and F2, the circuit scale is maintained while maintaining reliability. Can be suppressed.

Embodiment 2
FIG. 3 is a diagram showing a configuration example of the fuse cutting / reading circuit (semiconductor device) 2 according to the second embodiment of the present invention. The fuse cutting / reading circuit 2 shown in FIG. 3 differs from the fuse cutting / reading circuit 1 shown in FIG. 1 in the number of electric fuses connected in series and the configuration of the cutting circuit for cutting these electric fuses. This will be specifically described below.

  The fuse cutting / reading circuit 2 shown in FIG. 3 includes electrical fuses F1 to F3, a reading circuit 12, and a cutting circuit 21.

  The cutting circuit 21 includes transistors TR3, TR4, TR5, and TR6. In the present embodiment, the case where transistors TR3 and TR5 are N-channel MOS transistors and transistors TR4 and TR6 are P-channel MOS transistors will be described as an example.

  In the transistor TR3, the source is connected to the ground voltage terminal GND, the drain is connected to one end of the electric fuse F1 through the node N1, and the data signal is supplied to the gate. In the transistor TR4, the source is connected to the power supply voltage terminal VDD1, the drain is connected to the other end of the electric fuse F1 and one end of the fuse F2, and a data signal is supplied to the gate. In the transistor TR5, the source is connected to the ground voltage terminal GND, the drain is connected to the other end of the electric fuse F2 and one end of the fuse F3, and a data signal is supplied to the gate. In the transistor TR6, the source is connected to the power supply voltage terminal VDD1, the drain is connected to the other end of the electric fuse F3, and the data signal is supplied to the gate.

  A procedure for cutting the electrical fuses F1, F2, and F3 by the cutting circuit 21 will be described. The cutting circuit 21 cuts off the electric fuses F1, F2, and F3 by individually supplying current. Note that when the electric fuse is cut, both the transistors TR1 and TR2 of the readout circuit 12 are off. The power supply voltage VDD1 only needs to be supplied to the power supply voltage terminal VDD1 only when the electric fuse is cut.

  First, an L level voltage is applied to the respective gates of the transistors TR3 and TR6 and an H level voltage is applied to the respective gates of the transistors TR4 and TR5 according to the data signal. Thereby, the transistors TR5 and TR6 are turned on, and the transistors TR3 and TR4 are turned off. As a result, a current flows from the power supply voltage terminal VDD1 to the ground voltage terminal GND through the transistor TR6, the electric fuse F3, and the transistor TR5, so that the electric fuse F3 is cut.

  Next, an L level voltage is applied to the respective gates of the transistors TR3 and TR4, and an H level voltage is applied to the respective gates of the transistors TR5 and TR6 by the data signal. Thereby, the transistors TR4 and TR5 are turned on, and the transistors TR3 and TR6 are turned off. As a result, a current flows from the power supply voltage terminal VDD1 to the ground voltage terminal GND through the transistor TR4, the electric fuse F2, and the transistor TR5, so that the electric fuse F2 is cut.

  Next, an H level voltage is applied to the respective gates of the transistors TR3 and TR6 and an L level voltage is applied to the respective gates of the transistors TR4 and TR5 according to the data signal. Thereby, the transistors TR3 and TR4 are turned on, and the transistors TR5 and TR6 are turned off. As a result, a current flows from the power supply voltage terminal VDD1 to the ground voltage terminal GND through the transistor TR4, the electric fuse F1, and the transistor TR3, so that the electric fuse F1 is cut.

  In this way, the three electric fuses F1, F2, F3 connected in series are disconnected.

  Since the configuration of the readout circuit 12 is the same as that of the first embodiment, description thereof is omitted. Here, when the reading circuit 12 reads the disconnection state of the electrical fuses F1, F2, and F3, an L level voltage is applied to the gates of the transistors TR1, TR2, TR3, TR5, and TR6 according to the data signal, and the transistor TR4. An H level voltage is applied to the gates. Thereby, the transistors TR1, TR2, and TR6 are turned on, and the transistors TR3, TR4, and TR5 are turned off.

  For example, when no defect occurs in the normal cell, none of the electric fuses F1, F2, and F3 are cut. Therefore, a current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND through the transistors TR1 and TR2, the electric fuses F1, F2, and F3, and the transistor TR6. Thereby, the voltage level of the input terminal of the inverter INV1 becomes L level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (H level). Therefore, the output of the inverter INV2, that is, the switching signal becomes L level.

  On the other hand, when a defect occurs in the normal cell, the electric fuses F1, F2, and F3 are all cut. Therefore, no current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND through the transistors TR1 and TR2, the electrical fuses F1, F2, and F3 and the transistor TR6. As a result, the voltage at the input terminal of the inverter INV1 becomes H level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (L level). Therefore, the output of the inverter INV2, that is, the switching signal becomes H level.

  As described above, when a defect does not occur in the normal cell, the switching signal indicates the L level, and when a defect occurs in the normal cell, the switching signal indicates the H level.

  In addition, even if all of the electric fuses F1, F2, and F3 are cut when a defect occurs in the normal cell, one of them may re-adhere for some reason. Alternatively, when a defect occurs in a normal cell, one of the electric fuses F1, F2, and F3 that should be cut may not be cut for some reason. Even in such a case, if any one of them is disconnected, no current flows from the power supply voltage terminal VDD2 to the ground voltage terminal GND via the transistors TR1, TR2, the electrical fuses F1, F2, F3, and the transistor TR6. As a result, the voltage at the input terminal of the inverter INV1 becomes H level. The latch circuit LAT1 latches the inverted signal and outputs the latched state (L level). Therefore, the output of the inverter INV2, that is, the switching signal becomes H level. As described above, even if any of the electrical fuses F1, F2, and F3 has a disconnection failure, it can continue to operate normally, thereby improving reliability.

  FIG. 4 is a diagram showing a layout configuration of the fuse cutting / reading circuit 2 shown in FIG. In FIG. 4, two fuse cutting / reading circuits 2 are shown. Below, the fuse cutting / reading circuit 2 on one side (left side of the drawing) will be described as a representative.

  As shown in FIG. 4, transistors TR6 and TR4 are arranged adjacent to each other in the horizontal direction of the paper on the N well located above the paper. In addition, transistors TR5 and TR3 are arranged adjacent to each other in the horizontal direction of the paper on the P-well located below the paper. The transistors TR3 to TR6 are arranged so that the longitudinal direction of the gate electrode is the longitudinal direction of the paper surface. Further, the transistors TR6 and TR4 and the transistors TR5 and TR3 are opposed to each other with the horizontal direction of the paper surface as an axis.

  Note that in this embodiment, the case where the transistors TR6 and TR4 have substantially the same gate size, that is, substantially the same gate width and substantially the same gate length will be described as an example. In this embodiment, the case where the transistors TR5 and TR3 have substantially the same gate size, that is, the substantially same gate width and the substantially same gate length will be described as an example.

  The electric fuse F1 is disposed between the drain of the transistor TR3 and the drain of the transistor TR4. The electric fuse F2 is disposed between the drain of the transistor TR4 and the drain of the transistor TR5. The electric fuse F3 is disposed between the drain of the transistor TR5 and the drain of the transistor TR6.

  Here, the wiring lengths of the wirings connecting the transistors TR3 to TR6 and the electrical fuses F1 to F3 are preferably adjusted to be substantially the same in order to make the resistance values the same. Moreover, it is preferable to make these wirings as thick as possible to reduce the resistance value. Accordingly, when the electric fuses F1 to F3 are cut, substantially the same voltage can be applied to the respective electric fuses so that substantially the same current can flow. The variation in the cutting shape can be suppressed.

Embodiment 3
FIG. 5 is a diagram illustrating a configuration example of the fuse cutting / reading circuit 3 according to the third embodiment of the present invention. In the fuse cutting / reading circuit 3 shown in FIG. 5, as compared with the fuse cutting / reading circuit 1 shown in FIG. 1, the reading circuit 12 is shared by three sets of cutting circuits and electric fuses.

  The electrical fuses F11, F21, and F31 correspond to the electrical fuse F1 in FIG. 1, and the electrical fuses F12, F22, and F32 correspond to the electrical fuse F2 in FIG. The transistors TR13, TR23, and TR33 correspond to the transistor TR3 in FIG. 1, the transistors TR14, TR24, and TR34 correspond to the transistor TR4 in FIG. 1, and the transistors TR15, TR25, and TR35 correspond to the transistor TR5 in FIG. . The configuration and operation of each circuit are the same as those shown in FIG.

  In addition, by selectively turning on any of the transistors TR15, TR25, and TR35, the electrical fuses (first electrical fuses) F11 and F12, the electrical fuses (second electrical fuses) F21 and F22, and the electrical fuses F31, F31, It is possible to read out the cutting state of any of the electrical fuses selected from F32. The transistors TR13, TR14, and TR15 are also referred to as a first disconnect circuit. The transistors TR23, TR24, and TR25 are also referred to as a second cutting circuit.

  With such a circuit configuration, since the readout circuit 12 is shared, an increase in circuit scale is suppressed.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the number of electrical fuses connected in series is not limited to two or three, and may be four or more.

1,2,3 fuse cutting / reading circuit 11,21 cutting circuit 12 reading circuit F1-F3 electric fuse F11, F12, F21, F22, F31, F32 electric fuse INV1, INV2 inverter LAT1 latch circuit TR1-TR6 transistor TR13-TR15 , TR23 to TR25, TR33 to TR35 Transistors

Claims (5)

A plurality of electrical fuses connected in series and electrically disconnectable;
When the plurality of electrical fuses are selected for cutting, a cutting circuit that cuts each of the plurality of electrical fuses by flowing a current individually, and
A semiconductor device comprising: a control signal generation circuit that generates a control signal for controlling a control target based on a cut state of the plurality of electric fuses. A plurality of first electrical fuses connected in series and electrically disconnectable;
A plurality of second electrical fuses connected in series and electrically disconnectable;
A first cutting circuit that, when the plurality of first electric fuses are selected as a cutting target, individually cuts each of the plurality of first electric fuses by passing a current;
A second cutting circuit that cuts each of the plurality of second electric fuses by flowing a current individually when the plurality of second electric fuses are selected as cutting targets;
A control signal for controlling a controlled object based on a cutting state of any one of the plurality of first electric fuses and the plurality of second electric fuses selected based on a selection signal. A control signal generation circuit for generating the semiconductor device. The control signal generation circuit includes:
3. The semiconductor device according to claim 1, wherein the control signal is generated based on whether or not a current flows through the plurality of electric fuses connected in series.   The semiconductor device according to claim 1, wherein when any one of the plurality of electric fuses is cut, the control signal indicating that the fuse is cut is generated. .   The semiconductor device according to claim 1, wherein the control signal indicating that the plurality of electric fuses are not cut is generated only when none of the plurality of electric fuses is cut.

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