JP2013232262A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the discharge time of a bit line while suppressing an increase in layout area.SOLUTION: A nonvolatile semiconductor memory device includes: a sense amplifier circuit 8 that is connected to one end of bit lines BL1-BLm; and a charge/discharge circuit 3 that is connected to the other end of the bit lines BL1-BLm. The charge/discharge circuit 3 is formed on a well WEL where a memory cell array 1 is arranged, and charges or discharges the bit lines BL1-BLm in cooperation with the charge operation or discharge operation for the bit lines BL1-BLm which is performed by the sense amplifier circuit 8.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

  In a NAND flash memory, a bit line is discharged through a sense amplifier circuit when a read operation or the like is completed. In this discharge operation, if the parasitic capacitance and sheet resistance of the bit line increase with the miniaturization of the memory cell, the discharge time is increased.

JP 2002-117699 A

  The present embodiment provides a nonvolatile semiconductor memory device that can shorten the discharge time of a bit line while suppressing an increase in layout area.

  According to the nonvolatile semiconductor memory device of the embodiment, a memory cell array, a word line, a bit line, a sense amplifier circuit, and a charge / discharge circuit are provided. In the memory cell array, memory cells are arranged in a matrix in the row direction and the column direction. The word line selects the memory cell in the row direction. The bit line selects the memory cell in the column direction. The sense amplifier circuit determines a value stored in the memory cell based on the state of the bit line. The charge / discharge circuit is formed in a well in which the memory cell array is disposed, and charges or discharges the bit line.

FIG. 1 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram showing a schematic configuration of a block of the nonvolatile semiconductor memory device of FIG. FIG. 3 is a timing chart showing an example of the discharge operation of the bit line of FIG. FIG. 4 is a block diagram illustrating a configuration example of the charge / discharge circuit of FIG. FIG. 5A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 5B is a nonvolatile semiconductor memory according to the second embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. FIG. 6 is a cross-sectional view taken along the line AA in FIG. FIG. 7A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the third embodiment, and FIG. 7B is a nonvolatile semiconductor memory according to the third embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. FIG. 8 is a cross-sectional view taken along the line BB in FIG. FIG. 9A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 9B is a nonvolatile semiconductor memory according to the fourth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. FIG. 10A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the fifth embodiment, and FIG. 10B is a nonvolatile semiconductor memory according to the fifth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. FIG. 11A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the sixth embodiment, and FIG. 11B is a nonvolatile semiconductor memory according to the sixth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. FIG. 12 is a block diagram illustrating a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the seventh embodiment.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment will be described with reference to the drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment.
Referring to FIG. 1, the nonvolatile semiconductor memory device includes a memory cell array 1, a row selection circuit 2, a charge / discharge circuit 3, a column selection circuit 5, a data input / output buffer 6, a control circuit 7, and a sense amplifier circuit 8. Yes.

  In the memory cell array 1, memory cells for storing data are arranged in a matrix in the row direction RD and the column direction CD. Note that one memory cell may store data for 1 bit, or may be multi-valued so that data of 2 bits or more can be stored.

  Here, the memory cell array 1 has n (n is a positive integer) blocks B1 to Bn. Each of the blocks B1 to Bn can be configured by arranging a plurality of NAND cell units in the row direction.

FIG. 2 is a circuit diagram showing a schematic configuration of a block of the nonvolatile semiconductor memory device of FIG.
In FIG. 2, each block B1 to Bn is provided with h (h is a positive integer) number of word lines WL1 to WLh, select gate lines SGD and SGS, and a source line SCE. Further, m (m is a positive integer) bit lines BL1 to BLm are commonly provided in each of the blocks B1 to Bn.

  Each block B1 to Bn includes m NAND cell units NU1 to NUm, and the NAND cell units NU1 to NUm are connected to the bit lines BL1 to BLm, respectively.

  Here, cell transistors MT1 to MTh and select transistors MS1 and MS2 are provided in the NAND cell units NU1 to NUm, respectively. One memory cell of the memory cell array 1 can be composed of one cell transistor. The NAND strings are configured by connecting the cell transistors MT1 to MTh in series, and the NAND transistors NU1 to NUm are configured by connecting the select transistors MS1 and MS2 to both ends of the NAND string. .

  In each NAND cell unit NU1 to NUm, word lines WL1 to WLh are connected to the control gate electrodes of the cell transistors MT1 to MTh, respectively. In each NAND cell unit NU1 to NUm, one end of the NAND string including the cell transistors MT1 to MTh is connected to the bit lines BL1 to BLm via the select transistor MS1, and the other end of the NAND string is connected to the select transistor MS2. To the source line SCE.

  In FIG. 1, a row selection circuit 2 can select a word line WL during a read / write erase operation of a memory cell. The charge / discharge circuit 3 can charge or discharge the bit lines BL1 to BLm during a read / write operation of the memory cell. The charge / discharge circuit 3 is formed in the well WEL in which the memory cell array 1 is disposed. Further, the charge / discharge circuit 3 can charge or discharge the bit lines BL1 to BLm in cooperation with the charge operation or discharge operation of the bit lines BL1 to BLm by the sense amplifier circuit 8. The column selection circuit 5 can select the bit line BL during the memory cell read / write erase operation. The sense amplifier circuit 8 determines data stored in the memory cell based on the states of the bit lines BL1 to BLm. The sense amplifier circuit 8 may be voltage sense or current sense. The data input / output buffer 6 sends commands and addresses received from the outside to the control circuit 7 and exchanges data between the sense amplifier circuit 8 and the outside.

  The control circuit 7 controls operations of the row selection circuit 2, the charge / discharge circuit 3, the column selection circuit 5, the data input / output buffer 6, and the sense amplifier circuit 8 based on the command and the address. Here, the control circuit 7 includes a write control unit 7a, a read control unit 7b, and a charge / discharge control unit 7c.

  The write controller 7a can control the write operation of the memory cell. The read controller 7b can control the read operation of the memory cell. The charge / discharge control unit 7 c can control the charge operation and the discharge operation of the charge / discharge circuit 3 and the sense amplifier circuit 8. The write operation and the read operation are performed in units of a plurality of memory cells (pages) sharing the word line.

  In the write operation, a program voltage (for example, 20V) is applied to the selected word line of the selected block, and an intermediate voltage (for example, 10V) sufficient to turn on the cell transistor is applied to the unselected word line. For channel cut, a low voltage for preventing the cell transistor from being turned on may be applied to a part of the unselected word line. In addition, a write voltage (for example, 0 V) or a write inhibit voltage (for example, 2.5 V) is applied to the selected bit line according to the data to be written.

  The select gate line SGD has a voltage at which the selected cell is turned on when it is desired to increase the threshold value of the selected cell, and at which the selected cell is turned off when it is not desired to increase the threshold value of the selected cell. .5V is applied. Also, a low voltage sufficient to turn off the select transistor MS1 is applied to the select gate line SGS.

  When the write voltage is applied to the selected bit line, a high voltage is applied to the control gate electrode of the selected cell, and the write operation of the selected cell is executed.

  On the other hand, when the write inhibit voltage is applied to the selected bit line, the select transistor MS2 is turned off. As a result, the potential of the channel of the selected cell connected to the selected word line rises due to self-boost, and the write inhibit operation for the selected cell is executed.

  In the read operation, a read voltage (for example, 0 V) is applied to the selected word line of the selected block, and an intermediate voltage (for example, 4.5 V) sufficient to turn on the unselected cell is applied to the unselected word line. Is done. Further, an intermediate voltage (for example, 4.5 V) sufficient to turn on the select transistor MS2 is applied to the select gate line SGD, and 0 V is applied to SGS. Further, a precharge voltage (for example, 1.5 V) is applied to the selected bit line, and a source voltage (a voltage lower than the bit line precharge voltage, for example, 1.2 V) is applied to the source line SCE.

  Next, when an intermediate voltage (for example, 4.5 V) sufficient to turn on MS1 is applied to SGS, if the threshold value of the selected cell does not reach the read level, the charge charged in the selected bit line Is discharged through the NAND string, and the potential of the selected bit line becomes low level. On the other hand, when the threshold value of the selected cell has reached the read level, the electric charge charged in the selected bit line is not discharged through the NAND string, so the potential of the selected bit line is kept at the high level.

Then, by determining whether the potential of the selected bit line is low level or high level, it is determined whether the threshold value of the selected cell has reached the read level, and the data stored in the selected cell is read.
Note that the read operation may be voltage sensing or current sensing. In the case of current sensing, by applying a precharge voltage to the selected bit line and applying an intermediate voltage sufficient to turn on the select transistor MS1 to the select gate SGS, the cell current (cell current) is reduced. The data stored in the cell is read by determining the amount of the cell current flowing through the bit line.

  In the erase operation, 0V is applied to the word lines WL1 to WLh of the selected block, and the well potential of the selected block is set to the erase voltage (for example, 17V). Further, the source line SCE and select gate lines SGD and SGS of the selected block can be set in a floating state.

  At this time, a high voltage is applied between the well WEL of the memory cell of the selected block and the control gate electrode. For this reason, the erase operation of the memory cell of the selected block is executed.

  Here, the discharge operation of the bit lines BL1 to BLm is performed in order to reset the potential of the bit lines BL1 to BLm after the end of the write operation, the read operation, and the erase operation. Further, in the read operation, in order to reduce coupling noise between the bit lines BL1 to BLm, a discharge operation of the unselected bit lines is performed. Further, in the write operation, the non-selected bit line is charged in order to deselect the non-selected bit line.

  At this time, the charge / discharge circuit 3 charges and discharges the bit lines BL1 to BLm in cooperation with the charge and discharge operations of the bit lines BL1 to BLm by the sense amplifier circuit 8. Thereby, compared with the case where only the sense amplifier circuit 8 charges / discharges the bit lines BL1 to BLm, the charge / discharge time can be shortened, and the charge / discharge operation can be speeded up. For example, by connecting the sense amplifier circuit 8 to one end of the bit lines BL1 to BLm and connecting the charge / discharge circuit 3 to the other end of the bit lines BL1 to BLm, the CR load of the bit lines BL1 to BLm is reduced to ¼. Can be reduced. C is a parasitic capacitance of the bit lines BL1 to BLm, and R is a parasitic resistance of the bit lines BL1 to BLm.

  Further, by forming the charge / discharge circuit 3 in the well WEL in which the memory cell array 1 is arranged, the charge / discharge circuit 3 can be reduced in voltage compared to the case where the charge / discharge circuit 3 is formed outside the well WEL. The layout area can be reduced.

FIG. 3 is a timing chart showing an example of the discharge operation of the bit line of FIG.
In FIG. 3, in the discharge operation of the bit line BL, a discharge instruction signal BJ instructing the start of discharge of the bit line BL is sent from the control circuit 7 to the charge / discharge circuit 3, and at the same time, the discharge instruction signal BS is sent from the control circuit 7 to the sense amplifier. It is sent to the circuit 8. Then, the bit line BL is discharged through the charge / discharge circuit 3 and the sense amplifier circuit 8, and the potential of the bit line BL is reset.

FIG. 4 is a block diagram illustrating a configuration example of the charge / discharge circuit of FIG.
In FIG. 4, the charge / discharge circuit 3 is provided with charge / discharge transistors JT1 to JTm for each of the bit lines BL1 to BLm. As the charge / discharge transistors JT1 to JTm, for example, N-channel field effect transistors can be used. Here, the sources of the charge / discharge transistors JT1 to JTm are connected to the bit lines BL1 to BLm, and the drains of the charge / discharge transistors JT1 to JTm are connected to the source line SCE. Discharge instruction signal BJ is input to the gates of charge / discharge transistors JT1 to JTm. When the discharge instruction signal BS becomes “H” level, the bit lines BL1 to BLm are discharged through the sense amplifier circuit 8, and the potentials of the bit lines BL1 to BLm gradually decrease (dotted line). At this time, when the discharge instruction signal BJ becomes “H” level and the charge / discharge transistors JT1 to JTm are turned on, the bit lines BL1 to BLm are also discharged by the charge / discharge transistors JT1 to JTm, and the discharge instruction signal BJ becomes “L” level. In this case (dotted line), the potentials of the bit lines BL1 to BLm rapidly decrease (solid line).

(Second Embodiment)
FIG. 5A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 5B is a nonvolatile semiconductor memory according to the second embodiment. FIG. 6 is a cross-sectional view taken along the line AA in FIG. 5B, showing a layout configuration example of a charge / discharge circuit applied to the apparatus. In FIG. 5B, the case where four bit lines BL1 to BL4 are arranged is taken as an example. Further, in FIG. 5A and FIG. 6, the portion of the bit line BL2 is extracted and shown.
5A, 5B and 6, the well WEL1 is provided with a memory cell array region R2 and a charge / discharge transistor region R1. Here, the element isolation layer 23 is formed in the well WEL1. The memory cell array region R2 and the charge / discharge transistor region R1 are element-isolated by the element isolation layer 23. The element isolation layer 23 can use, for example, an STI (Shallow Trench Isolation) structure.

  In the memory cell array region R2, active regions AK separated in the row direction are formed in the well WEL1, and bit lines BL1 to BL4 are arranged on each active region AK.

  In each active region AK, the charge storage layer 15 and the select gate electrodes 19 and 20 are disposed on the well WEL1, and the control gate electrode 16 is disposed on the charge storage layer 15. The well WEL1 and the charge storage layer 15 can be insulated through a tunnel insulating film (not shown). The charge storage layer 15 and the control gate electrode 16 can be insulated via an interelectrode insulating film (not shown). Here, one charge storage layer 15 and the control gate electrode 16 thereon can constitute one memory cell.

  In the well WEL1, impurity diffusion layers 12, 13, and 14 disposed between the charge storage layers 15 or between the charge storage layer 15 and the select gate electrodes 19 and 20 are formed.

  The impurity diffusion layer 13 is connected to the bit line BL2 via the contact electrode 18, and the impurity diffusion layer 14 is connected to the source line SCE via the contact electrode 17. The control gate electrode 16 of each memory cell is connected to the word lines WL1 to WLl, and the select gate electrodes 19 and 20 are connected to the select gate lines SGD and SGS, respectively.

  On the other hand, a charge / discharge transistor JT2 is formed in the charge / discharge transistor region R1, and the charge / discharge transistor JT2 is connected to the bit line BL2. Here, the gate electrode GH1 is formed on the well WEL1. In the well WEL1, impurity diffusion layers 24 and 25 are formed so as to sandwich the channel region under the gate electrode GH1. For example, the well WEL1 can be formed in a P-type, and the impurity diffusion layers 12, 13, 14, 24, and 25 can be formed in an N-type. The impurity diffusion layer 24 is connected to the bit line BL 2 via the contact electrode 21, and the impurity diffusion layer 25 is connected to the source line SCE via the contact electrode 22.

  Here, by forming the charge / discharge transistor JT2 in the well WEL1 in which the memory cell array region R2 is disposed, the charge / discharge transistor JT2 can have a lower withstand voltage compared to the case where the charge / discharge transistor JT2 is formed outside the well WEL1. The layout area of JT2 can be reduced.

(Third embodiment)
FIG. 7A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the third embodiment, and FIG. 7B is a nonvolatile semiconductor memory according to the third embodiment. FIG. 8 is a plan view showing a layout configuration example of a charge / discharge circuit applied to the apparatus, and FIG. 8 is a cross-sectional view taken along the line BB in FIG. In FIG. 7B, the case where four bit lines BL1 to BL4 are arranged is taken as an example. Further, in FIG. 7A and FIG. 8, the portion of the bit line BL2 is extracted and shown.
7A, 7B and 8, the well WEL2 is provided with a memory cell array region R12 and a charge / discharge transistor region R11. In the memory cell array region R12, active regions AK separated in the row direction are formed in the well WEL2, and bit lines BL1 to BL4 are arranged on each active region AK.

  In each active region AK, the charge storage layer 15 and the select gate electrodes 19 and 20 are disposed on the well WEL2, and the control gate electrode 16 is disposed on the charge storage layer 15. In the well WEL2, impurity diffusion layers 12, 13, and 14 disposed between the charge storage layers 15 or between the charge storage layers 15 and the select gate electrodes 19 and 20 are formed.

  The impurity diffusion layer 13 is connected to the bit line BL2 via the contact electrode 18, and the impurity diffusion layer 14 is connected to the source line SCE via the contact electrode 17. The control gate electrode 16 of each memory cell is connected to the word lines WL1 to WLl, and the select gate electrodes 19 and 20 are connected to the select gate lines SGD and SGS, respectively.

  On the other hand, in the charge / discharge transistor region R11, the charge / discharge transistor JT2 is formed in the active region AK, and the charge / discharge transistor JT2 is connected to the bit line BL2. That is, the NAND cell unit NU and the charge / discharge transistor are formed in the active region AK extending in the column direction CD. Here, the gate electrode GH2 of the charge / discharge transistor JT2 is formed on the active region AK. In the active region AK, impurity diffusion layers 28 and 29 are formed so as to sandwich the channel region under the gate electrode GH2. For example, the well WEL2 can be formed in a P-type, and the impurity diffusion layers 12, 13, 14, 28, and 29 can be formed in an N-type. The impurity diffusion layer 28 is connected to the bit line BL2 via the contact electrode 26, and the impurity diffusion layer 29 is connected to the source line SCE via the contact electrode 27.

  An isolation transistor IT2 is formed in the active region AK between the memory cell array region R12 and the charge / discharge transistor region R11. Here, the source of the isolation transistor IT2 is connected to the source of the select transistor MS1, and the drain of the isolation transistor IT2 is connected to the drain of the charge / discharge transistor JT2. A well potential EL of the well WEL2 is applied to the gate of the isolation transistor IT2.

  Here, the gate electrode GW1 of the isolation transistor IT2 is formed in the active region AK. The gate electrode GW1 can be disposed between the impurity diffusion layers 14 and 28. When the well potential EL is applied to the gate electrode GW1 of the isolation transistor IT2, the isolation transistor IT2 is turned off, and the memory cell array region R12 and the charge / discharge transistor region R11 are electrically separated.

  Here, by forming the charge / discharge transistor JT2 in the active region AK in which the memory cells are formed, the layout area of the charge / discharge transistor JT2 can be reduced. Further, by providing the isolation transistor IT2 in the active region AK, the memory cell array region R12 and the charge / discharge transistor region R11 can be electrically separated without cutting the active region AK.

  In the examples of FIGS. 7A, 7B, and 8, the isolation transistor IT2 is provided in the active region AK in order to electrically isolate the memory cell array region R12 and the charge / discharge transistor region R11. Although the method has been described, the active region AK may be cut between the memory cell array region R12 and the charge / discharge transistor region R11.

(Fourth embodiment)
FIG. 9A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the fourth embodiment, and FIG. 9B is a nonvolatile semiconductor memory according to the fourth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. In FIG. 9B, the case where four bit lines BL1 to BL4 are arranged is taken as an example. In FIG. 9A, the bit lines BL1 and BL2 are extracted and shown.
In FIG. 9A and FIG. 9B, the well WEL3 is provided with a memory cell array region R22 and a charge / discharge transistor region R21. In the memory cell array region R22, active regions AK separated in the row direction are formed in the well WEL3. Bit lines BL1 to BL4 are arranged on each active region AK and orthogonal to the bit lines BL1 to BL4. Thus, select gate lines SGS and SGD and word lines WL1 to WLh are formed. Here, on the source side of the select gate line SGS, the source line SCE is connected to the active region AK via the contact electrode 31.

  On the other hand, in the charge / discharge transistor region R21, charge / discharge transistors JT11 and JT12, unused transistors UT11 and UT12, and isolation transistors IT11 and IT12 are formed in the active region AK. Here, the charge / discharge transistor JT11, the isolation transistor IT11, and the unused transistor UT11 are sequentially connected in series, and the source of the unused transistor UT11 is connected to the source side of the select gate line SGS. The unused transistor UT12, the isolation transistor IT12, and the charge / discharge transistor JT12 are sequentially connected in series, and the source of the charge / discharge transistor JT12 is connected to the source side of the select gate line SGS. The well potential EL of the well WEL3 is applied to the gates of the isolation transistors IT11 and IT12. Discharge instruction signals BJ1 and BJ2 are applied to the gates of the charge / discharge transistors JT11 and JT12, respectively.

  Here, on the active region AK, gate electrodes GH12 and GH11 of the charge / discharge transistors JT11 and JT12 and gate electrodes GW11 of the isolation transistors IT11 and IT12 are formed. Here, the gate electrode GW11 is disposed between the gate electrodes GH12 and GH11. The gate electrode GH12 is shared by the charge / discharge transistor JT11 and the unused transistor UT12. The gate electrode GH11 is shared by the charge / discharge transistor JT12 and the unused transistor UT11.

  The odd-numbered bit lines BL1 and BL3 are connected to the active region AK between the gate electrodes GW11 and GH12 via the contact electrode 33, and the even-numbered bit lines BL2 and BL4 are connected to the gate electrode GW11, It is connected to the active area AK between GH11. The active region AK on the drain side of the gate electrode GH12 is connected to the source line SCE via the contact electrode 32.

  When the well potential EL is applied to the gate electrode GW11 of the isolation transistors IT11 and IT12, the isolation transistors IT11 and IT12 are turned off. For this reason, the charge / discharge transistor JT11 and the unused transistor UT12 are electrically separated from the unused transistor UT11 and the charge / discharge transistor JT12.

  Here, in the configurations of FIG. 9A and FIG. 9B, selection and non-selection are alternately switched between the odd-numbered bit lines BL1 and BL3 and the even-numbered bit lines BL2 and BL4. Here, for example, when even-numbered bit lines BL2 and BL4 are selected, the even-numbered bit lines BL2 and BL4 are set by setting the potential of the discharge instruction signal BJ2 so that the charge / discharge transistor JT12 is cut off. Thus, the read operation can be normally performed. At this time, by setting the potential of the discharge instruction signal BJ1 so that the charge / discharge transistor JT11 is turned on, the charge / discharge of the unselected odd-numbered bit lines BL1 and BL3 via the sense amplifier circuit 8 and the charge / discharge transistor JT11. The operation can be performed, and the charge / discharge operation can be speeded up. For example, in the write operation, the charge operation of the unselected odd-numbered bit lines BL1 and BL3 is performed via the sense amplifier circuit 8 and the charge / discharge transistor JT11, thereby speeding up the charge operation of the unselected bit lines BL1 and BL3. Therefore, the time for deselecting the non-selected bit lines BL1 and BL3 can be shortened.

  In addition, by alternately switching selection and non-selection between the odd-numbered bit lines BL1 and BL3 and the even-numbered bit lines BL2 and BL4, the non-selected bit lines can be used as noise shields or when writing to the memory cells. It is possible to reduce inter-bit interference.

(Fifth embodiment)
FIG. 10A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the fifth embodiment, and FIG. 10B is a nonvolatile semiconductor memory according to the fifth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. In FIGS. 10A and 10B, the case where four bit lines BL1 to BL4 are arranged is taken as an example.
10A and 10B, the well WEL4 is provided with a memory cell array region R32 and a charge / discharge transistor region R31. In the memory cell array region R32, active regions AK separated in the row direction are formed in the well WEL4. Bit lines BL1 to BL4 are arranged on the active regions AK and orthogonal to the bit lines BL1 to BL4. Thus, select gate lines SGS and SGD and word lines WL1 to WLh are formed. Here, the source line SCE is connected to the active region AK via the contact electrode 41 on the source side of the select gate line SGS.

  On the other hand, in the charge / discharge transistor region R31, charge / discharge transistors JT21 to JT24, unused transistors UT21 to UT24, and isolation transistors IT21 to IT24 are formed in the active region AK. Here, the charge / discharge transistor JT21, the isolation transistor IT21, and the unused transistor UT21 are sequentially connected in series, and the source of the unused transistor UT21 is connected to the source side of the select gate line SGS. The charge / discharge transistor JT22, the isolation transistor IT22, and the unused transistor UT22 are sequentially connected in series, and the source of the unused transistor UT22 is connected to the source side of the select gate line SGS. The unused transistor UT23, the isolation transistor IT23, and the charge / discharge transistor JT23 are sequentially connected in series, and the source of the charge / discharge transistor JT23 is connected to the source side of the select gate line SGS. The unused transistor UT24, the isolation transistor IT24, and the charge / discharge transistor JT24 are sequentially connected in series, and the source of the charge / discharge transistor JT24 is connected to the source side of the select gate line SGS. The well potential EL of the well WEL4 is applied to the gates of the isolation transistors IT21 to IT24. Discharge instruction signal BJ21 is applied to the gates of charge / discharge transistors JT21 and JT22, and discharge instruction signal BJ22 is applied to the gates of charge / discharge transistors JT23 and JT24.

  Here, on the active region AK, the gate electrodes GH21 of the charge / discharge transistors JT23 and JT24, the gate electrodes GH22 of the charge / discharge transistors JT21 and JT22, and the gate electrodes GW21 of the isolation transistors IT21 to IT24 are formed. Here, the gate electrode GW21 is disposed between the gate electrodes GH22 and GH21. The gate electrode GH22 is shared by the charge / discharge transistors JT21 and JT22 and the unused transistors UT23 and UT24. The gate electrode GH21 is shared by the charge / discharge transistors JT23 and JT24 and the unused transistors UT21 and UT22.

  The bit line BL1 is connected to the active region AK between the gate electrodes GW21 and GH22 via the contact electrode 43, and the bit line BL2 is connected to the active region AK between the gate electrodes GW21 and GH22 via the contact electrode 44. The bit line BL3 is connected to the active region AK between the gate electrodes GW21 and GH21 via the contact electrode 45, and the bit line BL4 is connected to the active region AK between the gate electrodes GW21 and GH21 via the contact electrode 46. The active region AK on the drain side of the gate electrode GH22 is connected to the source line SCE via the contact electrode.

  When the well potential EL is applied to the gate electrodes GW21 of the isolation transistors IT21 to IT24, the isolation transistors IT21 to IT24 are turned off. For this reason, the charge / discharge transistors JT21, JT22 and the unused transistors UT23, UT24 are electrically separated from the unused transistors UT21, UT22 and the charge / discharge transistors JT23, JT24.

  Here, in the configurations of FIGS. 10A and 10B, selection and non-selection are alternately performed between two adjacent bit lines BL1 and BL2 and two adjacent bit lines BL3 and BL4. Switched. Here, for example, when two bit lines BL3 and BL4 adjacent to each other are selected, the potential of the discharge instruction signal BJ21 is set so that the charge / discharge transistors JT23 and JT24 are cut off. The write operation can be normally performed through each of the bit lines BL3 and BL4. At this time, by setting the potential of the discharge instruction signal BJ21 so that the charge / discharge transistors JT21, JT22 are turned on, charging / discharging of the non-selected bit lines BL1, BL2 via the sense amplifier circuit 8 and the charge / discharge transistors JT21, JT22 is performed. The discharge operation can be performed, and the charge / discharge operation can be speeded up. For example, in the write operation, the charge operation of the unselected bit lines BL1 and BL2 is performed through the sense amplifier circuit 8 and the charge / discharge transistors JT21 and JT22, thereby speeding up the charge operation of the unselected bit lines BL1 and BL2. The time for deselecting the non-selected bit lines BL1 and BL2 can be shortened.

  Further, by alternately switching between selection and non-selection between the two bit lines BL1 and BL2 adjacent to each other and the two bit lines BL3 and BL4 adjacent to each other, inter-bit interference is reduced when writing to the memory cell. It becomes possible.

(Sixth embodiment)
FIG. 11A is a circuit diagram showing a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the sixth embodiment, and FIG. 11B is a nonvolatile semiconductor memory according to the sixth embodiment. It is a top view which shows the layout structural example of the charging / discharging circuit applied to an apparatus. In FIGS. 11A and 11B, the case where four bit lines BL1 to BL4 are arranged is taken as an example.
In FIG. 11A and FIG. 11B, the well WEL5 is provided with a memory cell array region R42 and a charge / discharge transistor region R41. In the memory cell array region R42, active regions AK separated in the row direction are formed in the well WEL5. Bit lines BL1 to BL4 are arranged on each active region AK and orthogonal to the bit lines BL1 to BL4. Thus, select gate lines SGS and SGD and word lines WL1 to WLh are formed. Here, on the source side of the select gate line SGS, the source line SCE is connected to the active region AK via the contact electrode 51.

  On the other hand, in the charge / discharge transistor region R41, charge / discharge transistors JT31 to JT34, unused transistors UT31 to UT34, UT41 to UT44, UT51 to UT54 and isolation transistors IT31 to IT34, IT41 to IT44 are formed in the active region AK. ing. Here, the unused transistor UT51, the isolation transistor IT41, the unused transistor UT41, the unused transistor UT31, the isolation transistor IT31, and the charge / discharge transistor JT31 are sequentially connected in series. The source of the charge / discharge transistor JT31 is the select gate line SGS. Connected to the source side. The unused transistor UT52, the isolation transistor IT42, the unused transistor UT42, the charge / discharge transistor JT32, the isolation transistor IT32, and the unused transistor UT32 are sequentially connected in series, and the source of the unused transistor UT32 is connected to the select gate line SGS. Connected to the source side. The unused transistor UT53, the isolation transistor IT43, the charge / discharge transistor JT33, the unused transistor UT43, the isolation transistor IT33, and the unused transistor UT33 are sequentially connected in series, and the source of the unused transistor UT33 is connected to the select gate line SGS. Connected to the source side. The charge / discharge transistor JT34, the isolation transistor IT44, the unused transistor UT54, the unused transistor UT44, the isolation transistor IT34, and the unused transistor UT34 are sequentially connected in series, and the source of the unused transistor UT34 is connected to the select gate line SGS. Connected to the source side. The well potential EL of the well WEL5 is applied to the gates of the isolation transistors IT31 to IT34 and IT41 to IT44. The discharge instruction signal BJ31 is applied to the gate of the charge / discharge transistor JT31, the discharge instruction signal BJ32 is applied to the gate of the charge / discharge transistor JT32, and the discharge instruction signal BJ33 is applied to the gate of the charge / discharge transistor JT33. The discharge instruction signal BJ34 is applied to the gate of the charge / discharge transistor JT34.

  Here, on the active region AK, the gate electrode GH31 of the charge / discharge transistor JT31, the gate electrode GH32 of the charge / discharge transistor JT32, the gate electrode GH33 of the charge / discharge transistor JT33, the gate electrode GH34 of the charge / discharge transistor JT34, and the isolation transistor IT31. To 34 and gate electrodes GW32 of the isolation transistors IT41 to IT44 are formed. Here, the gate electrode GW31 is disposed between the gate electrodes GH31 and GH32. The gate electrode GW32 is disposed between the gate electrodes GH33 and GH34. The gate electrode GH31 is shared by the charge / discharge transistor JT31 and the unused transistors UT32 to UT34. The gate electrode GH32 is shared by the charge / discharge transistor JT32 and the unused transistors UT31, UT43, UT44. The gate electrode GH33 is shared by the charge / discharge transistor JT33 and the unused transistors UT41, UT42, UT54. The gate electrode GH34 is shared by the charge / discharge transistor JT34 and the unused transistors UT51 to UT53.

  The bit line BL1 is connected to the active region AK between the gate electrodes GW31 and GH31 via the contact electrode 54, the bit line BL2 is connected to the active region AK between the gate electrodes GW31 and GH32 via the contact electrode 55, The bit line BL3 is connected to the active region AK between the gate electrodes GW32 and GH33 via the contact electrode 56, and the bit line BL4 is connected to the active region AK between the gate electrodes GW32 and GH34 via the contact electrode 57. The active region AK on the drain side of the gate electrode GH 34 is connected to the source line SCE via the contact electrode 53. The active region AK between the gate electrodes GH32 and GH33 is connected to the source line SCE via the contact electrode 52.

  When the well potential EL is applied to the gate electrode GW31 of the isolation transistors IT31 to IT34 and the gate electrode GW32 of the isolation transistors IT41 to IT44, the isolation transistors IT31 to IT34 and IT41 to IT44 are turned off. Therefore, the charge / discharge transistor JT31 and the unused transistors UT32, UT33, UT34, the charge / discharge transistors JT32, JT33, the unused transistors UT31, UT41-UT44, UT54, the charge / discharge transistor JT34, and the unused transistors UT51-UT53 Electrically separated.

  Here, in the configurations of FIGS. 11A and 11B, selection and non-selection can be alternately switched between the odd-numbered bit lines BL1 and BL3 and the even-numbered bit lines BL2 and BL4. Selection and non-selection can be alternately switched between two bit lines BL1 and BL2 adjacent to each other and two bit lines BL3 and BL4 adjacent to each other. For example, when the even-numbered bit lines BL2 and BL4 are selected, the even-numbered bit lines are set by setting the potentials of the discharge instruction signals BJ32 and BJ34 so that the charge / discharge transistors JT32 and JT34 are cut off. A read operation can be normally performed via BL2 and BL4. At this time, by setting the potentials of the discharge instruction signals BJ31 and BJ33 so that the charge / discharge transistors JT31 and JT33 are turned on, the odd-numbered bit lines that are not selected via the sense amplifier circuit 8 and the charge / discharge transistors JT31 and JT33. The charge / discharge operation of BL1 and BL3 can be performed, and the charge / discharge operation can be speeded up.

  Alternatively, for example, when two bit lines BL3 and BL4 adjacent to each other are selected, the potentials of the discharge instruction signals BJ33 and BJ34 are set so as to cut off the charge / discharge transistors JT33 and JT34. The write operation can be normally performed via the two bit lines BL3 and BL4. At this time, by setting the potentials of the discharge instruction signals BJ31 and JT32 so that the charge / discharge transistors JT31 and JT32 are turned on, the unselected bit lines BL1 and BL2 are connected via the sense amplifier circuit 8 and the charge / discharge transistors JT31 and JT32. The charge / discharge operation can be performed, and the charge / discharge operation can be speeded up.

(Seventh embodiment)
FIG. 12 is a block diagram illustrating a configuration example of a charge / discharge circuit applied to the nonvolatile semiconductor memory device according to the seventh embodiment. In FIG. 12, the case where two bit lines BL1 and BL2 are arranged is taken as an example.
In FIG. 12, a well WEL6, a charge / discharge driver DV, a sense amplifier circuit SA, and a power supply pad PD are formed in a semiconductor chip CP. The well WEL6 is provided with a memory cell array 1, selection transistors AT1, AT2, switching transistors BT1, BT2, and charge / discharge transistors JT11, JT12. For example, N-channel field effect transistors can be used as the selection transistors AT1 and AT2 and the switching transistors BT1 and BT2.

  The sense amplifier circuit SA can determine the value stored in the memory cell based on the state of the bit lines BL1 and BL2. The sense amplifier circuit SA may be voltage sense or current sense. The charge / discharge driver DV can charge or discharge the bit lines BL1 and BL2. The selection transistors AT1 and AT2 can connect a selection bit line to the sense amplifier circuit SA. The switching transistors BT1 and BT2 can connect a non-selected bit line to the charge / discharge driver DV. The power supply pad PD can supply power to the sense amplifier circuit SA and the charge / discharge driver DV.

  One end of the bit line BL1 is connected to the sense amplifier circuit SA via the selection transistor AT1 and to the charge / discharge driver DV via the switching transistor BT1. The other end of the bit line BL1 is connected to the charge / discharge transistor JT11. One end of the bit line BL2 is connected to the sense amplifier circuit SA via the selection transistor AT2 and to the charge / discharge driver DV via the switching transistor BT2. The other end of the bit line BL2 is connected to the charge / discharge transistor JT12. Selection signals BS1 and BS2 are applied to the gates of the selection transistors AT1 and AT2, respectively, and switching signals BA1 and BA2 are applied to the gates of the switching transistors BT1 and BT2, respectively.

  Here, the charge / discharge driver DV can be disposed closer to the power supply pad PD than the memory cell array 1. For example, the charge / discharge driver DV may be disposed adjacent to the power supply pad PD.

  For example, when the even-numbered bit line BL2 is selected, the potential of the discharge instruction signal BJ2 is set so that the charge / discharge transistor JT12 is cut off. Further, by turning on the selection transistor AT2 and turning off the switching transistor BT2, the bit line BL2 can be connected to the sense amplifier circuit SA, and the read operation can be normally performed via the even-numbered bit line BL2. . At this time, the potential of the discharge instruction signal BJ1 is set so that the charge / discharge transistor JT11 is turned on, the selection transistor AT1 is turned off, and the switching transistor BT1 is turned on, so that the bit line is connected to the charge / discharge driver DV and the charge / discharge transistor JT11. BL1 can be connected. For this reason, the charge / discharge operation of the unselected odd-numbered bit line BL1 can be performed via the charge / discharge driver DV and the charge / discharge transistor JT11, and the charge / discharge operation can be speeded up.

  Here, by disposing the charge / discharge driver DV closer to the power supply pad PD than to the memory cell array 1, the wiring resistance between the power supply pad PD and the discharge driver DV can be reduced, and the charge / discharge driver DV is charged. The discharge operation can be speeded up.

(Eighth embodiment)
When conducting the energization test of the charge / discharge transistors JT1 to JTm in FIG. 4, the charge / discharge transistors JT1 to JTm are turned on in a state where all the memory cells of the memory cell array 1 are not selected, and the charge / discharge transistors JT1 to JTm are respectively Then, the bit lines BL1 to BLm are charged. Then, after the charge / discharge transistors JT1 to JTm are turned off, the quality of the charge / discharge transistors JT1 to JTm may be determined by determining the state of the bit lines BL1 to BLm via the sense amplifier circuit 8.

  At this time, for example, if the charge / discharge transistor JT1 has an open defect, the bit line BL1 is not charged, so the potential of the bit line BL1 becomes low. Therefore, it is possible to detect an open failure of the charge / discharge transistor JT1 by determining whether or not the potential of the bit line BL1 is lower than the determination value.

  Here, the high resistance failure can be detected by adjusting the parameters of the sense amplifier circuit 8 so that the charge / discharge transistors JT1 to JTm return pass / fail with the on-current necessary for performing a desired operation as a boundary. . When a failure of the charge / discharge transistors JT1 to JTm is detected, the redundancy column may be replaced in units of the bit lines BL1 to BLm.

  Further, when a short circuit failure of the charge / discharge transistors JT1 to JTm is detected, the charge / discharge transistors JT1 to JTm are turned off in a state where all the memory cells in the memory cell array 1 are not selected. Then, the bit lines BL1 to BLm are charged via the sense amplifier circuit 8.

  At this time, for example, when there is a short circuit failure in the charge / discharge transistor JT1, the electric charge charged in the bit line BL1 leaks through the charge / discharge transistor JT1, so the potential of the bit line BL1 decreases. Therefore, it is possible to detect a short circuit failure of the charge / discharge transistor JT1 by determining whether or not the potential of the bit line BL1 is lower than the determination value.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 memory cell array, B1-Bn block, 2 row selection circuit, 3 charge / discharge circuit, 5 column selection circuit, 6 data input / output buffer, 7 control circuit, 7a write control unit, 7b read control unit, 7c charge / discharge control unit, 8, SA sense amplifier circuit, MS1, MS2 select transistor, MT1-MTh cell transistor, WL1-WLh word line, SGD, SGS select gate line, SCE source line, BL1-BLm bit line, NU1-NUm NAND cell unit, JT1 ~ JTm charge / discharge transistor, WEL, WEL1 ~ WEL6 well, CP semiconductor chip, AK active region, GH1, GH2, GW1 gate electrode, 12-14, 24, 25, 28, 29 impurity diffusion layer, 15 charge storage layer, 16 Control gate electrode, 17, 18, 21, 22, 26, 27 Contact electrode, 19, 20 Select gate electrode, 23 Device isolation layer, IT2 isolation transistor, PD power pad, DV charge / discharge driver, AT1, AT2 selection transistor, BT1, BT2 switching Transistor

Claims (5)

A memory cell array in which memory cells are arranged in a matrix in the row direction and the column direction;
A word line for selecting the memory cell in the row direction;
A bit line for selecting the memory cells in the column direction;
A sense amplifier circuit for determining a value stored in the memory cell based on a state of the bit line;
A charge / discharge circuit that charges or discharges the bit line in cooperation with a charge operation or discharge operation of the bit line by the sense amplifier circuit;
The charge / discharge circuit is formed in a well in which the memory cell array is disposed,
One end of the bit line is connected to the sense amplifier circuit, and the other end of the bit line is connected to the charge / discharge circuit. A memory cell array in which memory cells are arranged in a matrix in the row direction and the column direction;
A word line for selecting the memory cell in the row direction;
A bit line for selecting the memory cells in the column direction;
A sense amplifier circuit for determining a value stored in the memory cell based on a state of the bit line;
A non-volatile semiconductor memory device comprising: a charge / discharge circuit that charges or discharges the bit line in cooperation with a charge operation or discharge operation of the bit line by the sense amplifier circuit. A memory cell array in which memory cells are arranged in a matrix in the row direction and the column direction;
A word line for selecting the memory cell in the row direction;
A bit line for selecting the memory cells in the column direction;
A sense amplifier circuit for determining a value stored in the memory cell based on a state of the bit line;
A non-volatile semiconductor memory device comprising: a charge / discharge circuit that is formed in a well in which the memory cell array is disposed and charges or discharges the bit line.   The charge / discharge is performed by charging the bit line through the charge / discharge circuit and determining the potential of the bit line through the sense amplifier circuit in a state where all the memory cells of the memory cell array are not selected. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the quality of the circuit is determined. A memory cell array in which memory cells are arranged in a matrix in the row direction and the column direction;
A word line for selecting the memory cell in the row direction;
A bit line for selecting the memory cells in the column direction;
A sense amplifier circuit for determining a value stored in the memory cell based on a state of the bit line;
A charge / discharge driver for charging or discharging the bit line;
A selection transistor for connecting a selection bit line to the sense amplifier circuit;
A switching transistor for connecting a non-selected bit line to the charge / discharge driver;
A power pad for supplying power to the sense amplifier circuit and the charge / discharge driver,
The nonvolatile semiconductor memory device, wherein the charge / discharge driver is disposed closer to the power supply pad than the memory cell array.

Images