JP2013229693A - Bit phase synchronous circuit and receiver unit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit phase synchronous circuit capable of significantly facilitating a circuit without using a squelch circuit or the like and of exactly performing bit synchronization for received data in a short time.SOLUTION: The bit phase synchronous circuit, which develops a clock signal subject to bit phase synchronization for received data, includes: means for developing a clock signal of a frequency with a phase resolution capable of identifying a bit phase of the received data; means for sampling a timing level to be compared with a predetermined threshold value of the received data according to the clock signal; and means for comparing the sampling level with the threshold value and controlling a phase of the clock signal according to the comparative result.

Description

  The present invention relates to a bit phase synchronization circuit and a receiving apparatus using the same, and more particularly to a bit phase synchronization circuit for a demodulated clock signal required for demodulating received data in a receiving apparatus that performs burst communication.

  For example, as shown in the uppermost stage of FIG. 6, in a receiving apparatus in a communication system that performs communication in which a non-signal period and a signal period are mixed to form data in bursts, the data is output from a demodulator during the non-signal period. In order to block noise, it is necessary to configure a squelch circuit inside the receiving apparatus.

  On the other hand, for demodulating data in the signal period, it is necessary to generate a demodulated clock that is synchronized with the bit phase of the data. To generate a demodulated clock that is synchronized with the bit phase, high speed is required. In particular, when the signal period is shorter than the no-signal period, such a requirement becomes significant.

  Patent Documents 1 and 2 propose a bit phase synchronization circuit that generates a demodulation clock for demodulating received data in such a burst communication system.

JP 09-149018 A Japanese Patent Laid-Open No. 11-317732

  In the technique using the squelch circuit described above, when the squelch circuit is configured, if the signal to be received is extremely weak or buried in noise, reception may not be possible, and sufficient reception sensitivity is obtained. There are cases where it cannot be secured. In addition, since the squelch circuit is configured, there is a problem that the circuit scale increases. Also in the techniques of Patent Documents 1 and 2, the circuit configuration is extremely complicated, and a bit phase synchronization circuit having a simple circuit configuration is desired.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a bit phase synchronization circuit capable of constructing a circuit very easily without using a squelch circuit and the like and capable of performing bit synchronization with respect to received data in a very short time and a receiving apparatus using the same. Is to provide.

The bit phase synchronization circuit according to the present invention comprises:
A bit phase synchronization circuit that generates a clock signal in which bit phase synchronization is performed on received data,
Means for generating a clock signal having a frequency having a phase resolution capable of identifying the bit phase of the received data;
Sampling means for sampling a level of timing to be compared with a predetermined threshold value of the received data by the clock signal;
Control means for comparing the sampling level with the threshold value and controlling the phase of the clock signal according to the comparison result;
It is characterized by including.

The receiving device according to the present invention is:
The clock signal of the bit phase synchronization circuit is used as a sampling clock for demodulating received data.

  According to the present invention, it is possible to generate an accurate demodulation clock in a short time without using a squelch circuit and with an extremely simple configuration, thereby reducing the frequency of erroneous data detection due to noise.

It is a functional block diagram of the receiver which applied the bit phase locked loop circuit of embodiment of this invention. It is a block diagram which shows the example of the signal processing part of FIG. It is a wave form diagram which shows the operation | movement of embodiment of this invention, and is a figure which shows an example of the relationship between an analog signal (Biphi-L) and a demodulation clock, and the demodulation clock is synchronizing correctly with the bit phase of received data. It is an example of a state. It is a figure which shows an example of the relationship between an analog signal (Biphi-L) and a demodulation clock, and is an example of the state in which the bit phase of reception data is advanced with respect to the demodulation clock. It is a figure which shows the other example of the relationship between an analog signal (Biphi-L) and a demodulation clock, and is an example of the state in which the bit phase of reception data is behind with respect to a demodulation clock. It is a figure for demonstrating operation | movement of the receiver of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a receiving apparatus to which a bit phase synchronization circuit according to an embodiment of the present invention is applied. Referring to FIG. 1, the receiving apparatus includes an antenna 3, a receiving unit 2, and a signal processing unit 1.

  The reception unit 2 includes a low noise amplification circuit 4, a mixer 5, an oscillation circuit 6, an intermediate frequency detection circuit 7, and a power amplification circuit 8. The signal processing unit 1 includes a digital PLL circuit 9 and a demodulation circuit 10.

  A transmission wave from the mother machine, which is a transmitter, is received by the antenna 3 and input to the low noise amplifier circuit 4. The input received wave is amplified to a desired power by the low noise amplifier circuit 4 and input to the mixer 5, where it is mixed with the oscillation frequency of the oscillation circuit 6 to obtain an intermediate frequency component. It is done. In the intermediate frequency detection circuit 7, the Biφ-L analog signal is demodulated from this intermediate frequency component, amplified to a desired power by the power amplification circuit 8, band-limited by a band filter, and supplied to the signal processing unit 1. Will be.

  In the signal processing unit 1, the input analog signal is converted into a Biφ-L digital signal by the digital PLL circuit 9. Further, the Biφ-L digital signal is demodulated into NRZ-L reception data by the demodulation circuit 10 and output as reception data.

  FIG. 2 is a block diagram showing details of the signal processing unit 1 shown in FIG. The digital PLL circuit 9 constituting this signal processing unit includes an A / D converter 11, latch circuits 12 to 14 having a three-stage cascade configuration, a threshold determination circuit 15, and a demodulation clock generation circuit 16. Yes.

  In the demodulation circuit 10, the Biφ-L digital signal that is the output of the A / D converter 11 is sampled and demodulated into NRZ-L reception data by the demodulation clock generated by the demodulation clock generation circuit 16. Therefore, the demodulated clock needs to be bit-phase synchronized with the received data. In the present invention, the digital PLL circuit 9 converts the demodulated clock into a Biφ-L digital signal that is the output of the A / D converter 11. A demodulated clock that is synchronized in bit phase is generated.

  Here, when the data bit rate in the communication system is (F) bps, the demodulated Biφ-L digital signal can be regarded as (F × 2) bps NRZ-L data. In order to establish bit phase synchronization for such a signal, an oscillation circuit 17 having a frequency capable of sufficiently identifying the bit phase of received data and ensuring a phase resolution is provided, and the oscillation frequency of the oscillation circuit 17 is provided. Is the frequency of the sampling clock.

  When the oscillation frequency of the oscillation circuit 17 is (F × A), the phase for one bit period is (360 / A) degrees. Note that the value of A is selected so that (F × A) can sufficiently secure the phase resolution, and in this example, A = 4 is selected to be four times the system frequency. . Therefore, the demodulation clock generation circuit 16 provided in the digital PLL circuit 9 also sets its reference frequency to (F × 4) Hz, and the demodulation circuit 10 samples data at the frequency of this clock. .

  The latch circuits 12 to 14 sequentially sample the output of the A / D converter 11 based on the oscillation clock of the oscillation circuit 17, the latch circuit 12 receives the (N + 1) th data, and the latch circuit 13 uses (N). The latch circuit 14 samples the (N-1) th data and the (N-1) th data. That is, the received data is sampled and latched at the timing of three consecutive clock signals.

  The threshold value comparison circuit 15 compares the sampling data of the latch circuits 12 to 14 with the threshold value to determine the progress or delay state between the phase of the demodulated clock and the bit phase of the data. The phase of the demodulated clock of the demodulated clock generation circuit 16 is controlled. The operation state in that case is shown in FIGS.

  As shown in FIG. 3, in an ideal state (a state where the phase of the demodulation clock matches the phase of the received data), the sampled (N) th data matches the threshold value. That is, since the (N) -th sampling data matches the threshold value 0, the phase control of the demodulation clock is not performed. However, when the received data is advanced with respect to the demodulated clock, the relationship between the (N) th sampling data and the threshold value is as shown in FIG. 4, and conversely, the received data is advanced with respect to the demodulated clock. In the delayed state, the relationship between the (N) th sampling data and the threshold value is as shown in FIG.

  That is, the relationship between the phase advance / lag of the demodulated clock and the received data and the magnitude thereof is determined by the sign and absolute value of the level difference of the comparison result between the (N) th sampling data and the threshold value. Become. Therefore, the threshold determination circuit 15 determines the clock of the clock generation circuit 16 so that the phase of the demodulation clock matches the phase of the data according to the comparison determination result between the (N) th sampling data and the threshold. Phase control is performed.

  The reason for sampling the (N + 1) th, (N) th, and (N-1) th data is to identify the (N) th data to be compared with the threshold 0, and (N + 1) ) Th and (N-1) th are used for determining whether the level is 0 (based on threshold 0) as a high level or a low level, respectively. . This high / low level refers to a level roughly corresponding to the upper limit value / lower limit value in the signal waveform of Biφ-L in FIGS.

  In the above example, A = 4 is selected to detect the upper and lower limits of the data and the threshold, but a faster clock frequency such as A = 8 or 16 is selected. Thus, the detection accuracy may be increased.

  FIG. 6 is a diagram for illustrating the overall operation of the bit phase synchronization circuit described above, and shows the relationship with the communication format. In other words, the operation of the digital PLL circuit 9 is started by the preamble of the signal period, and immediately, the phase of the bit phase of the received data and the demodulated clock are synchronized, and the data ( In the (data) period, the frequency phase of the demodulation clock is fixed to that of the system.

  If the signal period is shorter than the no-signal period of the system, it is necessary to set the tracking speed of the digital PLL circuit to a certain degree faster. However, the adjustment of the tracking speed is very severe, and if the adjustment is incorrect, there is no need to do so. It may lead to a false detection during the signal period or a situation where synchronization cannot be achieved during the signal period. Therefore, in the present invention, as described above, a system is adopted in which the frequency is set to a fixed value of the system in the data period using the SYNC code used in the communication format as a trigger.

  As described above, in the present invention, the follow-up speed of the digital PLL circuit can be made variable, and a demodulated clock can be obtained at high speed even in burst communication with a short signal period.

  It is obvious that the present invention can be applied to a bit phase synchronization circuit of a demodulated clock of various receiving devices by changing the configuration of the receiving unit 2 shown in FIG.

1 Signal processor
2 receiver
3 Antenna
4 Low noise amplifier circuit
5 Mixer
6 Oscillator circuit
7 Intermediate frequency detection circuit
8 Power amplifier circuit
DESCRIPTION OF SYMBOLS 9 Digital PLL circuit 10 Demodulation circuit 11 A / D converter 12-14 Latch circuit 15 Threshold judgment circuit 16 Demodulation clock generation circuit

Claims (5)

A bit phase synchronization circuit that generates a clock signal in which bit phase synchronization is performed on received data,
Means for generating a clock signal having a frequency having a phase resolution capable of identifying the bit phase of the received data;
Sampling means for sampling a level of timing to be compared with a predetermined threshold value of the received data by the clock signal;
And a control means for comparing the sampling level with the threshold value and controlling the phase of the clock signal in accordance with the comparison result. The sampling means includes
First to third latch means for latching the received data at first to third clock timings of the clock signal,
The control means includes
The output of the second latch means when the output of the first latch means and the output of the third latch means become a high level and a low level, respectively, with respect to the threshold value. The bit phase synchronization circuit according to claim 1, wherein The received data is burst communication data,
3. The bit phase synchronization circuit according to claim 1, wherein bit phase synchronization is performed by using a preamble signal present at the beginning of the burst data as an input.   4. The bit phase synchronization circuit according to claim 3, wherein a frequency phase of the demodulated clock is fixed in the data period with a synchronization signal existing next to the preamble signal as a trigger.   5. A receiving apparatus using the clock signal of the bit phase synchronization circuit according to claim 1 as a sampling clock for demodulating received data.

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