JP2013224991A - Laser scanning type microscope and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image of higher definition.SOLUTION: A current voltage converting section converts fluorescence, detected from a sample, into an electric signal corresponding to the intensity of the fluorescence and outputs the signal. Four sample hold circuits integrates a signal output from the current voltage conversion section for only a predetermined integration time. Corresponding AD converters carry out AD conversion, thereby obtaining a luminance signal. The four sample hold circuits are controlled in timing so as to start the signal integration at a timing delayed at a 1/4 interval of the predetermined integration time. The present invention can be applied in, for example, a laser scanning type microscope.

Description

  The present invention relates to a laser scanning microscope and a control method, and more particularly to a laser scanning microscope and a control method capable of increasing the resolution while suppressing an increase in image acquisition time.

  Conventionally, a laser scanning microscope scans laser light applied to a sample, introduces reflected light or fluorescence emitted from the sample into a photodetector, and detects the intensity of the detected light and the scanning position of the laser light. By associating with each other, an image within the scanning range of the laser beam is acquired and the sample is observed.

  For example, Patent Document 1 discloses a laser scanning microscope that can suppress errors associated with changes in laser light scanning conditions.

  In such a laser scanning microscope, if the resolution (resolution) of the image is improved, the number of pixels of the image increases, so when an image is acquired with the same AD conversion time by an AD (Analog Digital) converter, The time required to acquire one image is greatly extended. For example, if the vertical x horizontal pixel count is changed to 512 x 515 resolution and the vertical x horizontal pixel count is changed to 4096 x 4096 resolution, the number of pixels is the same if the AD conversion time for acquiring one pixel is the same. Increases 64 times, the image acquisition time for acquiring one image also increases 64 times. For this reason, attempts have been made to shorten the image acquisition time for acquiring one image by reducing the AD conversion time as much as possible.

JP 2011-154212 A

  However, since there is a limit to shortening the conversion time of the AD converter used for image acquisition, it is difficult to suppress an increase in image acquisition time when acquiring a high-resolution image. Further, since an AD converter capable of performing high-speed processing causes a cost increase, it is required to increase the resolution without using a high-speed AD converter.

  The present invention has been made in view of such a situation, and is intended to increase the resolution while suppressing an increase in image acquisition time.

  The laser scanning microscope of the present invention includes a conversion unit that converts light detected from a sample into an electrical signal corresponding to the intensity of the light, and outputs the signal output from the conversion unit. Integration of the signal at a timing delayed by an interval of 1 / n (n = positive integer) of the integration time. And a control unit for controlling the timing so as to start.

  The control method of the present invention includes a conversion unit that converts light detected from a sample into an electrical signal corresponding to the intensity of the light and outputs the signal, and outputs the signal output from the conversion unit to a predetermined integration. A method of controlling a laser scanning microscope comprising a plurality of first integration units that integrate over time, wherein the plurality of first integration units is 1 / n (n = a positive integer) of the integration time. Controlling the timing so as to start integration of the signal at a timing delayed by the interval.

  In the laser scanning microscope and the control method of the present invention, the plurality of first integrators are electrically controlled according to the intensity of light detected from the sample at a timing delayed by 1 / n of the integration time. Timing is controlled to start signal integration.

  According to the laser scanning microscope and the control method of the present invention, high resolution can be achieved while suppressing an increase in image acquisition time.

It is a block diagram which shows the structural example of one Embodiment of the laser scanning microscope to which this invention is applied. It is a block diagram which shows the 1st structural example of a sampling part. It is a figure explaining the sampling in a sampling part. It is a flowchart explaining the process by a sample hold circuit and an AD converter. It is a flowchart explaining the process by a calculating part and a determination part. It is a block diagram which shows the 2nd structural example of a sampling part. It is a figure explaining the sampling in a sampling part. It is a figure explaining the relationship of the timing signal in a sampling part.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of an embodiment of a laser scanning microscope to which the present invention is applied.

  In the laser scanning microscope 11 of FIG. 1, the sample 13 placed on the stage 12 is observed. The laser light output from the light source 14 is converted into parallel light by the condenser lens 15 and enters the light transmittance varying means 16. The light transmittance varying means 16 is composed of, for example, an AOTF (Acousto Optic Tunable Filter), an AOM (Acousto Optic Modulator), etc., and adjusts the intensity of the laser light.

  The laser light that has passed through the light transmittance varying means 16 is reflected toward the sample 13 through the dichroic mirror 17 by a galvano scanner configured to include an X scanning mirror 18 and a Y scanning mirror 19, and is a condensing lens. After being imaged once by 20, it is condensed on the sample 13 by the objective lens 21. Then, the X-axis scanning unit 22 and the Y-axis scanning unit 23 drive the X-scanning mirror 18 and the Y-scanning mirror 19 according to the control of the control device 29, thereby deflecting the laser beam and forming spots on the sample 13. Are scanned two-dimensionally. In addition, the drive mechanism 24 drives the stage 12 in the XY direction (a direction orthogonal to the Z direction with the optical axis of the laser light applied to the sample 13 as the Z direction), so that an arbitrary range of the sample 13 is obtained. In addition, a laser beam spot can be scanned. The drive mechanism 24 is configured by a manual mechanism that is manually driven by a user, an electric mechanism that is electrically controlled and driven, or the like.

  When the fluorescent material included in the sample 13 is irradiated with laser light, fluorescence is emitted from the fluorescent material, and the laser light path is reversed through the objective lens 21 and the condensing lens 20, and the dichroic mirror 17. Head for. The fluorescence that has entered the dichroic mirror 17 has a wavelength longer than that of the laser light, and is reflected by the dichroic mirror 17, collected by the condenser lens 25, and incident on the photodetector 26. The photodetector 26 outputs a signal current corresponding to the intensity of incident fluorescence to the sampling unit 27.

  The sampling unit 27 samples the signal voltage obtained by converting the signal current output from the photodetector 26 according to a predetermined pixel clock (selects a signal voltage value integrated at a predetermined integration time determined by the pixel clock), and outputs a predetermined voltage. A pixel value corresponding to the luminance of the fluorescence detected by the photodetector 26 is acquired with a pixel corresponding to the region of the sample 13 scanned in the integrated time of 1 pixel. The configuration of the sampling unit 27 will be described later with reference to FIG.

  The image processing unit 28 reads out pixel values from the sampling unit 27 and performs image processing for constructing an image, and outputs the constructed image to a display device (not shown) for display or outputs it to a storage device (not shown) for storage. I will let you.

  The control device 29 controls each part of the laser scanning microscope 11, for example, the X-axis scanning unit 22 and the Y-axis so as to scan the spot formed on the sample 13 with laser light at a predetermined scanning range and scanning speed. Control of the scanning means 23 is performed. Further, for example, the control device 29 controls the sampling unit 27 to acquire pixel values at the designated resolution in accordance with the resolution designated by a host device (not shown).

  Here, in the laser scanning microscope 11, the sampling unit 27 includes n (n = positive integer) sample and hold circuits and n AD converters, and n with a time difference of 1 / n of a predetermined integration time. By performing the sampling in stages, it is possible to acquire a higher resolution image than the resolution of the image obtained when one pixel is acquired in a predetermined integration time. For example, in the laser scanning microscope 11, the sampling unit 27 includes four sample-hold circuits and four AD converters, and performs four-stage sampling with a time difference of 1/4 of a predetermined integration time. An image having a resolution four times higher than the resolution of the image obtained when one pixel is acquired in a predetermined integration time can be acquired.

  FIG. 2 shows a first configuration example of the sampling unit 27 that acquires pixel values for constructing an image having a resolution four times higher than the resolution of an image obtained when one pixel is acquired with a predetermined integration time. FIG.

  As shown in FIG. 2, the sampling unit 27 includes a current-voltage conversion unit 31, sample-hold circuits 32-1 to 32-4, AD converters 33-1 to 33-4, a calculation unit 34, a determination unit 35, and a pixel buffer unit. 36, and a timing generation circuit 37.

  A signal current corresponding to the intensity of fluorescence detected by the photodetector 26 is supplied to the current-voltage converter 31. The current-voltage conversion unit 31 converts the signal current into a signal voltage having a voltage value corresponding to the current value, and supplies the signal voltage to the sample hold circuits 32-1 to 32-4.

  In accordance with the timing signal supplied from the timing generation circuit 37, the sample hold circuits 32-1 to 32-4 integrate the signal voltage output from the current-voltage converter 31 for a predetermined integration time, and the integrated analog Holds the value. As will be described later with reference to FIG. 3, the timing at which the sample hold circuits 32-1 to 32-4 start sampling and the timing at which the sample hold circuits 32-1 to 32-4 end sampling are as follows: Control is performed so as to have a time difference of ¼ of a predetermined integration time.

  The AD converters 33-1 to 33-4 AD convert the analog values held in the sample hold circuits 32-1 to 32-4 in accordance with the timing signals supplied from the timing generation circuit 37, respectively, and sample values S1. Thru | or S4 are acquired and supplied to the calculating part 34. FIG. The sampling values S1 to S4 are values according to the luminance in a predetermined integration time having an interval of ¼ of the predetermined integration time according to the sampling timing intervals of the sample hold circuits 32-1 to 32-4. Become.

  The computing unit 34 computes high-resolution luminance values Ts1 to Ts4 corresponding to the luminance at a quarter of a predetermined integration time from the sampling values S1 to S4 output from the AD converters 33-1 to 33-4. To do. As will be described later with reference to FIG. 3, the n-th high-resolution luminance value Tsn can be obtained by calculating the following equation (1).

  Tsn≈Sn− (3/4) × Sn + 1 (1)

  However, in Expression (1), Sn is the nth sampling value, and Sn + 1 is the (n + 1) th sampling value.

  The determination unit 35 determines whether or not the high-resolution luminance value Tsn calculated by the calculation unit 34 is an abnormal value due to the inclusion of a noise component. If the determination unit 35 determines that the high-resolution luminance value Tsn is not an abnormal value, the determination unit 35 supplies the high-resolution luminance value Tsn to the pixel buffer unit 36 for storage. On the other hand, when the determination unit 35 determines that the high-resolution luminance value Tsn is an abnormal value, the calculation unit 34 calculates the high-resolution luminance value Tsn by calculating the following equation (2). The high resolution luminance value Tsn is supplied to the pixel buffer unit 36 and stored therein.

  Tsn≈ (1/4) × Sn (2)

  The pixel buffer unit 36 stores the high-resolution luminance value Tsn supplied from the determination unit 35 as a pixel value corresponding to the luminance of the fluorescence detected by the photodetector 26, and the image processing unit 28 constructs an image. At this time, the image data is supplied to the image processing unit 28.

  The timing generation circuit 37 generates and supplies timing signals indicating the timings of driving to the sample hold circuits 32-1 to 32-4 and the AD converters 33-1 to 33-4, and each of them performs processing. Control the timing to do. For example, the timing generation circuit 37 supplies timing signals SH1_start to SH4_start for instructing start of integration and timing signals SH1_stop to SH4_stop for instructing end of integration to the sample hold circuits 32-1 to 32-4, respectively. To do. The timing generation circuit 37 supplies timing signals AD1_start to AD4_start to instruct the AD converters 33-1 to 33-4 to perform AD conversion of corresponding analog values, respectively.

  The sampling unit 27 configured as described above can acquire a pixel value for constructing an image having a resolution four times higher than the resolution of the image obtained when one pixel is acquired in a predetermined integration time. .

  Next, sampling in the sampling unit 27 will be described with reference to FIG.

  In FIG. 3, the pixel clock signal indicating the reference timing when the laser scanning microscope 11 acquires the pixel value and the sampling values S1 to S4 acquired by the sample hold circuits 32-1 to 32-4 are shown. It is shown.

  The sample hold circuits 32-1 to 32-4 integrate the signal voltage output from the current-voltage converter 31 for a predetermined integration time L, and the AD converters 33-1 to 33-4 use the AD converters 33-1 to 33-4 for AD integration. Conversion is performed to obtain sampling values S1 to S4. At that time, sampling is started and ended between the sample hold circuits 32-1 to 32-4 with a time difference of 1/4 of the predetermined integration time L.

  In other words, the sample hold circuit 32-1 starts sampling of the signal voltage from time t0, which is the timing according to the pixel clock signal, and ends sampling when the predetermined integration time L has elapsed. Then, the integrated value at that time is AD-converted by the AD converter 33-1, and the sampling value S1 is acquired. Further, the sample hold circuit 32-2 starts sampling of the signal voltage from time t1 when ¼ of the predetermined integration time L has elapsed with respect to time t0 when the sample hold circuit 32-1 started sampling. Then, the sampling is finished at the timing when the predetermined integration time L has elapsed. Then, the integrated value at that time is AD-converted by the AD converter 33-2, and the sampling value S2 is acquired.

  Similarly, the sample hold circuit 32-3 samples the signal voltage from the time t2 when 2/4 of the predetermined integration time L has elapsed with respect to the time t0 when the sample hold circuit 32-1 started sampling. The sampling of the signal voltage is terminated at the timing when the predetermined integration time L has elapsed. Then, the integrated value at that time is AD-converted by the AD converter 33-3, and the sampling value S3 is acquired. The sample hold circuit 32-4 starts sampling of the signal voltage from time t3 when 3/4 of the predetermined integration time L has elapsed with respect to time t0 when the sample hold circuit 32-1 started sampling. Then, the sampling of the signal voltage is finished at the timing when the predetermined integration time L has elapsed. Then, the integrated value at that time is AD-converted by the AD converter 33-4, and the sampling value S4 is acquired.

  Here, the predetermined integration time L for acquiring the sampling value S1 and the predetermined integration time L for acquiring the sampling value S2 are only 3/4 of the predetermined integration time L, that is, time It overlaps only for the time from t1 to time t4. Therefore, the luminance value Ts1 in the non-overlapping time, that is, the luminance value Ts1 in the time from the time t0 to the time t1, is a value obtained by integrating the signal voltage in the time from the sampling value S1 to the time t1 to the time t4. It can be obtained by subtraction.

  However, in the configuration of the sampling unit 27, a signal obtained by integrating the signal voltage in the time from the time t1 to the time t4 cannot be acquired. Therefore, the signal voltage is substituted with a value of 3/4 of the sampling value S2. Thus, the luminance value Ts1 can be obtained approximately. That is, the luminance value Ts1 can be approximately obtained by calculating Ts1≈S1− (3/4) × S2.

  Similarly, the luminance value Ts2 in the time from time t1 to time t2 is calculated by calculating Ts2≈S2− (3/4) × S3, and the luminance value Ts3 in the time from time t2 to time t3 is Ts3≈S3. By calculating − (3/4) × S4, it can be obtained approximately.

  The luminance value Ts4 in the time from time t3 to time t4 can be obtained by calculating Ts4≈S4- (3/4) × S5. Note that the sampling value S5 is obtained by starting sampling at time t4 at which ¼ of a predetermined integration time L has elapsed with respect to time t3 at which sampling for obtaining the sampling value S4 was started. The obtained sampling value (that is, the sampling value S1 obtained by starting integration at the next timing according to the pixel clock).

  Therefore, generally, the brightness value Tsn corresponding to the time from time tn to time tn + 1, that is, the time 1/4 of the predetermined integration time L, is calculated as Tsn≈Sn− (3/4) × Sn + 1. That is, it is obtained by calculating the above-described equation (1).

  As described above, the laser scanning microscope 11 uses the AD converters 33-1 to 33-4 by performing four-stage sampling with an interval of ¼ of the predetermined integration time L. Pixel values for constructing an image having a resolution four times that of an image obtained when one pixel is sampled at a predetermined integration time L can be acquired. That is, the laser scanning microscope 11 performs n-stage sampling with a time difference of 1 / n of the predetermined integration time L, so that n times the image obtained when one pixel is sampled with the predetermined integration time L. Pixel values for constructing an image having a resolution of 1 can be acquired.

  Here, for example, the time corresponding to the luminance value Ts1 (from time t0 to time t1) is 1/4 of the predetermined integration time L for obtaining the sampling value S1, so that Ts1≈ (1/4) It is considered that the luminance value Ts1 can also be obtained approximately by the calculation of × S1. However, the approximate expression of Ts1≈S1− (3/4) × S2 described above is the true value of luminance in the time from time t0 to time t1 than the approximate expression of Ts1≈ (1/4) × S1. A value close to.

  That is, the sampling value S1 and the sampling value S2 share 3/4 of the predetermined integration time L (from time t1 to time t4). Therefore, by calculating the difference using the approximate expression of Ts1≈S1− (3/4) × S2, it is possible to cancel the noise component generated in the ¾ time of the predetermined integration time L that is shared. it can. For example, since the probability of noise occurring in such a shared time zone is higher than the probability of noise occurring in a non-shared time zone, the probability of obtaining a good-quality image is increased stochastically. be able to.

  By the way, among the predetermined integration time L for determining the sampling value S2, the sampling value S2 is not shared with the predetermined integration time L for determining the sampling value S1, that is, after the elapse of time t4. It is also assumed that noise is generated in the time zone up to the time when the predetermined integration time L for obtaining ends. That is, it is assumed that noise occurs in the time zone X shown in FIG.

  As described above, when noise occurs in the time zone X, the sampling value S2 becomes a large value. Therefore, when Ts1≈S1− (3/4) × S2 is calculated to obtain the luminance value Ts1, the calculation result is obtained. May become a negative value, that is, an abnormal value. Accordingly, when the luminance value Ts1 becomes an abnormal value, the approximate value of Ts1≈ (1/4) × S1 is calculated, that is, the above-described equation (2) is calculated to calculate the luminance value Ts1. It will be reworked. As described above, in the sampling unit 27, when the luminance value Tsn becomes an abnormal value, the luminance value Tsn is recalculated to thereby contrast the luminance value Tsn with the luminance values Tsn-1 and Tsn + 1 before and after the luminance value Tsn. Can be maintained, and the image quality can be improved.

  Next, processing by the sample hold circuits 32-1 to 32-4 and the AD converters 33-1 to 33-4 will be described with reference to the flowchart of FIG.

  In step S11, the current-voltage converter 31 converts the fluorescence detected by the photodetector 26 into a signal voltage having a voltage value corresponding to the intensity, and supplies the signal voltage to the sample hold circuits 32-1 to 32-4. Start supplying.

  In step S12, the timing generation circuit 37 initializes the count value k and sets 1 (k = 1). Then, the timing generation circuit 37 advances the process to step S13 according to the timing of the pixel clock signal.

  In step S13, the timing generation circuit 37 supplies a timing signal instructing the start of integration to the sample hold circuit 32-k. For example, when the count value k is 1, the timing generation circuit 37 supplies the timing signal SH1_start instructing the start of integration to the sample hold circuit 32-1.

  In step S <b> 14, the sample hold circuit 32-k starts integration of the signal voltage supplied from the current-voltage conversion unit 31 in accordance with the timing signal from the timing generation circuit 37.

  In step S15, the timing generation circuit 37 determines whether or not a quarter of the predetermined integration time L has elapsed from the timing at which the sample hold circuit 32-k is instructed to start integration. The process waits until it is determined that a quarter of the predetermined integration time L has elapsed.

  If it is determined in step S15 that ¼ of the predetermined integration time L has elapsed, the process proceeds to step S16, and the timing generation circuit 37 determines whether the count value k is 4 or more. To do.

  When it is determined in step S16 that the count value k is not 4 or more (that is, the count value k is less than 4), the process proceeds to step S17. In step S17, the timing generation circuit 37 increments the count value k by 1, the process returns to step S13, and the same process is repeated thereafter.

  That is, the timing generation circuit 37 sets the sampling and holding circuit 32-2 every time a quarter of the predetermined integration time L elapses until it is determined in step S16 that the count value k is 4 or more. The timing signal SH2_start is supplied, the timing signal SH3_start is supplied to the sample hold circuit 32-3, and the timing signal SH4_start is supplied to the sample hold circuit 32-4. Then, the sample hold circuits 32-2 to 32-4 start integration of the signal voltage supplied from the current-voltage conversion unit 31 at each timing.

  Thereafter, when it is determined in step S16 that the count value k is 4 or more, the process proceeds to step S18, and the timing generation circuit 37 resets the count value k (k = 1).

  In step S19, the timing generation circuit 37 determines whether or not the predetermined integration time L has elapsed from the timing at which the sample hold circuit 32-k is instructed to start integration, and the predetermined integration time L has elapsed. The process waits until it is determined that it has been completed. When it is determined in step S16 that the count value k is 4 or more, that is, when a quarter of the predetermined integration time L has passed four times, the integration is performed on the sample hold circuit 32-1. A predetermined integration time L has elapsed from the timing when the start is instructed.

  If it is determined in step S19 that the predetermined integration time L has elapsed, the process proceeds to step S20, and the timing generation circuit 37 outputs a timing signal for instructing the sample hold circuit 32-k to end integration. Supply. Further, the timing generation circuit 37 supplies a timing signal that instructs the AD converter 33-k to perform AD conversion of the analog value held in the sample hold circuit 32-k. For example, when the count value k is 1, the timing generation circuit 37 supplies a timing signal SH1_stop that instructs the sample hold circuit 32-1 to end integration. Further, the timing generation circuit 37 supplies a timing signal AD1_start that instructs the AD converter 33-1 to perform AD conversion of the analog value held in the sample hold circuit 32-1.

  In step S21, the AD converter 33-k AD converts the analog value held in the sample hold circuit 32-k according to the timing signal from the timing generation circuit 37, and acquires the sampling value Sk.

  In step S22, the timing generation circuit 37 determines whether or not the count value k is 4 or more.

  If it is determined in step S22 that the count value k is not 4 or more (that is, the count value k is less than 4), the process proceeds to step S23. In step S23, the timing generation circuit 37 increments the count value k by 1, the process returns to step S19, and the same process is repeated thereafter.

  That is, each time a predetermined integration time L elapses until it is determined in step S22 that the count value k is 4 or more, the timing generation circuit 37 sends the timing signal SH2_stop to the sample hold circuit 32-2. The timing signal AD2_start is supplied to the AD converter 33-2, the timing signal SH3_stop is supplied to the sample hold circuit 32-3, the timing signal AD3_start is supplied to the AD converter 33-3, The timing signal SH4_stop is supplied to the hold circuit 32-4 and the timing signal AD4_start is supplied to the AD converter 33-4.

  Then, the sample hold circuits 32-2 to 32-4 stop the integration of the signal voltage supplied from the current-voltage converter 31 at each timing, and the AD converters 33-2 to 33-4 respectively S2 to 4 are acquired.

  Thereafter, when it is determined in step S22 that the count value k is 4 or more, the process returns to step S12, and the same process is repeated thereafter.

  Next, with reference to the flowchart of FIG. 5, the process by the calculating part 34 and the determination part 35 is demonstrated.

  In step S31, when the two sampling values Sn and the sampling value Sn + 1 are supplied, the calculation unit 34 calculates the luminance value Tsn approximately by calculating the above-described equation (1), and determines the determination unit 35. To supply.

  In step S32, the determination unit 35 determines whether or not the luminance value Tsn calculated by the calculation unit 34 in step S31 is an abnormal value. For example, when the luminance value Tsn is a negative value (Tsn <0), the determination unit 35 determines that the luminance value Tsn is an abnormal value.

  In step S32, when the determination unit 35 determines that the luminance value Tsn calculated by the calculation unit 34 in step S31 is not an abnormal value, the process proceeds to step S33, and the determination unit 35 uses the luminance value Tsn as a pixel buffer. It supplies to the part 36 and memorize | stores it.

  On the other hand, when the determination unit 35 determines in step S32 that the luminance value Tsn calculated by the calculation unit 34 in step S31 is an abnormal value, the process proceeds to step S34, and the determination unit 35 transfers the calculation unit 34 to the calculation unit 34. On the other hand, it is requested to recalculate the luminance value Tsn by calculating the above equation (2). In response to this, the calculation unit 34 recalculates the brightness value Tsn and supplies it to the determination unit 35. Thereafter, the process proceeds to step S34, and the determination unit 35 supplies the luminance value Tsn recalculated by the calculation unit 34 in step S34 to the pixel buffer unit 36 for storage.

  After the process of step S33, in step S35, the calculation unit 34 waits for the process until the next sampling value is supplied, and when the next sampling value is supplied, the process returns to step S31. Is repeated.

  As described above, the sampling unit 27 performs sampling in four stages with a time difference of ¼ of the predetermined integration time, so that the resolution of the image obtained when one pixel is acquired with the predetermined integration time is obtained. A pixel value (luminance value) for constructing an image having a resolution of 4 times can be acquired. In addition, since the scanning speed in the X direction of the spot scanned on the sample 13 is the same as when acquiring a resolution image obtained when one pixel is acquired in a predetermined integration time, a high resolution image is obtained. It is possible to avoid an increase in the time required to acquire That is, the laser scanning microscope 11 can acquire an image with a resolution four times as high as when acquiring an image with a resolution obtained when one pixel is acquired with a predetermined integration time. it can.

  Further, the laser scanning microscope 11 can avoid an increase in cost assumed when a high-speed AD converter is used. That is, the laser scanning microscope 11 can acquire a high-resolution image with a short image acquisition time and low cost.

  Further, the laser scanning microscope 11 can cancel the noise component generated in the time zone shared by the sampling value Sn and the sampling value Sn + 1 by calculating the luminance value by the above-described equation (1). A higher quality image can be acquired. Furthermore, when the luminance value calculated by the above equation (1) is an abnormal value, the laser scanning microscope 11 recalculates the luminance value by the above equation (2), thereby suppressing deterioration in image quality. can do.

  Next, FIG. 6 is a block diagram illustrating a second configuration example of the sampling unit 27. In the sampling unit 27 ′ illustrated in FIG. 6, the blocks common to the sampling unit 27 in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  That is, the sampling unit 27 ′ has the same configuration as the sampling unit 27 of FIG. 2 in that it includes the current-voltage conversion unit 31, the pixel buffer unit 36, and the timing generation circuit 37. However, the sampling unit 27 ′ includes sample hold circuits 32a-1 to 32a-4, sample hold circuits 32b-1 to 32b-4, and differential input AD converters 38-1 to 38-4. The sampling unit 27 is configured differently.

  The sample hold circuits 32 a-1 to 32 a-4 integrate the signal voltage output from the current-voltage conversion unit 31 for a predetermined integration time according to the timing signal supplied from the timing generation circuit 37, and the integrated analog Holds the value. In accordance with the timing signal supplied from the timing generation circuit 37, the sample hold circuits 32b-1 to 32b-4 integrate the signal voltage output from the current-voltage conversion unit 31 by a time corresponding to 3/4 of the predetermined integration time. The integrated analog value is held.

  That is, the sample hold circuits 32a-1 to 32a-4 perform integration for a predetermined integration time, whereas the sample hold circuits 32b-1 to 32b-4 correspond to 3/4 of the predetermined integration time. Perform integration of.

  The differential input AD converter 38-1 AD converts the difference value between the analog values held in the sample hold circuit 32a-1 and the sample hold circuit 32b-1 in accordance with the timing signal supplied from the timing generation circuit 37. The brightness value Ts1 is acquired. The differential input AD converter 38-2 AD converts the difference value between the analog values held in the sample hold circuit 32a-2 and the sample hold circuit 32b-2 according to the timing signal supplied from the timing generation circuit 37. Then, the brightness value Ts2 is obtained. Similarly, the differential input AD converter 38-3 acquires the luminance value Ts3, and the differential input AD converter 38-4 acquires the luminance value Ts4.

  The differential input AD converters 38-1 to 38-4 supply the acquired luminance values Ts1 to Ts4 to the pixel buffer unit 36, and store them as pixel values.

  Next, sampling in the sampling unit 27 'will be described with reference to FIG.

  In FIG. 7, a pixel clock signal indicating a reference timing when the laser scanning microscope 11 acquires a pixel value, sampling values S1a to S4a acquired by the sample hold circuits 32a-1 to 32a-4, and Sampling values S1b to S4b acquired by the sample hold circuits 32b-1 to 32b-4 are shown.

  The sample-and-hold circuits 32a-1 to 32a-4 acquire the sampling values S1a to S4a by integrating the signal voltage output from the current-voltage converter 31 for a predetermined integration time L. At that time, sampling is started between the sample hold circuits 32-1 to 32-4 with a time difference of 1/4 of the predetermined integration time L.

  That is, the sample hold circuit 32a-1 starts sampling of the signal voltage from time t0, which is the timing according to the pixel clock signal, and the sample hold circuit 32a-2 has a predetermined integration time L with respect to time t0. Sampling of the signal voltage is started from time t1 when ¼ time has elapsed. The sample hold circuit 32a-3 starts sampling of the signal voltage from time t2 when 2/4 of the predetermined integration time L has elapsed with respect to time t0, and the sample hold circuit 32a-4 Sampling of the signal voltage is started at time t3 when a third of the predetermined integration time L has elapsed with respect to t0.

  The sample hold circuits 32b-1 to 32b-4 obtain the sampling values S1b to S4b by integrating the signal voltage output from the current-voltage conversion unit 31 for a time that is 3/4 of the predetermined integration time L.

  At this time, the sample hold circuit 32b-1 performs sampling from time t1, which is a timing delayed by 1/4 of the predetermined integration time L with respect to time t0 when the sample hold circuit 32a-1 starts sampling. Start. The sample hold circuit 32b-2 starts sampling from time t2, which is a timing delayed by 1/4 of the predetermined integration time L with respect to time t1 when the sample hold circuit 32a-2 starts sampling. To do.

  Similarly, the sample hold circuit 32b-3 performs sampling from time t3, which is a timing delayed by 1/4 of the predetermined integration time L with respect to time t2 when the sample hold circuit 32a-3 starts sampling. Start. The sample hold circuit 32b-4 starts sampling from time t4, which is a timing delayed by 1/4 of the predetermined integration time L with respect to time t3 when the sample hold circuit 32a-4 starts sampling. To do.

  Therefore, the differential input AD converter 38-1 AD converts the difference value between the sampling value S1a held in the sample hold circuit 32a-1 and the sampling value S1b held in the sample hold circuit 32b-1. Thus, the luminance value Ts1 in the time from time t0 to time t1 is obtained. Further, the differential input AD converter 38-2 AD converts the difference value between the sampling value S2a held in the sample hold circuit 32a-2 and the sampling value S2b held in the sample hold circuit 32b-2. Thus, the luminance value Ts2 in the time from time t1 to time t2 is obtained.

  Similarly, the luminance value Ts3 in the time from time t2 to time t3 is obtained by the differential input AD converter 38-3, and the luminance value in the time from time t3 to time t4 is obtained by the differential input AD converter 38-4. Ts4 is obtained.

  Therefore, generally, the luminance value Tsn corresponding to ¼ of the predetermined integration time L from the time tn to the time tn + 1 is obtained as a difference by the differential input AD converter 38, that is, Tsn = Sna−. It is calculated | required by Snb.

  With reference to FIG. 8, the relationship of timing signals in the sampling unit 27 'will be described.

  FIG. 8 shows four clock signals Clock1 to Clock4 having a phase difference (time difference) of 1/4 each other.

  The timing generation circuit 37 supplies a timing signal SH1_start for instructing the sample hold circuit 32a-1 to start integration in accordance with the clock signal Clock1, and integration of the sampling value S1a is started.

  Next, the timing generation circuit 37 supplies a timing signal SH2_start for instructing the sample hold circuit 32b-1 to start integration in accordance with the clock signal Clock2, and integration of the sampling value S1b is started. At the same time, the timing generation circuit 37 supplies a timing signal SH3_start for instructing the sample hold circuit 32a-2 to start integration in accordance with the clock signal Clock2, and integration of the sampling value S2a is started.

  Similarly, the timing generation circuit 37 supplies timing signals SH4_start and SH5_start in accordance with the clock signal Clock3 to start integration of the sampling values S2b and S3a, and supplies timing signals SH6_start and SH7_start in accordance with the clock signal Clock4. Integration of S3b and S4a is started.

  Thereafter, the timing generation circuit 37 supplies the timing signal SH8_start for instructing the sample hold circuit 32b-4 to start integration in accordance with the clock signal Clock1, and the integration of the sampling value S4b is started. At the same time, the timing generation circuit 37 supplies timing signals SH1_stop and SH2_stop for instructing the end of integration to the sample hold circuits 32a-1 and 32b-1 according to the clock signal Clock1, and the integration of the sampling values S1a and S1b is completed. Is done. Further, the timing generation circuit 37 supplies a timing signal AD1_start that instructs the differential input AD converter 38-1 to perform AD conversion in accordance with the clock signal Clock1, and the differential input AD converter 38-1 has a luminance value. Obtain Ts1.

  Next, the timing generation circuit 37 supplies timing signals SH3_stop and SH4_stop for instructing the end of integration to the sample hold circuits 32a-2 and 32b-2 according to the clock signal Clock2, and integration of the sampling values S2a and S2b is performed. Is terminated. At the same time, the timing generation circuit 37 supplies a timing signal AD2_start for instructing the differential input AD converter 38-2 to perform AD conversion according to the clock signal Clock2, and the differential input AD converter 38-2 receives the luminance value. Get Ts2.

  Similarly, the timing generation circuit 37 supplies the timing signals SH5_stop and SH6_stop in accordance with the clock signal Clock3 to complete the integration of the sampling values S3b and S3a, and supplies the timing signal AD3_start to obtain the luminance value Ts3. Further, the timing generation circuit 37 supplies the timing signals SH7_stop and SH8_stop according to the clock signal Clock4 to complete the integration of the sampling values S4b and S4a, and supplies the timing signal AD4_start to obtain the luminance value Ts4.

  As described above, in the sampling unit 27 ′, four stages of sampling corresponding to the predetermined integration time L performed at a time difference of ¼ of the predetermined integration time L and a time difference of ¼ of the predetermined integration time L are performed. The luminance value can be accurately calculated by obtaining the difference from the sampling of four stages of L × 3/4 of the predetermined integration time to be performed. Thereby, the laser scanning microscope 11 can acquire an image with better image quality.

  Further, since the laser scanning microscope 11 does not need to significantly reduce the sampling time, it is not necessary to use a high-speed AD converter, and it is possible to display a high-resolution image while suppressing an increase in image acquisition time. Can be acquired. Furthermore, when acquiring the analog values held in the sample hold circuit 32a-1 and the sample hold circuit 32b-1, the higher the number of pixels, the higher the ratio of time zones shared in time. By calculating the difference by the differential input AD converter 38, the effect of removing noise can be enhanced.

  In the laser scanning microscope 11, the differential input AD converter 38 simultaneously performs AD conversion and difference calculation by connecting the sample hold circuit 32a and the sample hold circuit 32b to the differential input AD converter 38. The circuit can be simplified.

  Further, the sampling unit 27 ′ performs processing for correcting individual differences. That is, the same input signal is supplied to the sample hold circuits 32a-1 to 32a-4 with the same integration time, and the same input to the sample hold circuits 32b-1 to 32b-4 with the same integration time. Supply signal. Each individual difference is measured by measuring the luminance values Ts1 to Ts4 output from the differential input AD converters 38-1 to 38-4.

  Therefore, the processing for correcting the luminance values Ts1 to Ts4 to be within a predetermined error range includes the sample hold circuits 32a-1 to 32a-4, the sample hold circuits 32b-1 to 32b-4, and the differential input AD converter. It is applied to 38-1 to 38-4. As a result, pixel values that suppress individual differences among the sample hold circuits 32a-1 to 32a-4, the sample hold circuits 32b-1 to 32b-4, and the differential input AD converters 38-1 to 38-4 are acquired. Can do.

  Embodiments of the present invention provide a ¼ of a predetermined integration time L in order to construct an image having a resolution four times that of the image obtained when one pixel is acquired with a predetermined integration time. Although an example of performing integration using four sample-and-hold circuits with a time difference has been described, the present invention is not limited to this, and can be realized if there are at least two sample-and-hold circuits.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  In a computer, programs stored in ROM (Read Only Memory) or programs stored in a storage unit such as a hard disk or non-volatile memory are loaded into RAM (Random Access Memory) and CPU (Central Executed by the Processing Unit). Thereby, the series of processes described above are performed.

  These programs are stored in advance in a storage unit, or via a communication unit such as a network interface, or a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only). Memory, DVD (Digital Versatile Disc, etc.), magneto-optical disk, or drive that drives removable media such as semiconductor memory can be installed in the computer.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing. Further, the program may be processed by a single CPU, or may be processed in a distributed manner by a plurality of CPUs.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

  11 laser scanning microscope, 12 stage, 13 sample, 14 light source, 15 condenser lens, 16 light transmittance variable means, 17 dichroic mirror, 18 X scanning mirror, 19 Y scanning mirror, 20 condenser lens, 21 objective lens, 22 X-axis scanning means, 23 Y-axis scanning means, 24 drive mechanism, 25 condenser lens, 26 photodetector, 27 sampling unit, 28 image processing unit, 29 control device, 31 current voltage conversion unit, 32 sample hold circuit, 33 AD converter, 34 arithmetic unit, 35 determination unit, 36 pixel buffer unit, 37 timing generation circuit, 38 differential input AD converter

Claims (8)

A converter that converts the light detected from the sample into an electrical signal corresponding to the intensity of the light and outputs the electrical signal;
A plurality of first integration units that integrate the signal output from the conversion unit with a predetermined integration time;
A plurality of the first integration units, a control unit that controls timing so as to start integration of the signal at a timing delayed by an interval of 1 / n (n = positive integer) of the integration time. Scanning microscope. From the time at which the k (k = positive integer) th first integration unit of the plurality of first integration units starts integrating the signal, the (k + 1) th first integration unit is A k + 1th integration value obtained by integrating the signal with the integration time by the kth first integration unit, and a luminance value indicating the luminance of the light in the time until the signal integration start time. 2. The calculation unit according to claim 1, further comprising: an arithmetic unit that calculates a predetermined first approximate expression using an integration value obtained by integrating the signal with the integration time. The laser scanning microscope described in 1. A determination unit for determining whether or not the luminance value calculated by the calculation unit is an abnormal value;
When the luminance value is determined to be an abnormal value by the determination unit, the arithmetic unit is k + 1th from the time when the kth first integration unit starts integrating the signal. The luminance value indicating the luminance of the light in the time until the integration unit starts integrating the signal, and the integral value obtained by integrating the signal with the integration time by the kth first integration unit The laser scanning microscope according to claim 2, wherein the laser scanning microscope is recalculated by using a predetermined second approximate expression using The signal output from the conversion unit is (n−1) / of the integration time from the timing delayed by an interval of 1 / n with respect to the time when the first integration unit started integrating the signal. a plurality of second integrators that integrate over time n;
For each of the first integration unit and the second integration unit corresponding to each other, a value obtained by integrating the signal by the first integration unit, and the second integration unit integrating the signal. By calculating the difference from the value obtained by the above, the time in the time from the time when the first integrator starts integrating the signal to the time when the second integrator starts integrating the signal. The laser scanning microscope according to claim 1, further comprising: a difference calculation unit that calculates a luminance value indicating the luminance of light. The difference calculation unit performs AD (Analog Digital) conversion on the value integrated by the first integration unit, AD conversion of the value integrated by the second integration unit, and the first integration unit and The laser scanning microscope according to claim 4, wherein a difference between values obtained by the second integration unit is calculated. The laser scanning microscope according to claim 5, wherein the difference calculation unit is a differential input AD converter that simultaneously performs AD conversion and difference calculation. The same input signal is supplied to the first integration unit with the same integration time, and the same input signal is supplied to the second integration unit with the same integration time. A process for correcting the luminance value output from the AD converter to be within a predetermined error range is applied to the first integration unit, the second integration unit, and the differential input AD converter. The laser scanning microscope according to claim 1, wherein: A conversion unit that converts the light detected from the sample into an electrical signal corresponding to the intensity of the light and outputs the signal, and a plurality of second units that integrate the signal output from the conversion unit with a predetermined integration time. 1 is a control method of a laser scanning microscope including an integrating unit,
A control method including a step of controlling timing so that a plurality of the first integration units start integration of the signal at a timing delayed by an interval of 1 / n (n = positive integer) of the integration time.

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