JP2013219469A - Laminate type band-pass filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a band-pass filter (BPF) which, compact and low profile though, exhibits excellent characteristics by restraining high frequency spurious by a simple method without requiring significant modification or complication of a laminate structure.SOLUTION: The band-pass filter comprises: an input section including an input terminal, an output terminal, a plurality of resonators, and an input line connecting a first-stage resonator and the input terminal; and an output section including an output line connecting a last-stage resonator and the output terminal. The input line has an input side additional line connected in parallel thereto, which reduces the inductance of the input section, and the output line has an output side additional line connected in parallel thereto, which reduces the inductance of the output section.

Description

  The present invention relates to a multilayer bandpass filter, and more particularly to a technique for obtaining good harmonic characteristics by suppressing spurious generated in a high frequency region.

  A band-pass filter (hereinafter sometimes referred to as “BPF”) that attenuates unwanted waves and selectively passes signals in the used frequency band is used for transmission / reception of electronic devices equipped with wireless communication functions such as mobile phones, smartphones, and notebook computers. Such a BPF is generally provided as a chip-shaped electronic component (laminated BPF) in which a resonator is formed in an internal wiring layer of a laminated substrate.

  Further, the following patent documents disclose such multilayer electronic components.

JP 2009-246889 A

  By the way, in recent years, with the demand for multi-functionality and high functionality for electronic devices, the demand for harmonic countermeasures has also increased for BPF in addition to the reduction in size and height.

  Specifically, FIGS. 5, 6, and 7 </ b> A to 7 </ b> D are a circuit diagram of a laminated BPF according to a comparative example of the present invention, a plan view showing the arrangement of conductor patterns on each layer of the laminated substrate, and a line showing frequency characteristics. As shown in FIG. 7A, spurious S occurs in the high frequency region in the BPF.

  Since this high-frequency spurious deteriorates communication quality such as causing noise, a countermeasure is desired. However, there are various causes for the occurrence of spurious, and since it is caused by a plurality of factors affecting each other in a complicated manner, it is difficult to identify the cause, and thus countermeasures are not easy.

  On the other hand, in order to remove such high-frequency spurious, it may be possible to further include a filter. However, the addition of the filter increases the insertion loss and causes a deterioration in the characteristics of the passband, and the increase in the number of components violates the demand for a small and low-profile electronic device.

  On the other hand, in the invention described in Patent Document 1, the arrangement of the conductor pattern (electrode) in the multilayer substrate is changed, and the signal path connecting the signal terminal and the resonator is shortened, thereby reducing the stray inductance and reducing spurious. Suppress. However, in the invention described in this document, it is necessary to change the arrangement of conductors (elements and terminals) in the chip to a specific structure, which can be applied to an existing or any stacked chip. is not.

  Therefore, an object of the present invention is to suppress high-frequency spurious by a simpler method without significant design change or complication of the laminated structure (arrangement of the conductor pattern in the chip), and to have good characteristics with a small size and a low profile. It is in the point which implement | achieves BPF which has.

  In order to solve the above problems and achieve the object, a BPF (band pass filter) according to the present invention includes an input terminal capable of inputting a signal, an output terminal capable of outputting a signal, and between the input terminal and the output terminal. A plurality of resonators connected to each other to form a predetermined passband, and an input line that electrically connects between the input terminal and the first-stage resonator closest to the input terminal among the plurality of resonators A BPF comprising: an input unit; and an output unit including an output line that electrically connects a final stage resonator closest to the output terminal and the output terminal among the plurality of resonators, An input side additional line connected in parallel to the input line to reduce the inductance of the input unit is provided in the input unit, and an output side additional line connected in parallel to the output line to reduce the inductance of the output unit The Those with the serial output section.

  The present invention has been made while variously examining the cause of high-frequency spurious generated on the high-frequency side of the passband and a method for suppressing the high-frequency spurious. The resonance included in the BPF is one of the causes of spurious generation. Parts other than the resonator, specifically, an input unit that inputs a signal to the resonator (an input line connecting the input terminal and the resonator) and an output unit that outputs a signal from the resonator (the output terminal and the resonator) Output line), or a bypass capacitor (bypass capacitor) provided between the input terminal and the output terminal may resonate in a high frequency region. It has been found that it can be effectively suppressed by reducing the inductance of the part.

  Therefore, in the BPF of the present invention, the inductance of the input unit that is a signal input path from the input terminal to the first stage resonator and the output unit that is the signal output path from the final stage resonator to the output terminal are reduced. Thus, a conductor line (additional line) is added in parallel to the input line and the output line. The effect of suppressing spurious by this additional line will be described more specifically based on the simulation result in the description of the later embodiment.

  As described above, according to the present invention, spurious can be effectively suppressed by a simple method of adding a line to an input unit or an output unit, which may lead to a complicated stacked structure and an increased chip size. Therefore, it is possible to realize a BPF having a small size and a low profile and better characteristics than the conventional one. In the present invention, since it is not necessary to adopt a specific structure for the arrangement of other conductors constituting the resonator and the laminated structure of the substrate, the present invention can be widely applied to BPF chips having various laminated structures.

  The additional line is preferably provided in both the input unit and the output unit. However, as will be described later in the description of the embodiment, only the input side additional line or the output side additional line is provided. Even if it exists, compared with the conventional BPF, the effect of a favorable spurious suppression is acquired. Therefore, a BPF having the additional line only in the input unit and a BPF having the additional line only in the output unit are also included in the scope of the present invention.

  The BPF of the present invention typically includes the above-described configurations, that is, an input terminal, an output terminal, a plurality of resonators, an input unit, and an output unit, on a multilayer substrate having a plurality of wiring layers. The laminated BPF (chip-shaped BPF) is provided. As a first aspect of the laminated BPF, the input side additional line is arranged on a conductor layer different from the input line, and the output side additional line is defined as the output line. Place in different conductor layers. In the second aspect, the input side additional line is arranged on the same conductor layer as the input line, and the output side additional line is arranged on the same conductor layer as the output line.

  When an additional line is provided in parallel with the input line (the same applies to the output line) between the input terminal and the resonator, both lines (the additional line and the input line (or the output line) are used as in the second aspect. )) Is arranged in the same conductor layer, there is an advantage that only one conductor layer is required to realize the line structure according to the present invention. On the other hand, according to the second aspect, the input line (or output line) and the additional line form a loop between the input terminal (or output terminal) and the resonator as shown in FIG. The island-shaped portion surrounded by the two lines (the portion surrounded by the input line Li, the capacitor electrode C1, and the additional line La in FIG. 2 / the output line Lo, the capacitor electrode C3, and the additional line Lb. Part) may occur, and such an island-like part may deteriorate the adhesion between the insulating layers and cause cracks in the laminated substrate. In particular, when the chip size (the area when viewed from the plane) is reduced, the area occupied by the insulator is relatively reduced, so that the adhesion between the insulating layers is lowered. On the other hand, according to said 1st aspect, such a problem can be avoided.

  According to the present invention, high-frequency spurious is suppressed by a simpler method without significant design change of the laminated structure (the arrangement of conductor patterns in the chip), and a small and low-profile BPF having excellent characteristics is realized. I can do it.

  Other objects, features, and advantages of the present invention will become apparent from the following description of embodiments of the present invention described with reference to the drawings. In addition, in each figure, the same code | symbol shows the same or an equivalent part.

FIG. 1 is a circuit diagram showing a BPF according to a first embodiment of the present invention. FIG. 2 is a plan view showing the BPF laminated structure (each layer of the laminated substrate) according to the first embodiment. FIG. 3A is a diagram showing the frequency characteristics (pass attenuation characteristics) of the BPF according to the first embodiment. FIG. 3B is an enlarged diagram showing the pass attenuation characteristic (insertion loss) of the BPF according to the first embodiment. FIG. 3C is a diagram showing frequency characteristics (reflection loss) of the BPF according to the first embodiment. FIG. 3D is a Smith chart showing the reflection coefficient on the input terminal side in the BPF of the first embodiment. FIG. 3E is a diagram showing frequency characteristics (pass attenuation characteristics) of a BPF according to a modification of the first embodiment. FIG. 4 is a plan view showing a BPF laminated structure (each layer of the laminated substrate) according to the second embodiment of the present invention. FIG. 5 is a circuit diagram illustrating an example of a BPF according to a comparative example. FIG. 6 is a plan view showing a BPF laminated structure (each layer of the laminated substrate) according to the comparative example. FIG. 7A is a diagram showing the frequency characteristics (pass attenuation characteristics) of the BPF according to the comparative example. FIG. 7B is an enlarged diagram showing the pass attenuation characteristic (insertion loss) of the BPF according to the comparative example. FIG. 7C is a diagram showing frequency characteristics (reflection loss) of the BPF according to the comparative example. FIG. 7D is a Smith chart showing the reflection coefficient on the input terminal side in the BPF according to the comparative example.

[First Embodiment]
As shown in FIG. 1, the BPF 11 according to the first embodiment of the present invention includes three stages of resonators 12, 13, which are sequentially provided between an input terminal T1 and an output terminal T2 in order to form a predetermined pass band. 14, a bypass capacitor (bypass capacitor) C4 connected between the input terminal T1 and the output terminal T2 in parallel to these resonators 12 to 14, and a signal input through the input terminal T1 to the first-stage resonator 12 It has the input part 15 which transmits, and the output part 16 which transmits the signal output from the resonator 14 of the last stage to the output terminal T2. In the following description, the three-stage resonators 12 to 14 are referred to as a first resonator, a second resonator, and a third resonator in order from the input terminal T1 toward the output terminal T2.

  Each of the resonators 12 to 14 is an LC resonator composed of an inductor and a capacitor. The first resonator (first-stage resonator) 12 connected to the position closest to the input terminal T1 includes the input terminal T1 and the ground G. This is an LC parallel resonator composed of an inductor L1 and a capacitor C1 connected in parallel. Similarly, the third resonator (final stage resonator) 14 connected to the position closest to the output terminal T2 is an LC parallel circuit including an inductor L4 and a capacitor C3 connected in parallel between the output terminal T2 and the ground G. It is a resonator.

  The second resonator 13 is an LC series resonator including a first inductor L2, a capacitor C2, and a second inductor L3 connected in series between the ground G and the ground G in order. L3 is electromagnetically coupled to the inductor L1 of the first resonator and the inductor L4 of the second resonator, respectively.

  Further, the input unit 15 includes a conductor line (input line) Li connecting the input terminal T1 and the first resonator 12, and, in addition, a conductor line (input side additional line) La connected in parallel with the line Li. Is provided. In other words, the input unit 15 includes two conductor lines Li and La, and inputs a signal from the input terminal T1 to the first resonator 12 through the two conductor lines Li and La. The additional line La has an inductance component similar to the input line Li, reduces the inductance of the input unit 15, and thereby suppresses high-frequency spurious.

  Similarly, the output unit 16 includes a conductor line (output-side additional line) Lb connected in parallel with the output line Lo in addition to the conductor line (output line) Lo that connects the third resonator 14 and the output terminal T2. I have. That is, the output unit 16 is also provided with two conductor lines Lo and Lb similarly to the input unit 15, and outputs a signal from the third resonator 14 to the output terminal T2 through these conductor lines Lo and Lb.

  In the present embodiment, a chip-shaped BPF (hereinafter also referred to as “chip”) is configured by arranging the circuit elements and circuit elements in the conductor layer of the multilayer substrate. As the multilayer substrate, for example, an LTCC (Low Temperature Co-fired Ceramics) substrate can be used. In this case, conductor patterns constituting the circuit elements and circuit elements and via holes (hereinafter referred to as “vias”) for electrically connecting these conductor patterns are formed on the surface of a plurality of ceramic green sheets. After aligning and stacking and dividing into chips, they are integrated by firing.

  The specific arrangement of each conductor in the multilayer substrate is as shown in FIG. In the case of this embodiment, the laminated substrate is formed by stacking 10 ceramic green sheets. The back surface of the substrate (the bottom surface of the chip) is the first layer, and the substrate is directed toward the top surface of the substrate (the top surface of the chip). As the second layer, the third layer, the fourth layer,..., The uppermost wiring layer is referred to as the tenth layer in order as it goes to the upper layer (the second embodiment of FIG. 4 described later and the comparative example of FIG. 6). The same). In FIG. 2, a circle indicated by a symbol V represents a via.

  As shown in FIG. 2A, the input terminal T1, the output terminal T2, and the ground terminal TG are formed on the first layer on the back surface of the substrate. The chip (laminated substrate) has a rectangular planar shape, and an input terminal T1 is disposed at one end in the longitudinal direction, and an output terminal T2 is disposed at the other end. A ground terminal TG is arranged between the input terminal T1 and the output terminal T2 (in the center of the substrate).

  The inductor L1 of the first resonator 12 is formed by connecting U-shaped conductors arranged at one end of the ninth-layer substrate and one end of the tenth-layer substrate by vias V, respectively. Further, two capacitor electrodes C1 and C3 are arranged side by side at the center of the third layer substrate, and the first resonance is caused by the left capacitor electrode C1 and the ground electrode G disposed at the center of the second layer substrate. The capacitor C1 of the vessel 12 is formed.

  Similarly to the inductor L1 of the first resonator 12, the inductor L4 of the third resonator 14 has via-shaped U-shaped conductors disposed on the other end of the ninth layer substrate and the other end of the substrate of the tenth layer. V is connected and formed. Similarly to the capacitor C1 of the first resonator 12, the capacitor C3 of the third resonator 14 has a capacitor electrode C3 on the right side of the capacitor electrodes C1 and C3 arranged on the third layer and the capacitor C3 of the second layer. It is formed by a ground electrode G disposed at the center of the substrate.

  Further, an electrode C4 is disposed so as to spread left and right at the center of the substrate of the fourth layer and to face both the capacitor electrodes C1, C3 of the third layer, and the bypass capacitor C4 is formed by these electrodes C1, C3, C4. Configure.

  The first inductor L2 of the second resonator 13 includes the third layer, the fourth layer, the fifth layer, the sixth layer, the seventh layer, the eighth layer, and the ninth layer from the second layer ground electrode G. A via V that penetrates and is electrically connected to an electrode disposed in the central portion of the substrate of the tenth layer and an electrode disposed in the central portion of the tenth layer are configured. At the same time, the capacitor C2 of the second resonator is formed by the electrode disposed at the center of the tenth layer, the electrode disposed at the center of the ninth layer, and the electrode disposed at the center of the eighth layer. Thus, the electrode at the center of the tenth layer is the electrode that constitutes the capacitor C2 and the electrode that constitutes the inductor L2, and the fact that the reference numerals C2 and L2 are also written on the electrode indicates this. Yes (the same applies to the electrode at the center of the ninth layer). Further, the second resonator of the second resonator is provided by an electrode arranged at the center of the ninth layer and a via V extending from the electrode at the center of the ninth layer to the sixth layer through the eighth and seventh layers. An inductor L3 is formed.

  In the tenth layer, the inductor L1 of the first resonator 12, the inductor L2 of the second resonator 13 (the electrode at the center of the substrate of the tenth layer), and the inductor L4 of the third resonator 14 are arranged in order. By arranging, the inductor L1 and the inductor L2 are electromagnetically coupled, and the inductor L2 and the inductor L4 are electromagnetically coupled.

  Similarly, in the ninth layer, the inductor L1 of the first resonator 12, the inductor L3 of the second resonator 13 (the electrode at the center of the substrate of the ninth layer), and the inductor L4 of the third resonator 14 are sequentially arranged. By arranging them side by side, the inductor L1 and the inductor L3 are coupled, and the inductor L3 and the inductor L4 are coupled.

  Further, the first layer input terminal T1 and the first resonator 12 are connected by connecting the input terminal T1 and the capacitor electrode C1 on the left side of the third layer by a via V extending from the first layer to the fourth layer. . The input terminal T1 and the inductor L1 of the first resonator 12 are connected to the via V extending from the first layer to the fourth layer, the capacitor electrode C1 on the left side of the third layer, and the capacitor electrode C1 to the tenth. Via via V extending to the layer.

  Furthermore, the input side additional line La is arranged on the fourth layer, and the tip of the via V extending from the input terminal T1 to the fourth layer is connected to one end of the fourth layer additional line La. The other end of the input side additional line La is connected to the capacitor electrode C1 on the left side of the third layer through the via V (the capacitor C1 of the first resonator 12), and thereby the additional line in parallel with the input line Li. La was provided in the input unit 15.

  The connection between the output terminal T2 of the first layer and the third resonator 14 is also made by the output line Lo and the output side additional line Lb as in the case of the input unit 15. Specifically, this is performed by connecting the output terminal T2 and the capacitor electrode C3 on the right side of the third layer by another via V extending from the first layer to the fourth layer. The output terminal T2 and the inductor L4 of the third resonator 14 are connected to the via V extending from the first layer to the fourth layer, the capacitor electrode C3 on the right side of the third layer, and the capacitor electrode C3 to the tenth. Via via V extending to the layer.

  Further, an output side additional line Lb is arranged on the fourth layer, and the tip of the via V extending from the output terminal T2 to the fourth layer is connected to one end of the fourth layer additional line Lb, while the output side additional line Lb is connected. Is connected to the capacitor electrode C3 on the right side of the third layer (capacitor C3 of the third resonator 14) via the via V, whereby the output line 16 includes the additional line Lb in parallel with the output line Lo. .

  The frequency characteristics of the BPF chip thus formed are shown in FIGS. 3A to 3D. 5, FIG. 6 and FIGS. 7A to 7D are a circuit diagram of a multilayer BPF according to a comparative example, a plan view showing the arrangement of conductor patterns on each layer of the multilayer substrate, and a diagram showing frequency characteristics, respectively. However, the BPF of this comparative example differs from the BPF of the present embodiment only in that the input side additional line La and the output side additional line Lb are not provided (FIGS. 5 and 6 (d)). reference).

  As is clear from the comparison between FIG. 3A and FIG. 7A, the spurious S is generated in the high frequency region in the BPF of the comparative example, whereas according to the present embodiment, such high frequency spurious is generated. It can be suppressed.

  Furthermore, FIG. 3E is a diagram showing a passing attenuation characteristic when only one of the input side additional line La and the output side additional line Lb is provided in the embodiment. As is apparent from this result, the spurious suppression effect is somewhat inferior to that of the above-described embodiment in which the input lines La and Lb are provided on both the input and output sides. Even if it is provided, it is possible to obtain a better spurious suppression effect than the comparative example. FIG. 3E shows the result when only the output side additional line Lb is provided without the input side additional line La, but conversely, only the input side additional line La is provided without the output side additional line Lb. The same was true for the case.

[Second Embodiment]
FIG. 4 shows a BPF according to the second embodiment of the present invention. As shown in the figure, the BPF is different from the first embodiment in which the input side additional line La and the output side additional line Lb are arranged in a different layer from the input line Li and the output line Lo. The output side additional line Lb is arranged in the same layer as the input line Li and the output line Lo.

  Specifically, the input side additional line La is connected to the tip of the via V extending from the input terminal T1 of the first layer to the third layer and the other end is connected to the capacitor electrode C1 on the left side of the third layer. By arranging in three layers, a path for inputting a signal from the input terminal T1 to the first resonator 12 (capacitor electrode C1) via the via V is formed in parallel with the input line Li.

  Similarly, for the output unit 16, one end is connected to the tip of the via V extending from the output terminal T2 of the first layer to the third layer, and the other end is connected to the capacitor electrode C3 on the right side of the third layer. By arranging the additional line Lb on the third layer, a path for outputting a signal from the third resonator 14 (capacitor electrode C3) to the output terminal T2 via the via V is formed in parallel with the output line Lo.

  Since the other configuration is the same as that of the first embodiment, the same reference numerals are given and redundant description is omitted.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it is obvious to those skilled in the art that various modifications can be made within the scope of the claims. is there.

  For example, the specific circuit configuration and the number of connection stages of the laminated structure and the resonator are not limited to those of the embodiment. In the above embodiment, the input section and the output section are each provided with two lines. However, the present invention includes that the input section and the output section are constituted by three or more lines (provided with two or more additional lines). Is not excluded.

  Furthermore, the additional line according to the present invention (hereinafter, the input side additional line is described, but the same applies to the output side additional line) is one in which one end is connected to the input terminal and the other end is connected to the first-stage resonator. It is not always necessary to be completely parallel to the line (over the entire length of the path from the input terminal to the first stage resonator). For example, the first stage branches off from the middle of the input line connecting the input terminal and the first stage resonator. It may be connected to the resonator, one end is directly connected to the input terminal, the other end may be connected in the middle of the input line, and both ends of the additional line are both input line May be connected in the middle (a structure that branches from the middle of the input line and joins the input line again before connecting to the first resonator). Although it is desirable from the viewpoint of reducing the inductance that the additional line is provided so as to be parallel to the entire length of the input line, it is possible to reduce the inductance of the input unit in any of the above structures. Also, in the middle of the signal path between the input terminal and the first stage resonator, neither the path via the input line nor the path via the additional line is a conductor line formed on the surface of the conductor layer. (For example, an interlayer connection conductor such as a side electrode provided on a side surface of a via or a chip) may be interposed.

DESCRIPTION OF SYMBOLS 11 Band pass filter 12 1st resonator 13 2nd resonator 14 3rd resonator 15 Input part 16 Output part C1, C2, C3 Capacitor C4 Bypass capacitor (bypass capacitor)
G ground electrode L1, L2, L3, L4 Inductor La Input side additional line Lb Output side additional line Li Input line Lo Output line S High band spurious T1 Input terminal T2 Output terminal TG Ground terminal V Via hole

Claims (5)

An input terminal capable of inputting a signal;
An output terminal capable of outputting a signal;
A plurality of resonators connected between the input terminal and the output terminal to form a predetermined passband;
An input unit including an input line that electrically connects a first-stage resonator closest to the input terminal and the input terminal among the plurality of resonators;
A band-pass filter comprising: an output line that electrically connects a final-stage resonator closest to the output terminal and the output terminal among the plurality of resonators;
A band-pass filter comprising: an input side additional line connected in parallel to the input line to reduce inductance of the input unit. An input terminal capable of inputting a signal;
An output terminal capable of outputting a signal;
A plurality of resonators connected between the input terminal and the output terminal to form a predetermined passband;
An input unit including an input line that electrically connects a first-stage resonator closest to the input terminal and the input terminal among the plurality of resonators;
A band-pass filter comprising: an output line that electrically connects a final-stage resonator closest to the output terminal and the output terminal among the plurality of resonators;
An output side additional line connected in parallel to the output line to reduce inductance of the output unit is provided in the output unit. The band-pass filter according to claim 1, further comprising an output-side additional line connected to the output line in parallel to reduce inductance of the output unit. A band-pass filter comprising a laminated substrate having a plurality of wiring layers, the input terminal, the output terminal, the plurality of resonators, the input unit, and the output unit;
While arranging the input side additional line in a conductor layer different from the input line,
The band-pass filter according to claim 3, wherein the output side additional line is arranged in a conductor layer different from the output line. A band-pass filter comprising a laminated substrate having a plurality of wiring layers, the input terminal, the output terminal, the plurality of resonators, the input unit, and the output unit;
While arranging the input side additional line in the same conductor layer as the input line,
The band-pass filter according to claim 3, wherein the output side additional line is disposed on the same conductor layer as the output line.

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