JP2013219097A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce electric resistance of a high melting point metal film at low cost.SOLUTION: A semiconductor device manufacturing method comprises a process of forming a high melting point metal film on a semiconductor substrate by a sputtering method using a target including a boron-added high melting point metal. The semiconductor device manufacturing method comprises: (a) a process of forming a gate electrode composed of a first high melting point metal film so as to fill in a groove in an active region; (b) a process of forming a second high melting point metal film on a first film; (c) a process of forming a contact plug by forming a third high melting point metal film on a third film so as to fill in a contact hole; and (d) a process of further forming a fourth high melting point metal film on an insulation film. At least in one process among the processes, the high melting point metal film is formed by the sputtering method using the target including the boron-added high melting point metal.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  With the miniaturization of semiconductor devices, there is a problem that the resistance of wiring made of a refractory metal such as tungsten wiring used in the semiconductor device becomes higher than the design target value in the conventional resistance value. Thus, conventionally, there has been a demand for lower resistance of refractory metal wiring. It is known that resistance of refractory metals such as tungsten decreases as the crystal grains become larger.

Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-194468) discloses a method for growing W by reducing WF ₆ gas with B ₂ H ₆ gas to form W nuclei.

  Patent Document 2 (Japanese Patent Laid-Open No. 2004-270035) discloses that tungsten is formed by a sputtering method using krypton or xenon as a sputtering gas, and its resistivity is lowered.

JP 2007-194468 A JP 2004-270035 A

However, in the method of Patent Document 1, B ₂ H ₆ gas is used for W nucleation, and boron is insufficiently introduced into tungsten, and is insufficient for reducing the resistance of tungsten. .

  Further, the krypton and xenon gas used in the method of Patent Document 2 is more expensive than the argon gas, and there is a problem that the cost increases when this method is used.

  As described above, conventionally, it has been impossible to sufficiently reduce the resistance of the refractory metal film at low cost.

One embodiment is:
The present invention relates to a method for manufacturing a semiconductor device, comprising a step of forming a refractory metal film on a semiconductor substrate by sputtering using a target containing a refractory metal to which boron is added.

Other embodiments are:
Forming a groove in the active region of the semiconductor substrate;
Forming a gate insulating film on the inner surface of the groove;
Forming a gate electrode made of the first refractory metal film by forming a first refractory metal film so as to fill the trench;
Forming a first impurity diffusion layer in one of the regions on both sides of the active region and sandwiching the groove;
Forming a first film on the semiconductor substrate;
Forming a second refractory metal film on the first film;
The first film and the second refractory metal film are patterned so that at least a part of the first film and the second refractory metal film remain on the first impurity diffusion layer. Forming a bit line having the first film and the second refractory metal film;
Forming an insulating film on the semiconductor substrate;
Forming a contact hole in the insulating film so as to expose the other region of the active region on both sides of the groove.
Forming a second impurity diffusion layer in the other region of the active region;
Forming second and third films below the contact holes;
A contact plug having the second and third films and the third refractory metal film is formed by forming a third refractory metal film on the third film so as to fill the contact hole. Forming, and
Forming a fourth refractory metal film on the insulating film;
Forming a contact pad by patterning the fourth refractory metal film such that at least part of the fourth refractory metal film remains on the third refractory metal film;
Have
In at least one of the steps of forming the first, second, third and fourth refractory metal films, the refractory metal film is formed by sputtering using a target containing a refractory metal to which boron is added. The present invention relates to a method for manufacturing a semiconductor device.

  The electric resistance of the refractory metal film can be reduced at a low cost.

1 is a plan view illustrating a semiconductor device according to a first embodiment. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the first embodiment.

  In an example of the method for manufacturing a semiconductor device of the present invention, a refractory metal film is formed on a semiconductor substrate by sputtering using a target containing a refractory metal to which boron (boron) is added. By forming the refractory metal film using the sputtering method, the crystal grain size (grain size) of the refractory metal film can be increased. As a result, the electrical resistance of the refractory metal film can be reduced. In addition, since this sputtering method can be carried out by simply changing the target to a material containing a refractory metal to which boron is added in a conventional sputtering apparatus, the refractory metal film is formed at a low cost without increasing the manufacturing cost. Can be formed.

  As the sputtering apparatus used for the sputtering method, the same sputtering apparatus as conventionally used can be used except that a target containing a refractory metal to which boron is added is used. For example, an ECR sputtering apparatus, a DC magnetron sputtering apparatus, an RF magnetron sputtering apparatus, or the like can be used as the sputtering apparatus.

  The target can be produced, for example, by mixing boron and a refractory metal powder and sintering. The boron content in the target is preferably 0.01% by weight or more and 1.0% by weight or less. When the boron content is within these ranges, the crystal grain size of the refractory metal film can be effectively increased. The boron content in the target can be controlled by adjusting the mixing ratio of the boron and refractory metal powder when the target is produced.

  The refractory metal is not particularly limited, but tungsten (W), molybdenum (Mo), titanium (Ti), cobalt (Co), or nickel (Ni) is preferably used. Among these refractory metals, the effect of reducing the electrical resistance by the method of the present invention is large, and tungsten (W) is more preferably used as a material useful for each part of a semiconductor device such as a wiring or a contact plug. preferable.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the DRAM 100 according to the present embodiment, and shows a memory cell region of the DRAM 100. FIG. 1 is a schematic plan view showing an arrangement of an element isolation region, an element formation region, and a buried wiring of the DRAM 100. However, in FIG. 1, the capacitor located on the capacitor contact pad 42 and the upper metal wiring located on the capacitor are omitted in order to clarify the arrangement state of the components.

  2 is a cross-sectional view showing the configuration of the DRAM 100 according to the present embodiment. FIG. 2A is a cross-sectional view taken along line AA ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB ′ of FIG. Show. Here, FIG. 2A shows a cross section in the Y direction, whereas FIG. 2B strictly deviates from the X direction, but in this embodiment, it is described as a cross section in the X direction. To do. Further, in the DRAM 100 of the present embodiment, a silicon substrate is used as the base semiconductor substrate. Further, not only a single semiconductor substrate but also a state in which a semiconductor device is manufactured on the semiconductor substrate and a state in which the semiconductor device is formed on the semiconductor substrate are collectively referred to as a wafer.

  As shown in FIG. 1, the DRAM 100 has a memory cell region 60 and a peripheral region (not shown) in which driving transistors (not shown) are arranged outside the memory cell region 60. In the memory cell region 60, an element isolation film 9 (hereinafter referred to as “STI (Shallow Trench Isolation) 9”) in which an insulating film is embedded in an element isolation trench 4 provided in the silicon substrate 1, A partitioned element forming region 1A (hereinafter also referred to as “active region 1A”) is provided.

  As shown in FIG. 1, the plurality of embedded wirings 5 include an embedded word line 23 extending in the Y direction and an embedded wiring 22 for element isolation. The buried word line 23 and the buried wiring 22 for element isolation have the same structure but have different functions. The buried word line 23 functions as a gate electrode of the memory cell. The embedded wiring 22 for element isolation isolates adjacent elements (transistors) by maintaining a predetermined potential. That is, the parasitic transistors can be separated from each other adjacent elements on the same element formation region 1A by maintaining the element isolation buried wiring 22 at a predetermined potential. A plurality of bit lines 30 are arranged at a predetermined interval in a direction orthogonal to the embedded wiring 5 (X direction in FIG. 1).

  As shown in FIG. 2, the embedded wiring 22 covers a plurality of STI 9 and part of the upper surface of the silicon substrate 1. Each memory cell is formed in a region where the buried word line 23 and the element formation region 1A intersect. A plurality of memory cells are provided in the entire memory cell region 60, and a capacitor 48 is connected to each memory cell via a capacitor contact pad 42. As shown in FIG. 1, the capacitor contact pads 42 are arranged in the memory cell region 60 at a predetermined interval so as not to overlap each other. As shown in FIG. 1, the DRAM 100 of this embodiment has a 6F2 cell arrangement (F value is a minimum processing dimension) corresponding to a unit area in which the intervals in the X direction and the Y direction are 3F and 2F, respectively.

  As shown in FIG. 2, the DRAM 100 of this embodiment includes a buried gate type transistor in which a buried word line 23 that functions as a gate electrode is completely buried in the silicon substrate 1. The buried gate type transistor is provided in the element formation region 1A surrounded by the STI 9 serving as the element isolation region of the silicon substrate 1. The STI 9 is obtained by laminating the insulating film 6 and the insulating film 7 in the groove of the silicon substrate 1. The buried gate type transistor includes a gate insulating film 16 covering an inner wall of a groove provided in the element formation region 1A, an intervening layer 17 covering an upper surface portion and a part of a side surface portion of the gate insulating film 16, A conductive film 18 to be a buried word line 23 provided inside the intervening layer 17, a first impurity diffusion layer 26 to be one of the source / drain regions provided in the low-concentration impurity diffusion layer 11, The second impurity diffusion layer 37 serving as the other drain region is included. The low-concentration impurity diffusion layer 11 is provided above the element formation region 1A excluding the region where the gate insulating film 16 is provided, and has a conductivity type opposite to the conductive impurity contained in the silicon substrate 1 in large quantities. Is a diffused layer. The upper surface of the conductive film 18 is covered with a liner film 20 and a buried insulating film 21.

  In the element formation region 1A shown in FIG. 2B, two buried gate transistors having a buried word line 23 are shown for convenience of explanation, but there are thousands of memory cell regions in an actual DRAM. Up to several hundred thousand buried gate type transistors are arranged. However, although the conductive film 18A shown in FIG. 2B has the same structure as the embedded word line 23, it does not function as a word line, and electrically isolates adjacent embedded gate type transistors. It is a buried wiring 22.

  As shown in FIG. 2A, the buried gate type transistor of this embodiment has a structure in which a part of the buried wiring 22 is buried in the upper surface of the STI 9 arranged in the extending direction of the buried wiring 22. It has become. That is, the STI 9 is disposed such that the height of the upper surface is lower than the height of the surface of the silicon substrate 1 between the adjacent STIs 9. Thus, on the upper surface of the silicon substrate 1, a saddle-shaped silicon protrusion 1 </ b> B is provided in which the embedded portion of the STI 9 by the embedded wiring 22 and the bottom surface of the embedded wiring 22 are connected via the gate insulating film 16. . Since the buried word line 23 has the same structure as the buried wiring 22, a similar buried portion of STI 9 and a saddle-shaped silicon protrusion 1B are provided below the buried word line 23. ing.

  The saddle-shaped silicon protrusion 1B can function as a channel when the potential difference between the source region and the drain region exceeds a threshold value. The buried gate type transistor of this embodiment is a saddle fin type transistor having a channel region such as a saddle-shaped silicon protrusion 1B. By using a saddle fin type transistor as the buried gate type transistor, there is an advantage that the on-current is increased.

  Next, the configuration above the buried gate type transistor will be described with reference to FIG. In the memory cell region of the DRAM 100, a plurality of memory cells having the embedded gate transistor and the capacitor 48 are provided. The capacitor 48 is a cylinder type capacitor, and includes a lower electrode 45, a capacitive insulating film 46, and an upper electrode 47. The lower electrode 45 has a cylindrical shape and has an inner wall and an outer wall, and the inner wall side is embedded with a capacitive insulating film 46 and an upper electrode 47. The first impurity diffusion layer 26 of the buried gate transistor is connected to a conductive film 27 provided on the first impurity diffusion layer 26. Here, the conductive film 27 and the conductive film 28 provided on the conductive film 27 constitute a bit line 30. Further, the upper surface of the bit line 30 is covered with a mask film 29, and the side surface portion thereof is covered with an insulating film 31. The second impurity diffusion layer 37 of the buried gate transistor is connected to the lower electrode 45 through a capacitor contact plug 41 and a capacitor contact pad 42 provided on the second impurity diffusion layer 37. Here, the capacitor contact plug 41 has a laminated structure in which an intervening layer 39 is inserted between the conductive film 38 and the conductive film 40, and the side surface portion is covered with the sidewall insulating film 36. Further, since the capacitor contact pad 42 is provided to secure an alignment margin between the capacitor 48 and the capacitor contact plug 41, it is not necessary to cover the upper surface of the capacitor contact plug 41 as shown in FIG. It suffices to be located on the capacitor contact plug 41 and connected to at least a part thereof.

  The side surfaces of the bit line 30, the mask film 29, and the capacitor contact plug 41 are formed on the first interlayer insulating film 24, the insulating film 31, the liner film 32, and the coating insulating film 33 (hereinafter referred to as “SOD (Spin On Dielectrics) 33”). The capacitor contact pad 42 is covered with a stopper film 43 for protecting the SOD 33. A third interlayer insulating film 44 is provided on the stopper film 43. Since the cylinder hole 44 </ b> A penetrating the third interlayer insulating film 44 and the stopper film 43 is covered with the lower electrode 45, the outer wall of the lower electrode 45 is in contact with the third interlayer insulating film 44 and the stopper film 43. The upper surface of the third interlayer insulating film 44 is covered with a capacitive insulating film 46, and the upper surface of the capacitive insulating film 46 is covered with an upper electrode 47.

  The upper electrode 47 is covered with a fourth interlayer insulating film 49. A contact plug 50 is provided in the fourth interlayer insulating film 49, and an upper metal wiring 51 is provided on the upper surface of the fourth interlayer insulating film 49. The upper electrode 47 of the capacitor 48 is connected to the upper metal wiring 51 through the contact plug 50. The upper metal wiring 51 and the fourth interlayer insulating film 49 are covered with a protective film 52.

  In addition, although the cylinder type capacitor which uses only the inner wall of the lower electrode 45 as an electrode is described as a capacitor in this embodiment, a capacitor is not limited to this. For example, it is possible to change to a crown type capacitor that uses the inner wall and the outer wall of the lower electrode 45 as electrodes. On the capacitor, a wiring layer including an upper metal wiring 51 and a protective film 52 is provided via a fourth interlayer insulating film 49. In the present embodiment, a single-layer wiring structure having one wiring layer is described as an example, but the present invention is not limited to this. For example, it is possible to change to a multilayer wiring structure constituted by a plurality of wirings and an interlayer insulating film.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 3 to 24, taking the case where the semiconductor device is a DRAM 100 as an example. In each figure, (a) is a view corresponding to the A-A 'section in FIG. 1, and (b) is a view corresponding to the B-B' section in FIG. 2A is a cross section parallel to the Y direction, and FIG. 2B is also described as a cross section in the X direction.

As shown in FIG. 3, a sacrificial film 2 which is a silicon oxide film (SiO ₂ ) by a thermal oxidation method and a silicon nitride film (Si ₃ N by a thermal CVD (Chemical Vapor Deposition) method are formed on a P-type silicon substrate 1. ₄ ) The mask film 3 is sequentially deposited. Next, the mask film 3, the sacrificial film 2 and the silicon substrate 1 are patterned by using a photolithography technique and a dry etching technique, and an element isolation groove 4 (trench) for partitioning the element formation region 1A is formed in the silicon substrate 1. To form. The upper portion of the silicon substrate 1 that becomes the element formation region 1A is covered with a mask film 3.

  As shown in FIG. 4, an insulating film 6 that is a silicon oxide film is formed on the surfaces of the silicon substrate 1 and the mask film 3 by a thermal oxidation method. Thereafter, an insulating film 7 which is a silicon nitride film is deposited by thermal CVD so as to fill the inside of the element isolation trench 4, and then etched back, so that the insulating film is formed only inside the element isolation trench 4. 7 remains.

  As shown in FIG. 5, after the buried film 8 which is a silicon oxide film is deposited so as to fill the inside of the element isolation trench 4 by plasma CVD, the mask film 3 formed in FIG. 3 is exposed. CMP (Chemical Mechanical Polishing) is performed until the surface of the buried film 8 is planarized.

  As shown in FIG. 6, the mask film 3 and the sacrificial film 2 are removed by wet etching, and a part of the silicon substrate 1 is exposed. Further, the buried film 8 on the surface of the element isolation trench 4 is made to be substantially equal to the position of the exposed surface of the silicon substrate 1. Through the above processing, the STI 9 composed of the insulating films 6 and 7 is formed. In the method of manufacturing the DRAM 100 according to the present embodiment, the STI 9 is formed, thereby forming the line-shaped element formation region 1A and the peripheral region (not shown) in the memory cell region 60 as shown in FIG. .

  After the STI 9 is formed, a sacrificial film 10 that is a silicon oxide film is formed on the surface of the silicon substrate 1 by thermal oxidation. Thereafter, an N-type low-concentration impurity diffusion layer 11 is formed by injecting a low-concentration N-type impurity (such as phosphorus) into the silicon substrate 1 by an ion implantation method. The low concentration impurity diffusion layer 11 functions as a part of the source / drain (S / D) region of the transistor.

  As shown in FIG. 7, a lower layer mask film 12 which is a silicon nitride film is formed on the sacrificial film 10 by a CVD method, and a carbon film (amorphous carbon film) is formed on the lower layer mask film 12 by a plasma CVD method. The upper mask film 13 is sequentially deposited. Thereafter, an opening 13A is formed in the upper mask film 13 and the lower mask film 12, and a part of the silicon substrate 1 is exposed.

As shown in FIG. 8, the silicon substrate 1 exposed from the opening 13A is etched by dry etching to form a gate electrode groove (trench) 15 having a width X3 of 35 nm. This dry etching is inductively coupled plasma (ICP: I nductively C oupled P lasma) by reactive ion etching: a (RIE Reactive Ion Etching) method, tetrafluoromethane and (CF ₄₎ and sulfur hexafluoride (SF ₆₎ Chlorine (CL ₂ ) and helium (He) are used as process gases, and the bias power is 100 to 300 W and the pressure is 3 to 10 Pa. The gate electrode trench 15 is formed as a line pattern extending in the Y direction intersecting the element formation region 1A and the peripheral region (not shown). When forming the gate electrode trench 15, the STI 9 is etched deeper than the surface of the silicon protrusion 1B. By this etching, a saddle-shaped silicon protrusion 1B having a height Z1 from the upper surface of the STI 9 of 55 nm remains. This saddle-shaped silicon protrusion 1B functions as a channel region of the transistor.

  As shown in FIG. 9, a gate insulating film 16 is formed. As the gate insulating film 16, a silicon oxide film formed by a thermal oxidation method can be used. Thereafter, tungsten (W) containing boron (boron) is formed by sputtering using an intervening layer 17 made of titanium nitride (TiN) by CVD and a tungsten target to which boron (boron) is added according to the method of the present invention. A conductive film (first refractory metal film) 18 is sequentially deposited.

  As shown in FIG. 10, in the gate electrode trench 15, the upper portion of the conductive film 18 that has become unnecessary by dry etching so that the conductive film 18 remains with a thickness Z5 from the upper surface of the silicon protrusion 1B of about 145 nm. Remove. In this dry etching, the bias is not applied to the silicon substrate 1 and the selection ratio of the conductive film 18 to the intervening layer 17 and the gate insulating film 16 is 6 or more. Can be easily left, and the thickness and variation of the conductive film 18 do not occur. Note that the height of the remaining conductive film 18 can be controlled by the processing time of dry etching.

  The unnecessary intervening layer 17 is removed by dry etching so that the intervening layer 17 remains at the same height as the surface of the conductive film 18 at the bottom of the gate electrode trench 15. In this dry etching, the bias is not applied to the silicon substrate 1 and the selection ratio of the intervening layer 17 to the lower mask film 12 and the gate insulating film 16 is 6 or more. Only can be easily left. Note that the height of the remaining intervening layer 17 can be controlled by the dry etching processing time. By this dry etching, the buried word line 23 and the buried wiring 22 composed of the intervening layer 17 and the conductive film 18 can be formed at the bottom of the gate electrode trench 15.

As shown in FIG. 11, a liner film 20 that is a silicon nitride film is formed by thermal CVD so as to cover the upper surface of the remaining conductive film 18 and the inner wall of the gate electrode groove 15. Next, a buried insulating film 21 is deposited on the liner film 20. As the buried insulating film 21, a silicon oxide film formed by a plasma CVD method, an SOD film as a coating film, or a laminated film thereof can be used. When the SOD film is used, after the formation, an annealing process is performed in a high-temperature water vapor (H ₂ O) atmosphere to modify the film into a solid film.

  As shown in FIG. 12, after the buried insulating film 21 is removed by CMP until the liner film 20 is exposed, the lower mask film 12, the sacrificial film 10, the buried insulating film 21, and the liner film 20 are etched back. Is partially removed so that the surface of the buried insulating film 21 is approximately as high as the surface of the silicon substrate 1. As a result, the upper surfaces of the buried word line 23 and the buried wiring 22 for element isolation are insulated.

  As shown in FIG. 13, a first interlayer insulating film 24, which is a silicon oxide film by plasma CVD, is formed so as to cover the silicon substrate 1. Thereafter, a part of the first interlayer insulating film 24 is removed by a photolithography technique and a dry etching technique, and a bit contact opening 25 is formed. As shown in FIGS. 1 and 13, the surface of the silicon substrate 1 is exposed at the portion where the bit contact opening 25 and the element formation region 1A overlap. After the bit contact opening 25 is formed, an N-type impurity (such as arsenic) is ion-implanted into the bottom of the bit contact opening 25 to form an N-type first impurity diffusion layer 26 near the surface of the silicon substrate 1. The formed N-type first impurity diffusion layer 26 functions as a source / drain region of the transistor.

  As shown in FIG. 14, a conductive film (polysilicon film) containing an N-type impurity (phosphorus or the like) by thermal CVD so as to cover the first impurity diffusion layer 26 and the first interlayer insulating film 24. A conductive film (second high melting point) made of tungsten (W) containing boron (boron) by sputtering using a tungsten target doped with boron (boron) according to the method of the present invention by the first film 27). (Metal film) 28 and a mask film 29 which is a silicon nitride film formed by plasma CVD are sequentially deposited.

  As shown in FIG. 15, the laminated film of the conductive film 27, the conductive film 28, and the mask film 29 is patterned into a line shape, and the bit line 30 composed of the conductive film 27 and the conductive film 28 is formed. The width Y7 and the interval Y8 of the bit line 30 in the Y direction are 50 nm, respectively. Hereinafter, the mask film 29 remaining on the upper surface of the bit line 30 may be referred to as the bit line 30. The bit line 30 is formed as a pattern extending in the X direction intersecting with the buried word line 23. In FIG. 1, the bit line 30 is shown in a straight line shape orthogonal to the embedded word line 23, but may be arranged in a partially curved shape. The conductive film 27 constituting the lower layer of the bit line 30 and the first impurity diffusion layer 26 (one of the source / drain regions) are connected to the surface portion of the silicon substrate 1 exposed in the bit contact opening 25.

  As shown in FIG. 16, after forming an insulating film 31 which is a silicon nitride film by a thermal CVD method so as to cover the side surface of the bit line 30, a silicon nitride film or the like by a thermal CVD method is formed so as to cover the upper surface. A liner film 32 is formed.

As shown in FIG. 17, after depositing an SOD film 33 as a coating film so as to fill a space between adjacent bit lines 30, an annealing process is performed in a high-temperature water vapor (H ₂ O) atmosphere. To a solid film. Next, after removing the SOD film 33 by CMP until the upper surface of the liner film 32 is exposed, a second interlayer insulating film 34, which is a silicon oxide film, is formed by plasma CVD, and the surface of the SOD film 33 is formed. cover.

  As shown in FIG. 18, a capacitor contact hole 35 penetrating through the second interlayer insulating film 34 and the SOD film 33 is formed by using a photolithography method and a dry etching method. Here, the capacitor contact hole 35 is formed by the SAC (Self Alignment Contact) method using the insulating film 31 and the liner film 32 formed on the side surface of the bit line 30 as sidewalls. The surface of the silicon substrate 1 is exposed at the portion where the capacitor contact hole 35 and the element formation region 1A overlap. A silicon nitride film is formed by thermal CVD so as to cover the inner wall of the capacitor contact hole 35, and then etched back to form a sidewall (SW) insulating film 36 on the side surface of the capacitor contact hole 35. . After forming the sidewall insulating film 36, N-type impurities (such as phosphorus) are ion-implanted into the silicon substrate 1 to form an N-type second impurity diffusion layer 37 near the surface of the silicon substrate 1. The formed N-type second impurity diffusion layer 37 functions as a source / drain region of the transistor.

  As shown in FIG. 19, a polysilicon film containing phosphorus is deposited inside the capacitor contact hole 35 by thermal CVD, and then etched back to form a polysilicon film at the bottom of the capacitor contact hole 35. A conductive film (second film) 38 is left. Thereafter, an intervening layer (third film) 39 made of cobalt silicide (CoSi) is formed on the upper surface of the conductive film 38 by sputtering, and then the inside of the capacitor contact hole 35 is filled. A conductive film (third refractory metal film) 40 that is tungsten (W) containing boron (boron) is deposited by sputtering using a tungsten target to which boron (boron) is added. Next, the conductive film 40, the second interlayer insulating film 34, the liner film 32, and the insulating film 31 are removed by CMP until the surface of the mask film 29 is exposed, so that the conductive film 40 is only inside the capacitor contact hole 35. To remain. As a result, a capacitive contact plug 41 composed of the laminated conductive film 38, the intervening layer 39, and the conductive film 40 is formed.

  As shown in FIG. 20, above the silicon substrate (wafer) 1, boron (WN) by sputtering and boron (boron) added with boron (boron) according to the method of the present invention are sputtered using boron ( A laminated film in which a tungsten (W) film (fourth refractory metal film) containing boron is sequentially deposited is formed. Next, the capacitor contact pad 42 is formed by patterning the laminated film using a photolithography method and a dry etching method. Here, the capacitor contact pad 42 is connected to the conductive film 40 constituting the capacitor contact plug 41.

  As shown in FIG. 21, after a stopper film 43, which is a silicon nitride film formed by thermal CVD, is formed so as to cover the upper surface of the capacitor contact pad 42, a first silicon oxide film formed by plasma CVD is formed on the stopper film 43. A three-layer insulating film 44 is formed.

  As shown in FIG. 22, a cylinder hole 44A that penetrates the third interlayer insulating film 44 and the stopper film 43 so as to expose at least a part of the upper surface of the capacitive contact pad 42 by using a photolithography method and a dry etching method. Form. Next, a capacitor lower electrode 45 is formed of titanium nitride by CVD so as to cover the inner wall of the cylinder hole 44A. The lower surface of the lower electrode 45 at the bottom of the cylinder hole 44 </ b> A is connected to the capacitor contact pad 42.

As shown in FIG. 23, after forming a capacitive insulating film 46 by an ALD (Atomic Layer Deposition) method so as to cover the surface of the lower electrode 45, an upper electrode 47 of a capacitor made of titanium nitride by a CVD method is formed. Here, as the capacitor insulating film 46, zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or a laminated film thereof can be used.

  As shown in FIG. 24, after forming a fourth interlayer insulating film 49 which is a silicon oxide film by plasma CVD so as to cover the upper electrode 47, the fourth interlayer insulating film is formed by using a photolithography method and a dry etching method. A contact hole (not shown) is formed in 49. Next, after filling the contact hole with tungsten by CVD, excess tungsten on the upper surface of the fourth interlayer insulating film 49 is removed by CMP to form the contact plug 50. Next, an upper metal wiring 51 is formed by patterning after depositing aluminum (Al), copper (Cu), or the like on the upper surface of the fourth interlayer insulating film 49. At this time, the upper metal wiring 51 is connected to the upper electrode 47 through the contact plug 50. Thereafter, if the protective film 52 is formed so as to cover the upper metal wiring 51, the memory cell of the DRAM 100 is completed.

  In the first embodiment, the step of forming the conductive film 18 in FIG. 9, the step of forming the conductive film 28 in FIG. 14, the step of forming the conductive film 40 in FIG. 19, and the tungsten (W) containing boron in FIG. A film (a part of the laminated film) is formed by a sputtering method using a tungsten target to which boron is added. As a result, it is possible to increase the crystal grain size (grain size) of the conductive films 18, 28, 40 and the tungsten (W) film containing boron, and to reduce the electrical resistance. In addition, this sputtering method can be performed simply by changing the target to a material containing a refractory metal to which boron is added in a conventional sputtering apparatus, so that a conductive film or the like can be formed at a low cost without increasing the manufacturing cost. can do.

  In the first embodiment, the four conductive films 18, 28, and 40 and the tungsten film in FIG. 20 were formed by sputtering using a tungsten target to which boron was added. However, even when the four conductive films 18, 28, and 40 and the tungsten film in FIG. 20 are formed by sputtering using a tungsten target to which boron is added, Similarly, the resistance of the formed film can be reduced at low cost.

1 Silicon substrate 1A Element formation region (active region)
1B Silicon protrusion 1C Silicon protrusion 1D Silicon protrusion 2 Sacrificial film 3 Mask film 4 Element isolation trench (trench)
5 buried wiring 6 insulating film 7 insulating film 8 buried film 9 STI
10 Sacrificial film 11 Low-concentration impurity diffusion layer 12 Lower mask film 13 Upper mask film 13A Opening 14 Channel region 15 Gate electrode trench (trench)
15A hole 16 gate insulating film 17 intervening layer 17A intervening layer 18 conductive film 18A conductive film 19 cover film 20 liner film 21 buried insulating film 22 buried wiring 23 for element isolation buried word line 24 first interlayer insulating film 25 bit Contact opening 26 First impurity diffusion layer 27 Conductive film 28 Conductive film 29 Mask film 30 Bit line 31 Insulating film 32 Liner film 33 SOD (coating insulating film)
34 Second interlayer insulating film 35 Capacitor contact hole 36 Side wall insulating film 37 Second impurity diffusion layer 38 Conductive film 39 Intervening layer 40 Conductive film 41 Capacitor contact plug 42 Capacitor contact pad 43 Stopper film 44 Third interlayer insulating film 44A Cylinder Hole 45 Lower electrode 46 Capacitance insulating film 47 Upper electrode 48 Capacitor 49 Fourth interlayer insulating film 50 Contact plug 51 Upper metal wiring 52 Protective film 60 Memory cell region 100 DRAM
200 DRAM

Claims (14)

  A method for manufacturing a semiconductor device, comprising: forming a refractory metal film on a semiconductor substrate by a sputtering method using a target containing a refractory metal to which boron is added.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal is tungsten.   The method of manufacturing a semiconductor device according to claim 1, wherein the target contains 0.01 wt% or more and 1.0 wt% or less of boron. Forming a trench in the active region of the semiconductor substrate;
Forming an insulating film on the inner surface of the groove;
A step of forming a first refractory metal film so as to fill the groove by the step of forming the refractory metal film according to any one of claims 1 to 3,
A method for manufacturing a semiconductor device, comprising: The insulating film is a gate insulating film;
5. The method of manufacturing a semiconductor device according to claim 4, wherein the first refractory metal film is a gate electrode. Forming a first film on the semiconductor substrate;
Forming the second refractory metal film on the first film by forming the refractory metal film according to any one of claims 1 to 3;
Patterning the first film and the second refractory metal film;
A method for manufacturing a semiconductor device, comprising: In the step of patterning the first film and the second refractory metal film,
7. The bit line having the first film and the second refractory metal film is formed by patterning the first film and the second refractory metal film. The manufacturing method of the semiconductor device of description. Forming an insulating film on the semiconductor substrate;
Forming a contact hole in the insulating film;
Forming second and third films at the bottom of the contact hole;
A step of forming a third refractory metal film on the third film so as to embed the contact hole by the step of forming the refractory metal film according to claim 1. When,
A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the second and third films and the third refractory metal film embedded in the contact hole are contact plugs. After the step of forming the third refractory metal film,
A step of further forming a fourth refractory metal film on the insulating film by the step of forming the refractory metal film according to any one of claims 1 to 3.
Patterning the fourth refractory metal film such that at least a part of the fourth refractory metal film remains on the third refractory metal film;
The method of manufacturing a semiconductor device according to claim 8, wherein: In the step of patterning the fourth refractory metal film,
11. The method of manufacturing a semiconductor device according to claim 10, wherein the contact pad is formed by patterning the fourth refractory metal film. Forming a groove in the active region of the semiconductor substrate;
Forming a gate insulating film on the inner surface of the groove;
Forming a gate electrode made of the first refractory metal film by forming a first refractory metal film so as to fill the trench;
Forming a first impurity diffusion layer in one of the regions on both sides of the active region and sandwiching the groove;
Forming a first film on the semiconductor substrate;
Forming a second refractory metal film on the first film;
The first film and the second refractory metal film are patterned so that at least a part of the first film and the second refractory metal film remain on the first impurity diffusion layer. Forming a bit line having the first film and the second refractory metal film;
Forming an insulating film on the semiconductor substrate;
Forming a contact hole in the insulating film so as to expose the other region of the active region on both sides of the groove.
Forming a second impurity diffusion layer in the other region of the active region;
Forming second and third films below the contact holes;
A contact plug having the second and third films and the third refractory metal film is formed by forming a third refractory metal film on the third film so as to fill the contact hole. Forming, and
Forming a fourth refractory metal film on the insulating film;
Forming a contact pad by patterning the fourth refractory metal film such that at least part of the fourth refractory metal film remains on the third refractory metal film;
Have
In at least one of the steps of forming the first, second, third and fourth refractory metal films, the refractory metal film is formed by sputtering using a target containing a refractory metal to which boron is added. Forming a semiconductor device. After the step of forming the contact pad,
13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of forming a capacitor on the contact pad.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the capacitor is a cylinder type or a crown type capacitor.