JP2013218767A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a data bus structure capable of transferring data in parallel and at a high speed by reducing a difference between far and close ends of a data bus connecting a data input/output section to a memory cell array and the like.SOLUTION: A semiconductor device comprises: a data bus; a data input-output section that is connected to the data bus, and inputs and outputs data transmitted through the data bus; and a plurality of bus interface sections each of which is connected to the data bus, and inputs and outputs data for the data input-output section through the data bus. The data bus is arranged and wired so that a wiring length of the data bus from each of the plurality of bus interface sections to the data input-output section becomes equal to each other.

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including a data storage unit, an input / output circuit for data stored in the data storage unit, and a data bus connecting the data storage unit and the input / output circuit.

  Some semiconductor devices incorporating memories such as DRAMs and flash memories have built-in large-capacity memories on the order of gigabits due to advances in microfabrication technology and circuit technology of semiconductor devices. Furthermore, as the speed of systems using semiconductor devices increases, it becomes necessary to enable high-speed data transfer between the memory and the data input / output unit that inputs and outputs read / write data to and from the memory. It is coming.

  Further, the capacity, the number of bits, and the number of banks of the memory built in the semiconductor device are various, and the layout arrangement is also various. Further, the number and arrangement of data input / output terminals for inputting / outputting read / write data to / from the memory vary depending on the specifications.

  For example, DRAMs having an internal storage capacity of 4 Gbits are already being mass-produced. As for data input / output to / from the outside, DDR SDRAM (Double Data Rate Synchronous DRAM) transfers the read / write data to the outside in synchronism with both the clock and the rising and falling edges, thereby increasing the system speed. There are also products that can read and write data at a transfer rate such that the data transfer is possible and the transfer rate exceeds 1 Gbps.

  Furthermore, depending on the application, the number of bits of the memory may be as large as 32 bits or more, and products that input / output in parallel from the same number of data input / output terminals (DQ terminals) according to the number of bits of the memory are required. It may become. In such a product, it is necessary to simultaneously input / output multi-bit read / write data from a data input / output terminal (DQ terminal) in parallel and to perform high-speed data transfer with a large-capacity memory array.

  Note that Patent Document 1 describes a semiconductor device on which a semiconductor chip having pads arranged in a row in a peripheral portion is mounted.

Japanese Patent Laid-Open No. 11-87414

  The following analysis is given by the present invention. The memory array and the external input / output unit are connected by a data bus. There is a demand for data transfer on a data bus at high speed inside a semiconductor device.

  According to a first aspect of the present invention, a data bus, a data input / output unit that is connected to the data bus and performs input / output of data transmitted through the data bus, and the data bus are connected to the data bus. A plurality of bus interface units for inputting / outputting data to / from the input / output unit via the data bus, and the wiring length of the data bus from the plurality of bus interface units to the data input / output unit is Semiconductor devices that are arranged and wired so as to be equal to each other are provided.

  According to a second aspect of the present invention, the first data bus, the second data bus connected to the first data bus by a first connection point, and the second data bus are connected. A data input / output unit for inputting / outputting data transmitted through the second data bus, and the first and second data buses connected to the first data bus and connected to the data input / output unit, respectively. Three or more bus interface units for inputting / outputting data via the first data bus, wherein the first connection point is among the three or more bus interface units connected to the first data bus, A semiconductor device is provided in which the wiring lengths from the bus interface units connected to both ends of the first data bus are equal.

According to a third aspect of the present invention, a plurality of data input / output units, a plurality of first and second bus interface units provided corresponding to the plurality of data input / output units, respectively, A data input / output unit and a plurality of bit data buses connecting the plurality of first and second bus interface units in parallel, and the data bus includes the plurality of first bus interface units and the plurality of first bus interface units. A first data bus connecting a plurality of second bus interface units; a second data bus connecting the first data bus and the plurality of data input / output units;
Each bit of the data bus at the position where the wiring length from the first bus interface unit and the wiring length from the second bus interface unit are equal to each other in the first data bus. A semiconductor device connected to the corresponding bit of the two data buses is provided.

  According to each aspect of the present invention, it is possible to perform high-speed data transfer with little difference between the far and near ends on a data bus in a semiconductor device. In particular, when each bus interface unit is connected to a memory array having a different bank or address, when performing read / write access from the input / output unit via the data bus, the bus interface unit is connected to the data bus of each memory array. High-speed data transfer is possible without depending on it.

(A) Overall schematic layout, (b) Enlarged view of bank part, (c) Enlarged view of memory cell array, (d) Basic data input / output area FIG. It is a block diagram of the whole semiconductor device by one Embodiment. (A) The preferred schematic layout wiring diagram of the data input / output area according to one embodiment, and (b) The schematic layout wiring diagram of the data input / output area according to the comparative example. (A) The figure which shows an example of arrangement | positioning of the data output part by one Embodiment, (b) The figure which shows arrangement | positioning of the data output part by a comparative example. (A) The figure which shows an example of arrangement | positioning of the data input part by one Embodiment, and (b) The figure which shows arrangement | positioning of the data input part by a comparative example. (A) Waveform diagram of read operation, (b) Waveform diagram of write operation, (c) Waveform diagram showing dullness of internal data bus signal, and (d) Internal data bus signal at higher speed than It is a wave form diagram which shows dullness. (A) A diagram showing a flow of data input / output unit control signals in one whole chip, (b) a wiring diagram of data input / output unit control signals in a data input / output region of a comparative example, and (c) one embodiment of the present invention. It is a wiring diagram of a control signal in the form. (A) schematic wiring diagram of control signal according to comparative example, (b) waveform diagram of control signal according to comparative example, (c) schematic wiring diagram of control signal according to one embodiment, and (d) control according to one embodiment. It is a waveform diagram of a signal, (e) a schematic wiring portion of a control signal according to another comparative example, and (f) a waveform diagram of a control signal according to another comparative example. It is a figure which shows distribution of the consumption current at the time of burst write. It is the (a) arrangement | positioning figure of a data output part by the modification of one Embodiment, and (b) the arrangement | positioning figure of a data input part. (A), (b) is the arrangement wiring diagram which shows the modification of arrangement | positioning of the data input / output area | region in one Embodiment, respectively. (A), (b) is the arrangement wiring diagram which shows another modification of arrangement | positioning of the data input / output area | region in one Embodiment, respectively.

  An outline of an embodiment of the present invention will be described. As shown in the basic schematic layout wiring diagram of the data input / output area in FIG. 1D, a plurality of bus interface units (for example, 25-1 and 25-9) and a data input / output unit (for example, 28-5). Are connected and wired so that the wiring lengths of the data buses from the plurality of bus interface units to the data input / output unit are equal to each other. Yes.

  Therefore, regardless of the arrangement position of the bus interface unit and the data input / output unit with respect to the data bus, it is possible to suppress the difference between the far end and the far end of the data bus, and to transfer data at a high speed.

  Preferably, the wiring length of the first data bus (26-1) from the first bus interface unit (for example, 25-1) to the first connection point (A), and the second bus interface unit (25 The first connection point (A) is provided so that the wiring length (26-2) of the first data bus from -9) to the first connection point (A) is equal to each other. The second data bus (26-5) from the first connection point (A) to the data input / output unit (28-5) is common. Therefore, the wiring length can be made equal.

  More preferably, as shown in FIG. 3A, of the data input / output units (23-1 and 24-1), the input / output unit side bus interface unit (24-1) that interfaces the data bus. Is arranged in the vicinity of the first connection point (C). The wiring length of the data bus is shortened, and the wiring length of the data input / output unit control signal (71) is also shortened as shown in FIG. 7C to reduce the skew, thereby enabling high-speed data bus transfer. Become.

  Even when there are three or more bus interface units connected to the same data input / output unit, if they are connected to the tournament system as shown in FIG. 12A, from three or more bus interface units to the data input / output unit The data bus wiring length can be made equal. Further, as shown in FIG. 12B, the wiring area of the data bus is suppressed by connecting the data input / output units so that the wiring lengths from the bus interface units connected to both ends of the data bus are equal. In addition, the data bus wiring length from the bus interface unit connected to the farthest end is minimized, and high-speed data transfer with little difference between the far and far ends becomes possible.

  It should be noted that the drawings quoted in this summary and the attached drawing reference numerals are merely examples for assisting understanding, and are not intended to be limited to the illustrated embodiments.

  Following the outline description, the embodiment will be described more specifically with reference to the drawings.

[First Embodiment]
FIG. 2 is a block diagram of the entire semiconductor device 1 according to the first embodiment. The semiconductor device 1 is a DDR SDRAM (Double Data Rate Synchronous DRAM). In FIG. 2, 10 is a memory array, 11 is a row decoder that decodes a row address and drives a selected word line, 12 is a sense amplifier that senses data of a memory cell selected from the memory array, and 13 is a sense amplifier. Is a column selector that outputs data selected based on a column address out of a plurality of data sensed by the sensor to the outside of the memory array. The semiconductor device 1 is provided with four memory arrays 10 of Bank 0 to Bank 3, and a row decoder 11, a sense amplifier 12, and a column selector 13 are also provided for each memory array.

  Further, the read / write amplifier 31 is provided for every two memory arrays 10 arranged adjacent to each other. The read / write amplifier 31 and the column selector 13 are connected to each other by a wiring 35 such as an I / O line. At the time of data writing to each memory array 10, write data is written to the memory array 10 from the read / write amplifier 31 via the wiring 35, the column selector 13, and the sense amplifier 12. At the time of data reading from each memory array, data in the memory array 10 amplified by the sense amplifier 12 is input to the read / write amplifier 31 via the column selector 13 and the wiring 35.

  The read / write amplifier 31 is connected to the array interface unit (array-side bus interface unit) 25 via a wiring 27 such as a bus in the memory array area. Note that the memory array 10, the row decoder 11, the sense amplifier 12, the column selector 13, and the read / write amplifier 31 are circuit blocks arranged in the memory array region 42, and are standardized by the memory capacity, the number of bits, and the like.

  The array interface unit 25 is arranged on the outer boundary of the memory array area 42, connects the memory arranged in the memory array area 42 and the data bus 26, and interfaces read / write data between the memory and the data bus 26. It has a function to do. The data bus 26 is further connected to a data input / output unit 28, and the data input / output unit 28 is further connected to a DQ-PAD that is an external data input / output terminal 22. The data input / output unit 28 includes a circuit directly connected to the data bus 26, and includes an input / output unit side bus interface unit 24 for interfacing data input / output to / from the data bus 26, and an external input / output buffer 23. ing. The external input / output buffer 23 includes an input buffer for inputting write data to the memory from the external data input / output terminal 22 and an output buffer for outputting read data from the memory.

  The external input / output buffer 23 inputs / outputs data from an external data input / output terminal (DQ terminal) 22 in synchronization with both the rising edge and falling edge of the data strobe signal input / output from the DQS terminal. In the case of data write, the DQS terminal becomes an input terminal for the data strobe signal, and the write data sent from the outside is synchronized with both the rising edge and falling edge of the data strobe signal input from the DQS terminal. take in. On the other hand, in the case of data read, the DQS terminal serves as an output terminal for the data strobe signal, and the read data is sent to the external data input / output terminal (DQ terminal) in synchronization with the rising and falling edges of the data strobe signal output from the DQS terminal. 22 to output. The number of external data input / output terminals (DQ terminals) 22 is determined according to the number of bits for inputting / outputting data in parallel from the outside of the semiconductor device 1. The data input / output units 28 are provided in the same number as the number of external data input / output terminals (DQ terminals) 22 corresponding to the external data input / output terminals (DQ terminals) 22, respectively.

  The clock generator 20 generates an internal operation clock from a normal clock signal CK, an inverted clock signal / CK, and a clock enable signal CKE given from the outside. The command decoder 14 decodes a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE given from outside and gives them to the semiconductor device 1 from an external memory controller or the like. Decodes the read / write command. Based on the command decoded by the command decoder 14 and the state of the mode register 17, the control logic 15 is a signal necessary for executing the command to each part of the semiconductor device 1 in synchronization with the clock supplied from the clock generator 20. Is output. External address input terminals A0 to A13 and bank address input terminals BA0 and BA1 are connected to the mode register 17, the column address buffer / burst counter 16 and the row address buffer 18 via an internal address bus, respectively. When the mode register setting command is given, the mode register 17 sets the data given from the internal address bus in the register. The row address buffer 18 latches the row address and outputs it to the row decoder 11 when a bank active ACT command is given. The column address buffer / burst counter 16 latches and decodes the column address when a read command or a write command is given, and selects the column selector 13. When a burst read or burst write command is given, the column address is counted based on the designated burst length. The refresh counter circuit 19 counts up the refresh address.

  The DLL 21 generates a clock signal in phase with the external clock signal based on the external clock signal given from the external clock terminals CK and / CK, and controls the timing of data input / output from the external I / O terminal 22. To do. When the semiconductor device 1 is used for low power consumption and priority is given to low power consumption over timing accuracy of data input / output, the DLL 21 is not necessarily provided.

  Next, the arrangement in the semiconductor chip of the semiconductor device 1 according to the first embodiment will be described with reference to FIG. FIG. 1A is a schematic layout diagram of the entire semiconductor chip. In the drawing, pads 81 and 82 are provided at both ends of the chip in the Y-axis direction. The side on which the pad 81 is provided is an address control circuit area 41 in which circuits for controlling addresses such as the row address buffer 18 and the column address buffer / burst counter 16 (see FIG. 2) are arranged. The side on which the pad 82 is provided is a data input / output area 43 on which the array side bus interface unit (array interface unit) 25, the data bus 26, and the data input / output unit 28 are arranged.

  A 4-bank memory array area 42 is arranged between the address control circuit area 41 and the data input / output area 43. With the control wiring region 83 provided in the center of the semiconductor chip in the X-axis direction, the memory array region 42 of bank 0, bank 2 and the memory array region 42 of bank 1 and bank 3 are each 2 in the Y-axis direction. Banks are arranged side by side. A read / write amplifier 31 is disposed between the bank 0 and bank 2 memory array areas 42 arranged side by side in the Y-axis direction, and is shared by the bank 0 memory array area 42 and the bank 2 memory array area 42. ing. A Y decoder (column decoder) 44 is provided between the read / write amplifier 31 and the memory array areas 42 of the banks 0 and 2. Similarly, a read / write amplifier 31 and a Y decoder 44 are provided between the bank 1 and the memory array area 42 of the bank 3.

  FIG. 1B is an enlarged view of the memory array area 42 of the bank 1. As shown in FIG. 1B, in the memory array region 42, a large number of memory cell arrays 45 are arranged in a matrix. FIG. 1B shows the inside of the memory array region 42 of the bank 1, but the memory array regions 42 of other banks have the same configuration as the bank 1.

  FIG. 1C is an enlarged view of one memory cell array 45. A large number of memory cells 85 are arranged in a matrix in the memory cell array 45. A sub word driver SWD is provided at the end of the memory cell array 45 in the X axis direction, and a sub word line (not shown) extends from the sub word driver SWD to the memory cell 85 in the X axis direction. A sense amplifier 12 is provided at the end in the Y-axis direction, and an input / output wiring (bit line) 46 is connected between the memory cell 85 and the sense amplifier 12. Further, a control circuit SWC for controlling the memory cell array 45 is provided at the boundary between the sense amplifier 12 and the sub word driver SWD.

  FIG. 1D is a basic schematic layout wiring diagram of the data input / output area 43. At the boundary between the data input / output area 43 and the memory array area 42, data read from the memory array arranged in the memory array area 42 via the read / write amplifier 31 is received, and the memory arranged in the memory array area 42 is received. Array side bus interface units (array interface units) 25-1 to 25-16 for outputting data to be written to the array via the read / write amplifier 31 are provided. The array side bus interface units (array interface units) 25-1 to 25-8 are provided corresponding to the memory array areas 42 of the banks 0 and 2, and the array side bus interface units (array interface units) 25-9 to 25- 16 is provided corresponding to the memory array area 42 of the banks 1 and 3.

  The data input / output area 43 further includes data input / output sections 28-1 to 28-8, and is connected to the array side bus interface sections 25-1 to 25-16 by the data bus 26 provided in the data bus area 47. It is connected. FIG. 1D shows data buses 26-3 and 26-4 for connecting the array side bus interface units 25-8 and 25-16 to the data input / output unit 28-1 among the many wirings of the data bus 26. 26-6, and only the data buses 26-3, 26-4, and 26-6 that connect the array side bus interface units 25-1 and 25-9 to the data input / output unit 28-5 are illustrated.

  In FIG. 1D, for example, one data bus 26-3, 26-4, 26-6 connecting the array side bus interface units 25-8 and 25-16 to the data input / output unit 28-1. It is described as if the wiring. However, the data input / output unit 28 inputs / outputs data to / from the external data input / output terminal (DQ-PAD) 22 at high speed in synchronization with the clock, the rising edge, and the falling edge. For this reason, the data buses 26-3, 26-4, and 26-6 can be provided with a margin in the transfer speed of the data bus 26 by parallelizing the data bus 26 as about 2 to 8 parallel wires. Good.

  Each data input / output unit 28-1 to 28-8 is connected to an external data input / output terminal (DQ-PAD) 22. That is, the memory array arranged in the memory array area 42 is connected to the external data input / output terminal (DQ-PAD) 22 via the array-side bus interface unit 25, the data bus 26, and the data input / output unit 28. Read / write data can be accessed from the DQ-PAD connected to the outside of the semiconductor device 1 to the memory array in the memory array area 42. In the data input / output area 43, in addition to the external data input / output terminal (DQ-PAD) 22, an I / O buffer VDD power supply terminal VDDQ that supplies power to an input / output buffer provided in the data input / output unit 28 is provided. -VSS power supply terminal VSSQ-PAD for PAD and I / O buffer is provided.

  In the wiring of the data bus 26, each of the data input / output units 28-1 to 28-8 is connected to one of the array side bus interface units 25-1 to 25-8 corresponding to the banks 0 and 2, and the bank 1, 3 is connected to any one of the array side bus interface units 25-9 to 25-16 corresponding to 3. That is, each data input / output unit 28 is connected to each two array side bus interface units 25. In the data bus wiring from the data input / output units 28 to the array side bus interface unit 25 connected two by two, the data bus 26 from the data input / output unit 28 to the two array side bus interface units 25 is connected. Wiring is performed so that the wiring lengths are equal to each other. That is, first data buses (main lines) 26-1 to 26-that connect a plurality of (two in the example of FIG. 1D) array side bus interface units 25 connected to the same data input / output unit 28. 4 and second data buses (branch lines) 26-5 and 26-6 connected to the data input / output unit 28. The second data buses 26-5 and 26-6 are connected to the first data bus. The buses are connected to the first data buses 26-1 to 26-4 at the first connection points A and B where the wiring lengths from the plurality of array-side bus interface units 25 are equal.

  More specifically, the first data bus 26-1 to which the array side bus interface unit 25-1 is connected and the first data bus 26-2 to which the array side bus interface unit 25-9 is connected include an array Are connected to the second data bus 26-5 at the connection point A where the wiring lengths from the side bus interface units 25-1 and 25-9 are equal, and the second data bus is connected to the data input / output unit 28-5. It is connected. The first data bus 26-1 and the first data bus 26-2 have the same wiring length, and the second data bus 26-5 is shared by the array side bus interface units 25-1 and 25-9. Data bus. Accordingly, the wiring length of the data bus from the array side bus interface unit 25-1 to the data input / output unit 28-5 and the wiring length of the data bus from the array side bus interface unit 25-9 to the data input / output unit 28-5. Are equal to each other.

  Similarly, the first data buses 26-3 and 26-4 are connected to the second data bus 26-6 at the first connection point B having the same wiring length. Accordingly, the wiring length of the data bus from the array side bus interface unit 25-8 to the data input / output unit 28-1, and the wiring length of the data bus from the array side bus interface unit 25-15 to the data input / output unit 28-1. Are equal to each other.

  Since the wiring lengths of the first data buses from the array-side bus interface unit 25 are connected to the common second data bus at the first connection point where the wiring lengths are equal to each other, the wiring lengths of the entire data buses are equal to each other. Can be wired like this. Therefore, there is no difference in the wiring length of the data bus from the data input / output unit 28 to each array-side bus interface unit 25 connected to the same data input / output unit 28, and the near-end difference can be eliminated with respect to the signal delay of the data bus. it can.

  The arrangement of the array-side bus interface unit 25 is determined by the capacity of the memory array, the number of memory arrays, the number of banks, the configuration, etc., and the arrangement of the external data input / output terminals (DQ-PAD) 22 is Depends on product specifications. Since the data input / output unit 28 is provided for each external data input / output terminal (DQ-PAD) 22, how is the arrangement and number of the plurality of array side bus interface units 25 connected to the same data input / output unit 28? The wire length can be made equal even if the soldering is done. That is, in the first data bus that connects the plurality of array-side bus interface units 25, the data bus wiring length from each array-side bus interface unit 25 is connected to the corresponding data input / output unit 28 at the connection point. This is because it is connected to the second data bus.

  In FIG. 1 (d), the case where the number of array side bus interface units 25 connected to the same data input / output unit 28 is two has been described, but the same data input / output unit 28 is connected. The number of the array-side bus interface units 25 is not limited to two, and even when the number is three or more, the data bus is shared at a connection point where the data bus is tournament-type and has an equal wiring length from the array-side bus interface unit 25. By repeating the connection to the data bus, the wiring lengths from the three or more array-side bus interface units 25 to the data input / output unit 28 can be made equal to each other. When the number of array-side bus interface units 25 connected to the same data input / output unit 28 is three or more, when priority is given to the wiring area of the data bus, it is connected to the first data bus. Of the three or more array side bus interface units 25, the second data bus is connected at the connection point where the distances from the array side bus interface units 25 connected to both ends of the first data bus extending in the X-axis direction are equal. By connecting, the wiring length from the farthest array side bus interface unit 25 to the data input / output unit 28 can be made as short as possible. Details will be described later with reference to FIG.

  FIG. 3A shows a more preferable schematic layout wiring diagram of the data input / output area according to the first embodiment. As shown in FIG. 3A, an array interface area 51 is provided at the end closest to the memory array areas 42-1 and 42-2 arranged adjacent to the data input / output area in the Y-axis direction. The array-side bus interface unit 25 is disposed in the array. Further, in the Y-axis direction, a data bus area 47a for wiring the data bus 26 is provided on the opposite side of the array interface area 51 from the memory array areas 42-1 and 42-2. In FIG. 3A, the input / output unit side bus interface unit 24 including a circuit directly connected to the data bus among the circuits of the data input / output unit 28 is arranged in a part of the data bus region 47a, and the first The wiring length of the data bus (second data bus) from the connection point C to the input / output unit side bus interface unit 24 is shortened.

  A data input / output unit arrangement region 52 is provided on the opposite side of the array interface region 51 in the Y-axis direction with the data bus region 47a interposed therebetween. In the data input / output unit arrangement area 52, the external input / output buffer 23 which is not arranged in the data bus area 47a other than the input / output unit side bus interface unit 24 in the circuit of the data input / output unit 28 is arranged. That is, in FIG. 3A, the data input / output unit 28 is divided into the input / output unit side bus interface unit 24 and the external input / output buffer 23.

  A pad area 53 is provided on the opposite side of the data bus area 47a in the Y-axis direction with respect to the data input / output unit arrangement area 52. The pad area 53 is provided with a power pad (PAD) for supplying power to the external data input / output terminal (DQ-PAD) 22 and the input / output buffer.

  3A, the array-side bus interface unit 25-a has a memory array area 42-1 in which the bank 2 is arranged and a memory array area (not shown) in which the bank 0 is arranged. ). Similarly, the array-side bus interface unit 25-a is provided corresponding to a memory array area 42-2 in which the bank 3 is arranged and a memory array area (not shown) in which the bank 1 is arranged.

  The array side bus interface units 25-a and 25-b are both connected to the input / output unit side bus interface unit 24-1 by the data bus 26, but the wiring length Aa from the array side bus interface unit 25-a and They are connected to a common second data bus (branch line) at a connection point C where the wiring length Ba from the array side bus interface unit 25-b becomes equal. Furthermore, since the input / output unit side bus interface unit 24-1 is disposed in the vicinity of the connection point C, the wiring length itself of the second data bus (branch line) is short. FIG. 3A shows only the data bus between some of the array side bus interface units 25-a and 25-b and some of the input / output unit side bus interface units 24-1. This also applies to the data bus wiring between the array side bus interface unit 25 and the input / output unit side bus interface unit (not shown).

  Therefore, there is no difference between the far end and the far end between the array side bus interface unit 25 and the data input / output unit 28 (input / output unit side bus interface unit 24), and data can be transferred at high speed.

  FIG. 3B is a schematic layout diagram of a data input / output area according to a comparative example. The portions that are substantially the same as those in FIG. 3A, which is a preferred arrangement example of the first embodiment, are denoted by the same reference numerals, and only the portions that are different from FIG. In the data bus area 147, only the data bus 26 is arranged, and some circuits of the data input / output unit 28 are not arranged as shown in FIG. That is, all the data input / output units 28 are arranged in the data input / output unit arrangement area 152. In FIG. 3B, the array side bus interface units 25-a and 25-b are connected to the data input / output unit 28-1, and the array side bus interface unit 25-a to the data input / output unit 28- The wiring length Ab of the data bus up to 1 and the wiring length Bb of the data bus from the array side bus interface unit 25-b to the data input / output unit 28-1 are longer than the wiring length Ab. That is, the data bus wiring length Bb from the array-side bus interface unit 25-b to the data input / output unit 28-1 is equal to the data bus wiring from the array-side bus interface unit 25-a to the data input / output unit 28-1. Since the length is longer than the length Ab, the delay time of the data bus between the array side bus interface unit 25-b and the data input / output unit 28-1 is less than the array side bus interface unit 25-a and the data input / output unit 28-1. Becomes larger than the delay time of the data bus between the two and the far end difference occurs.

  That is, compared with the comparative example, in the first embodiment, as shown in FIG. 3A, the wiring length of the data bus between the array-side bus interface units 25 connected to the same data input / output unit 28 is as follows. By connecting to the same second data bus (branch line) at the same first connection point C, it is possible to eliminate the near-end difference. Further, among the circuits of the data input / output unit 28, the input / output unit side bus interface unit 24 including the circuit directly connected to the data bus is arranged so as to shorten the wiring length of the second data bus (branch line). By disposing in the vicinity of the connection point C, the data bus length can be shortened and high-speed data transfer can be realized.

  Next, in the circuit of the data input / output unit 28, the input / output unit side bus interface unit 24 disposed near the connection point of the data bus 26 and the external input / output buffer 23 disposed near the external data input / output terminal 22. A specific example will be described. A description will be given separately for a data output unit for outputting read data from the memory to the outside and a data input unit for inputting write data to the memory from the outside.

  FIG. 4A is a diagram illustrating an example of an arrangement of data output units according to the first embodiment. First, the circuit function of the data output unit will be described. The “read data selection + data latch circuit” 61 selects data output from the corresponding external data input / output terminal (DQ-PAD) 22 among the data transmitted through the data bus 26 and latches the data. The read clock synchronization circuit 62 selects data to be output in series from the external data input / output terminal (DQ-PAD) 22 in synchronization with the read clock among the data latched in the “read data selection + data latch circuit” 61. Output. A “slew rate adjustment + driver strength selection circuit” 63 adjusts the slew rate of the output driver 64 and selects the driver strength. For example, the slew rate can be adjusted by adjusting the rise time and fall time of the pre-buffer that is the previous stage of the final stage output transistor of the output driver 64. In addition, the driver strength can be selected based on the parallel number in which a plurality of final stage output transistors of the output driver 64 are provided in parallel and are simultaneously conducted. The output driver 64 outputs read data in series from the external data input / output terminal (DQ-PAD) 22 in synchronization with the read clock.

  In the first embodiment shown in FIG. 4A, among these, the “read data selection + data latch circuit” 61 is arranged in the vicinity of the first connection point C of the data bus (the data bus area 47a in FIG. 3A). The read clock synchronization circuit 62, “slew rate adjustment + driver strength selection circuit” 63, and output driver 64 are arranged near the external data input / output terminal (DQ-PAD) 22 (see FIG. 3A). It arranges in the output part arrangement | positioning area | region 52). That is, the data output unit of the input / output unit side bus interface unit 24 in FIG. 3A is the “read data selection + data latch circuit” 61, and the data output unit of the external input / output buffer 23 is the read clock synchronization circuit. 62, “slew rate adjustment + driver strength selection circuit” 63, and output driver 64.

  FIG. 4B shows the arrangement of the data output unit of the data input / output unit 28 shown as a comparative example in FIG. The circuit function itself is the same as the data output unit according to the first embodiment shown in FIG. 4A, but the arrangement is different. That is, all of “read data selection + data latch circuit” 61, read clock synchronization circuit 62, “slew rate adjustment + driver strength selection circuit” 63, and output driver 64 are in the vicinity of the external data input / output terminal (DQ-PAD) 22. (Data input / output unit arrangement area 152 in FIG. 3B).

  That is, when the arrangement of the data output unit in the first embodiment shown in FIG. 4A is compared with the comparative example shown in FIG. 4B, the “read data selection + data latch circuit” 61 is changed to the first of the data bus. The wiring length of the second data bus (branch line), which is a common data bus, is shortened by arranging it in the vicinity of the connection point C, and the distance between the near and far ends is eliminated and the wiring length of the entire data bus is shortened. Transmission of read data can be made possible.

  FIG. 5A is a diagram illustrating an example of an arrangement of data input units according to the first embodiment. First, the circuit function of the data input unit will be described. The input first stage circuit 66 compares the voltage of the data input from the external data input / output terminal (DQ-PAD) 22 with the REF signal input voltage which is a comparison level between the high level and the low level logic level, and determines the logic of the input data. Determine the level. The “delay adjustment + data latch circuit” 67 latches the signal that the input initial stage circuit 66 has determined the high level and the low level after adjusting the delay time by the delay circuit. The write clock synchronization circuit 68 shifts the data latched by the “delay adjustment + data latch circuit” 67 in synchronization with the write clock that is the internal timing of the semiconductor device 1. The write data decode circuit 69 decodes the data shifted by the write clock synchronization circuit 68 and outputs it to the data bus 26.

  In the first embodiment shown in FIG. 5A, the input initial stage circuit 66 and the “delay adjustment + data latch circuit” 67 are arranged near the external data input / output terminal (DQ-PAD) 22 (see FIG. ) In the data input / output unit arrangement area 52), the write clock synchronization circuit 68 and the write data decode circuit 69 are arranged in the vicinity of the first connection point C of the data bus 26 (the data bus area 47a in FIG. 3A). ). That is, the data input unit of the input / output unit side bus interface unit 24 in FIG. 3A is the write clock synchronization circuit 68 and the write data decode circuit 69, and the data input unit of the external input / output buffer 23 is the input first stage circuit. 66 and “delay adjustment + data latch circuit” 67.

  FIG. 5B shows the arrangement of the data input unit of the data input / output unit 28 shown as a comparative example in FIG. The circuit function itself is the same as that of the data input unit according to the first embodiment shown in FIG. 5A, but the arrangement is different. That is, the input first stage circuit 66, the “delay adjustment + data latch circuit” 67, the write clock synchronization circuit 68, and the write data decode circuit 69 are all in the vicinity of the external data input / output terminal (DQ-PAD) 22 (FIG. 3B). ) In the data input / output unit arrangement area 152).

  When the arrangement of the data input unit in the first embodiment shown in FIG. 5A is compared with the comparative example shown in FIG. 5B, the write clock synchronization circuit 68 and the write data decode circuit 69 are connected to the first data bus. By arranging it in the vicinity of the connection point C, the wiring length of the second data bus (branch line), which is a common data bus, is shortened, the difference between the near end and the near end is eliminated, and the wiring length of the entire data bus is shortened, so that high-speed writing is performed. Data transmission can be enabled.

  Next, the relationship between the read / write operation of the DRAM of the semiconductor device 1 and the like, the delay of the data bus 26, and the far / near end difference will be described with reference to FIG. In the DDR SDRAM, a command is given in synchronization with an externally applied clock signal, and read / write data is input / output in synchronization with the clock signal.

  FIG. 6A is a waveform diagram of the read operation of the DDR SDRAM. In synchronization with the clock signal, an ACT command is given at timing t1, and a bank is selected. Thereafter, a Read command is given at timing t2, and read data is output in synchronization with the clock signal at timing t3 after a predetermined Read_Latency. Read_Latency is affected not only by the read operation time of the memory array but also by the transfer speed of the data bus 26.

  Similarly, FIG. 6B is a waveform diagram of the write operation of the DDR SDRAM. In synchronization with the clock signal, an ACT command is given at timing t4 to select a bank. Thereafter, a write command is given at timing t5, and write data is input in synchronization with the clock signal at timing t6 after a predetermined write_latency. Write_Latency is affected by the transfer rate of the data bus 26.

  FIG. 6C shows a waveform diagram in the case where the arrangement and wiring with the difference between the near and far ends is performed on the data bus 26 as in the comparative example shown in FIG. The waveform in FIG. 6C is a waveform on the data bus data receiving side of the array side bus interface unit 25 during data writing and the data input / output unit 28 during data reading. When the wiring length of the data bus 26 has a difference between long and short (far and near), the rising and falling of data are delayed at the farthest end compared to the nearest end as shown in FIG. As shown in FIG. 6D, when the clock speed is further increased, when there is a far-end difference in the wiring of the data bus 26 as in the comparative example, the rise and fall of the data are caused at the farthest end. Due to the delay, the data becomes unstable.

  On the other hand, as shown in FIG. 3A, according to the first embodiment, the wiring length of the data bus is made equal, thereby eliminating the difference between the rising and falling waveforms at the nearest end and the farthest end. Is possible. Therefore, faster data transfer is possible.

  Next, control signals for controlling the data input / output unit 28 will be described. FIG. 7A is a diagram showing a schematic wiring of the data input / output unit control signal 71 in the entire chip. The data input / output unit control signal 71 is transmitted from the address control circuit area 41 between the memory array area 42-1 in which the banks 0 and 2 are arranged and the memory array area 42-2 in which the banks 1 and 3 are arranged. It is wired to the data input / output unit arranged in the data input / output area 43.

  FIG. 7B shows the wiring of the data input / output unit control signal 71 in the data input / output area 43 according to the comparative example described with reference to FIG. In the comparative example of FIG. 7B, the data input / output units 28 are arranged in the vicinity of the corresponding external data input / output terminals (DQ-PAD) 22. If the external data input / output terminals (DQ-PAD) 22 are spread over one side of the semiconductor chip and are arranged apart from each other, the data input / output units 28 are also arranged correspondingly away from each other. Therefore, the wiring length L1 of the data input / output unit control signal 71 is also increased, the wiring load (time constant) of the control signal is increased, the control signal also has a near-end difference, and there is a timing difference between the data input / output units. And high-speed data transfer on the data bus 26 is hindered. Further, the power load increases as the wiring load (time constant) of the control signal increases.

  On the other hand, FIG. 7C shows the wiring of the data input / output unit control signal 71 in the data input / output area 43 according to the first embodiment. As described with reference to FIG. 3A, in the first embodiment, in the circuit of the data input / output unit 28, the input / output unit side bus interface unit 24 is connected to the first data bus (main line) 26-a. Is provided in the vicinity of the first connection point C of the second data bus (branch line) 26-b to shorten the wiring length of the second data bus (branch line) 26-b. The first connection point C is a first data bus (main line) 26 between the array side bus interface unit 25 connected to the banks 0 and 2 and the array side bus interface unit 25 connected to the banks 1 and 3. Since the wiring lengths of −a are equal, the position of the first connection point C in the X-axis direction is relatively closer to the center. Therefore, the input / output unit side bus interface unit 24 arranged in the vicinity of the connection point C is also arranged in a relatively central portion, and the data input / output unit connected to the input / output unit side bus interface unit 24 is arranged. The wiring length L2 of the control signal 71 can be made shorter than the wiring length L1 of the comparative example shown in FIG.

  Therefore, since the wiring load (time constant) of the data input / output unit control signal 71 can be reduced, the data bus can be speeded up and the power consumption can be reduced. In addition, the buffer size for outputting the data input / output unit control signal 71 can be reduced, so that the base area in the layout of the semiconductor chip can be reduced and the power consumption can be reduced. Furthermore, not only the wiring length of the data input / output unit control signal 71 but also the wiring width can be reduced, and the wiring area in the layout can be reduced.

  FIG. 8 is a diagram illustrating the difference in the waveform of the control signal between the comparative example and the first embodiment. FIG. 8A is a schematic wiring diagram of a control signal according to the comparative example, and FIG. 8B is a waveform diagram of the control signal according to the comparative example. As shown in FIG. 8A, in the comparative example, the data input / output unit 28-D arranged closest to the buffer 72-1 of the data input / output unit control signal 71 and the data input / output unit arranged farthest away. There is a large difference in wiring length with 28-A. Therefore, as shown in FIG. 8B, a large variation occurs between the waveform D of the data input / output unit 28-D and the waveform A of the data input / output unit 28-A with respect to the ideal waveform immediately after the output of the buffer 72-1. .

  On the other hand, FIG. 8C is a schematic wiring diagram of a control signal according to the first embodiment, and FIG. 8D is a waveform diagram of the control signal. According to the first embodiment, among the data input / output units 28, the input / output unit side bus interface units 24 for interfacing with the data bus can be arranged relatively collectively, so that the data input / output unit control signal 71 is farthest away. The difference in wiring length between the end and the nearest end is relatively small. Therefore, as shown in FIG. 8D, the variation in the waveform of the control signal in each input / output unit side bus interface unit 24 is reduced.

  FIG. 8E is a schematic wiring diagram of a control signal according to another comparative example, and FIG. 8F is a waveform diagram of the control signal. In another comparative example, as shown in FIG. 8 (e), a buffer 72-2 is further provided in the vicinity of the data input / output unit 28, and a control signal is wired in a tournament type to be input to each input / output unit 28. The variation of the data input / output unit control signal 71 is reduced. As shown in FIG. 8 (f), the variation in the waveform of the control signal is reduced, but an area for arranging the buffer 72-2 is required, and the wiring area is increased by wiring in the tournament type.

  That is, in the first embodiment shown in FIG. 8C, the control signal variation can be reduced as compared with the comparative examples shown in FIG. 8A and FIG. The buffer size for outputting the control signal 71 can be reduced, so that the base region in the layout of the semiconductor chip can be reduced and the power consumption can be reduced. Further, the wiring length and wiring width of the control signal can be reduced, and the wiring area in the layout can be reduced.

  FIG. 9 is a graph showing the distribution of current consumption (IDD4W) during burst write in DDR3_SDRAM. Current specifications in DDR3_SDRAM include IDD0 (active precharge current), IDD1 (active read precharge current), IDD2P (precharge power-down current), IDD2Q (precharge quiescent standby current), IDD2N (precharge standby current), IDD3P (active power down current), IDD4W (burst write current), IDD4R (burst read current), IDD5B (burst refresh current), IDD6 (self refresh current), IDD6ET (self refresh current in the extended temperature range), IDD7 ( Bank interleave lead current) is defined. Here, as a typical current value, the distribution of current consumption (IDD4W) during burst write is shown as described above.

  As shown in FIG. 9, out of the current consumption of the entire chip, the current consumption in the data input / output area is 57%, the current consumption in the amplifier area is 20%, the current consumption in the address area is 15%, and the current consumption in the array area Is 7% and other current consumption is 1%. That is, the current consumption in the data input / output area consumes nearly 60% of the current, and a reduction in the current consumption of the control signal for controlling the data bus 26 and the data input / output unit is required. The effect of reducing the current consumption by shortening the data bus and making the characteristics uniform according to the embodiment is also great.

  The arrangement example of the data input / output unit in the first embodiment has been described with reference to FIGS. 4 and 5, but a modified example of the arrangement of the data input / output unit will be described with reference to FIG. 10. FIG. 10A is a diagram illustrating an arrangement of data output units modified from the first embodiment, and FIG. 10B is a diagram illustrating an arrangement of data input units modified from the first embodiment. is there.

  A modified example of the arrangement of the data output unit will be described with reference to FIG. In FIG. 4A, a “read data selection + data latch circuit” 61 is arranged near the first connection point C of the data bus 26, a read clock synchronization circuit 62, and a “slew rate adjustment + driver strength selection circuit” 63. The output driver 64 is disposed in the vicinity of the external data input / output terminal (DQ-PAD) 22. On the other hand, in the modification shown in FIG. 10A, the “read data selection + data latch circuit” 61, the read clock synchronization circuit 62, and the “slew rate adjustment + driver strength selection circuit” 63 are connected to the first connection point C. The output driver 64 is arranged near the external data input / output terminal (DQ-PAD) 22. The output driver and the output protection circuit are arranged in the vicinity of the pad, but the others are arranged in the vicinity of the connection point C. In other words, where to divide the output circuit can be freely selected depending on layout convenience and circuit characteristics.

  A modified example of the arrangement of the data input unit will be described with reference to FIG. In FIG. 5A, the input first stage circuit 66 and the “delay adjustment + data latch circuit” 67 are arranged in the vicinity of the external data input / output terminal (DQ-PAD) 22, and the write clock synchronization circuit 68 and the write data decode circuit 69 are arranged. Is arranged in the vicinity of the first connection point C of the data bus (data bus area 47a in FIG. 3A). On the other hand, in the modification shown in FIG. 10B, the first connection is not limited to the write clock synchronization circuit 68 and the write data decoding circuit 69, but the input first stage circuit 66 and the “delay adjustment + data latch circuit” 67 are also connected in the first way. It is arranged near the vicinity of the point C.

  5A, the wiring length (wiring load) from the pad to the input first stage circuit 66 can be made uniform for all the pads. On the other hand, in the arrangement according to the modification of FIG. 10B, the wiring length (wiring load) from the pad to the input first stage circuit 66 varies from pad to pad. However, the wiring length reduction effect can be expected for the reference signal REF, and the wiring length from the “delay adjustment + data latch circuit” 67 to the write clock synchronization circuit 68 can be shortened, so that the current consumption reduction effect can be expected.

  10B, the wiring length from the pad to the input first stage circuit 66 is long instead of the wiring length from the “delay adjustment + data latch circuit” 67 to the write clock synchronization circuit 68 being short. Become. However, since the wiring from the “delay adjustment + data latch circuit” 67 to the write clock synchronization circuit 68 is driven by a driver by an internal power supply, it is included in the current consumption of the semiconductor chip, but the wiring from the pad to the input first stage circuit 66 is Since it is a part driven by an external power supply, it is not included in the current consumption in the semiconductor chip. Therefore, even if the wiring of this part becomes long, the current consumption of the semiconductor chip does not increase, and the current consumption of the semiconductor chip can be reduced as a whole.

  Next, a modified example of the arrangement of the data input / output areas will be described with reference to FIGS. 11 (a) and 11 (b) are specifications of 4-bit parallel input / output of bit 0 to bit 3. However, since the bit configuration of the arranged memory array is different between FIGS. 11A and 11B, the arrangement of the array-side bus interface unit 25 is different.

  In FIG. 11A, the array-side bus interface units 25-1 and 25-2 are connected to bit 0 and bit 1 of the corresponding memory array, respectively. On the other hand, the array-side bus interface units 25-3 and 25-4 are connected to bit 2 and bit 3 of the corresponding memory array, respectively. The input / output unit side bus interface unit 24-1 is provided corresponding to the bit 0 and bit 1 of the external data input / output terminal, and performs input / output with respect to the bit 0 and bit 1 data buses. The input / output unit side bus interface unit 24-2 is provided corresponding to the bit 2 and bit 3 of the external data input / output terminal, and performs input / output to the bit 2 and bit 3 data buses.

  Bit 0 and bit 1 of the input / output unit side bus interface unit 24-1 are connected to the bit 0 and bit 1 of the array side bus interface unit 25-1 and 25-2 via a data bus, respectively. Looking at the arrangement in the X-axis direction, the input / output unit side bus interface unit 24-1 that performs input / output for bit 0 and bit 1 has the same data bus wiring length for bit 0 and bit 1, respectively. Arranged between the array-side bus interface units 25-1 and 25-2.

  On the other hand, bit 2 and bit 3 of the input / output unit side bus interface unit 24-2 are connected to bit 2 and bit 3 of the array side bus interface units 25-3 and 25-4, respectively, via a data bus. Looking at the arrangement in the X-axis direction, the input / output unit side bus interface unit 24-2 that inputs / outputs the bit 2 and the bit 3 is configured so that the data bus wiring lengths of the bit 2 and the bit 3 are equal to each other. Arranged between the array-side bus interface units 25-3 and 25-4.

  In FIG. 11B, the array side bus interface unit 25-1 is connected to bit 0 and bit 1 of the corresponding memory array, and the array side bus interface unit 25-2 is bit 2 and bit 3 of the corresponding memory array. And connected to. Similarly, the array side bus interface unit 25-3 is connected to bits 0 and 1 of the corresponding memory array, and the array side bus interface unit 25-4 is connected to bits 2 and 3 of the corresponding memory array. ing. The input / output unit side bus interface unit 24 is provided corresponding to 4 bits of bit 0 to bit 3 of the external data input / output terminal, and performs input / output to / from the data bus for 4 bits of bit 0 to bit 3.

  Bit 0 of input / output unit side bus interface unit 24 is arranged at a position in the X-axis direction such that the wiring length of the data bus is equal to bit 0 of each of array side bus interface units 25-1 and 25-3. And connected via a data bus. Similarly, bit 1 of the input / output unit side bus interface unit 24 is arranged in the X-axis direction so that the data bus wiring length is equal to the bit 1 of each of the array side bus interface units 25-1 and 25-3. Arranged at a position and connected via a data bus.

  Similarly, the bit 2 of the input / output unit side bus interface unit 24 is arranged in the X-axis direction so that the data bus wiring length is equal to the bit 2 of each of the array side bus interface units 25-2 and 25-4. Arranged at a position and connected via a data bus. Similarly to the other bits of bit 3 of the input / output unit side bus interface unit 24, the wiring lengths of the data buses are equal to each other for bit 3 of the array side bus interface units 25-2 and 25-4. Are arranged at positions in the X-axis direction and connected via a data bus.

  12A and 12B, the array-side bus interface units 25-1 to 25-4 are respectively connected to bit 0 and bit 1 of the corresponding memory array. The input / output unit side bus interface unit 24 is provided corresponding to the bit 0 and bit 1 of the external data input / output terminal, and performs input / output with respect to the bit 0 and bit 1 data buses. Accordingly, bit 0 of the array side bus interface units 25-1 to 25-4 is connected to bit 0 of the input / output unit side bus interface unit 24 via the data bus, respectively, and the array side bus interface units 25-1 to 25- Bit 1 of 4 is connected to bit 1 of the input / output unit side bus interface unit 24 via a data bus.

  In FIG. 12A, the data buses are wired so that the bit lengths of the data buses from the array side bus interface units 25-1 to 25-4 are equal for bit 0 and bit 1, respectively. That is, the array side bus interface units 25-1 and 25-2 are connected to the common data bus wiring at a position where the data bus wiring lengths from the array side bus interface units 25-1 and 25-2 are equal. Similarly, the array side bus interface units 25-3 and 25-4 are connected to the common data bus wiring at a position where the wiring lengths of the data buses from the array side bus interface units 25-3 and 25-4 are equal. . Further, the common data buses are connected to the input / output unit side bus interface unit 24 at a position where they have the same wiring length.

  On the other hand, in FIG. 12B, the bit lengths of the data buses from the array side bus interface units 25-1 and 25-4 located at both ends of the data bus in the X-axis direction are equal for bit 0 and bit 1. To the input / output unit side bus interface unit 24. In FIG. 12B, the data bus from the array side bus interface units 25-2 and 25-3 located between the array side bus interface units 25-1 and 25-4 to the input / output unit side bus interface unit 24. Is shorter than the data bus wiring length from the array side bus interface units 25-1 and 25-4. However, by setting the connection to the input / output unit side bus interface unit 24 at positions where the wiring lengths from the array side bus interface units 25-1 and 25-4 located at both ends in the X-axis direction are equal to each other, the data bus The variation due to the difference between the far and near ends can be reduced. In addition, the wiring area of the data bus can be suppressed smaller in FIG. 12B than in FIG. 12A. Further, if necessary, the data bus output length of the array-side bus interface units 25-2 and 25-3, in which the data bus wiring length is shortened, can be reduced, or a delay can be added to the input buffer. It is also possible to align the bus delay time.

  As described above, according to the present invention, high-speed data bus transmission is ensured, and the bank configuration of the memory array, the number of bits, the number of parallel input / output bits required as a product, the pad arrangement, etc. In addition, placement and routing can be freely performed. In addition, current consumption of the data bus can be suppressed.

  In the embodiment, as a preferred application example of the present invention, for a data bus that transfers data between the bus interface unit and the input / output unit, the bus interface unit is connected to a memory, and the data input / output unit is connected to an external data input. Although the data bus connected to the output terminal and used for transferring read / write data between the memory and the external data input / output terminal has been described, the present invention is such that the data input / output unit is connected to other than the external data input / output terminal. It can also be applied to a semiconductor device in which the bus interface unit is connected to other than the memory.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. is there. That is, the present invention naturally includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

1: Semiconductor device 10: Memory array 11: Row decoder (X decoder)
12: Sense amplifier 13: Column selector 14: Command decoder 15: Control logic 16: Column address buffer / burst counter 17: Mode register 18: Row address buffer 19: Refresh counter circuit 20: Clock generator 21: DLL
22: External data input / output terminal 23: External input / output buffer 24: Input / output unit side bus interface unit 25: Array side bus interface unit (array interface unit)
26: Data bus 27, 29, 35: Wiring 28: Data input / output unit 31: Read / write amplifier 41: Address control circuit area 42: Memory array area 43: Data input / output area 44: Y decoder (column decoder)
45: Memory cell array 46: Input / output wiring (bit line)
47, 47a, 147: Data bus area 51: Array interface area 52, 152: Data input / output unit arrangement area 53: Pad area 61: Read data selection + data latch circuit 62: Read clock synchronization circuit 63: Slew rate adjustment + driver Strength selection circuit 64: Output driver 66: Input first stage circuit 67: Delay adjustment + data latch circuit 68: Write clock synchronization circuit 69: Write data decode circuit 71: Data input / output unit control signal 72: Buffer 75: Power supply terminal (power supply pad) )
81, 82: Pad 83: Control wiring area 85: Memory cell L1: Control signal wiring length in the comparative example L2: Control signal wiring length in the first embodiment SWD: Sub word driver SWC: Control circuit DQ-PAD: External Data input / output terminal VDDQ-PAD: VDD power supply terminal for I / O buffer VSSQ-PAD: VSS power supply terminal for I / O buffer A, B, C: (First) connection point D: Connection point

Claims (8)

A data bus,
A data input / output unit connected to the data bus and performing input / output of data transmitted through the data bus;
A plurality of bus interface units, each connected to the data bus, for inputting / outputting data to / from the data input / output unit via the data bus;
With
2. A semiconductor device according to claim 1, wherein wiring lengths of the data buses from the plurality of bus interface units to the data input / output unit are equal to each other. The data bus is connected to the first data bus connected to the first and second bus interface units, to the first data bus at a first connection point, and to the data input / output unit. A second data bus,
The wiring length of the first data bus from the first bus interface unit to the first connection point, and the first data bus from the second bus interface unit to the first connection point. The semiconductor device according to claim 1, wherein the first connection point is provided so that a wiring length is equal to each other. A first data bus;
A second data bus connected to the first data bus by a first connection point;
A data input / output unit connected to the second data bus for performing input / output of data transmitted through the second data bus;
Three or more bus interface units, each connected to the first data bus, for inputting / outputting data to / from the data input / output unit via the first and second data buses;
With
Of the three or more bus interface units connected to the first data bus, the first connection point has the same wiring length from the bus interface unit connected to both ends of the first data bus. A semiconductor device characterized by being provided at a position. A plurality of data input / output units;
A plurality of first and second bus interface units respectively provided corresponding to the plurality of data input / output units;
A plurality of data buses connecting the plurality of data input / output units and the plurality of first and second bus interface units in parallel;
With
A first data bus connecting the plurality of first bus interface units and the plurality of second bus interface units;
A second data bus connecting the first data bus and the plurality of data input / output units;
With
Each bit of the data bus has the second data at a position where the wiring length from the first bus interface unit and the wiring length from the second bus interface unit are equal to each other in the first data bus. A semiconductor device connected to a corresponding bit of a bus. A plurality of external data input / output terminals respectively connected to a plurality of data input / output units;
Further comprising
Each of the plurality of data input / output units includes an input / output unit side bus interface unit that interfaces the data bus, and an input / output buffer that inputs / outputs data to / from the external data input / output terminal. ,
The plurality of input / output unit side bus interface units are arranged such that a distance between the plurality of input / output unit side bus interface units is smaller than a distance between the plurality of external data input / output terminals. The semiconductor device according to claim 4. The first data bus is wired in a first direction;
The plurality of bus interface units are disposed on one side of the first data bus along the first data bus;
The plurality of data input / output units are provided opposite to the plurality of bus interface units across the first data bus, and the second data bus is in a second direction different from the first direction. 6. The semiconductor device according to claim 4, wherein the first data bus and the plurality of bus interface units are wired and connected to each other. Comprising a plurality of memory cell arrays arranged side by side in a first direction;
7. The semiconductor device according to claim 6, wherein the plurality of memory cell arrays are connected to the data bus via the plurality of bus interface units.   8. The semiconductor device according to claim 1, wherein the data bus, the data input / output unit, and the plurality of bus interface units are formed on a surface of the same semiconductor substrate. .

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