JP2013218582A - Signal processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing apparatus in which when data or a control command is communicated among a plurality of processing devices, increase of a circuit scale is prevented, and a degree of freedom in design is secured.SOLUTION: A signal processing apparatus includes: a first device connected to a parallel bus; a second device connected to the parallel bus; and a third device connected via a serial bus to the second device; wherein the fist device transmits a first command to be sent to the second device and a second command to be sent to the third device via the parallel bus to the second device; the second device executes processing according to the first command received via the parallel bus from the first device; and when the second command is received via the parallel bus from the first device, the second command is transmitted via the serial bus to the third device.

Description

  The present invention relates to a signal processing apparatus, and more particularly to communication of a control signal between a plurality of devices.

  A parallel bus interface or a serial bus interface is used when image data and control commands are communicated between processing circuits such as a plurality of LSIs (see, for example, Patent Document 1). For example, a master device controls a plurality of slave devices via a parallel bus interface.

JP 2006-133924 A

  However, when the distance between the master device and the slave device is long, there is a problem that if the connection is made by the parallel bus, the board design becomes difficult due to the increase of the signal lines, and the skew management between the signal lines becomes difficult.

  Thus, it is conceivable to perform communication using a serial bus between devices that are far away, but in this case, the master device needs to include both a parallel bus interface and a serial bus interface. For this reason, there is a problem that the circuit scale of the master device increases and the degree of freedom in design decreases.

  An object of the present invention is to prevent an increase in circuit scale and secure a degree of design freedom when communicating data and control commands between a plurality of processing devices in view of the above-described problems.

  In the present invention, a first device connected to the parallel bus, a second device connected to the parallel bus, and a third device connected to the second device via the previous serial bus, The first device transmits a first command to the second device and a second command to the third device to the second device via the parallel bus. The second device performs processing according to the first command received from the first device via the parallel bus, and also performs the processing from the first device via the parallel bus. When the second command is received, the second command is transmitted to the third device via the serial bus.

  According to the present invention, when data and control commands are communicated between a plurality of processing devices, an increase in circuit scale can be prevented and design freedom can be ensured.

It is a block diagram which shows the structure of the signal processing apparatus which concerns on embodiment of this invention. It is a figure which shows the address space in a slave device. It is a figure which shows the format of the data transmitted by a serial bus. It is a timing chart at the time of read access command transmission. It is a figure which shows the format of the data transmitted by a serial bus. It is a figure which shows the structure of the imaging device which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of a signal processing device 100 according to an embodiment of the present invention.

  In FIG. 1, a master device (first device) 101 controls a plurality of slave devices 102, 103, and 104. The master device 101 and each of the slave devices 102, 103, and 104 perform determined processing. For example, each of the master device 101 and the slave devices 102-104 is a single LSI (integrated circuit: IC), and performs predetermined processing on information signals such as image signals and audio signals. The master device 101 is connected to the parallel bus 105 and has a parallel IF 101 a that communicates with each slave device via the parallel bus 105. The master device 101 also includes a CPU 101b for controlling by issuing a control command to be transmitted to each slave device. The parallel IF 101a includes a chip select signal line for selecting a slave device to be controlled, a 23-bit address signal line, a 16-bit data (control command) line, and a ready signal line.

  The slave device 102 has a parallel IF 102 a that is connected to the parallel bus 105 and communicates with the master device 101 via the parallel bus 105. The parallel IF 102a has a chip select signal line, a 23-bit address signal line, and a 16-bit data line.

  The slave device 103 (second device) has a parallel IF 103 a that is connected to the parallel bus 105 and communicates with the master device 101 via the parallel bus 105. The parallel IF 102a includes a chip select signal line, a 23-bit address signal line, a 16-bit data line, and a ready signal line. The slave device 103 further includes a serial IF 103 b that communicates with the slave device 104 via the serial bus 106. The serial IF 103b has a transmission signal line (MOSI) and a reception signal line (MISO).

  The slave device 104 (third device) includes a serial IF 104 a that performs communication with the slave device 103 via the serial bus 106. The serial IF 104a has a transmission signal line (MOSI) and a reception signal line (MISO).

  The master device 101 transmits a control command (first command) to the slave device 102 and the slave device 103 via the parallel bus 105. The master device 101 transmits a control command (second command) addressed to the slave device 104 via the parallel bus 105 and the slave device 103.

  The parallel IF 103a of the slave device 103 detects the control command received from the master device 101. Then, when the received control command is a control command to the slave device 104, the parallel IF 103a transmits the received control command to the slave device 104 via the serial bus 106 by the serial IF 103b.

  FIG. 2 is a diagram illustrating a configuration of a storage area in a memory (register) for storing a control command received by the slave device 103 from the master device 101. Of the 23-bit address space, an address space in the range of 0x0000000 to 0x7FFFFF is allocated as a space for receiving a control command for the slave device 103. An address space in the range of 0x800000 to 0xFFFFFF is allocated as a space for receiving a control command for the slave device 104.

  When transmitting a control command to the slave device 103 or 104, the master device 101 specifies one of the address spaces in FIG. 2 and transmits the control command. The parallel IF 103a of the slave device 103 stores the control command at the received address in the storage area of FIG. The parallel IF 103a instructs the serial IF 103b to transmit the received control command when the received address (address signal value) is the address space for the slave device 104. Then, the serial IF 103 b transmits the received control command to the slave device 104 via the serial bus 106. If the received address is the address space for the slave device 103, the slave device 104 executes processing according to the received command.

  FIG. 3 is a diagram illustrating an example of a transmission format for transmitting a control command to the slave device 104 via the serial bus 106.

  When the master device 101 does not transmit a control command for the slave device 104 to the slave device 103, the reception signal (MOSI) of the serial bus is fixed to “0”. When the master device 101 transmits a control command for the slave device 104 to the slave device 103, the slave device 103 converts the received control command into the following format and sends it to the slave device 104 via the serial bus 106. To transmit.

  First, 8-bit “1” is transmitted to the reception signal of the serial bus. Thereafter, 7-bit data from the 15th bit to the 9th bit of data (control command) is transmitted following “0” of 1 bit. Thereafter, 1-bit “0” and 7-bit control commands are continuously transmitted, and when transmission of all 22-bit addresses and 16-bit data is completed, the output is fixed to “0” again.

  When receiving 8 bits of “1”, the slave device 104 detects that transmission of the control command has started. Then, the slave device 104 extracts valid bits from the combination of “0” and 7-bit received data below, reconstructs the control command, and performs processing according to the designated control command. In the data format, “1” that is 8 bits continuous does not occur except for the control command transmission start timing, so that the slave device 104 can reliably receive the control command.

  Next, processing at the time of read access to the slave device will be described. FIG. 4 is a timing chart of each signal line at the time of read access. The read command is a command for requesting a response from the slave device.

  When the master device 101 performs read access to the slave device 104, the address 0x800000 of the slave device 103 is specified, and a chip select signal, a read signal, and an address signal are transmitted to the slave device 103.

  The slave device 103 transmits a read command to the slave device 104 via the serial bus 106. In the case of read access, the slave device 103 acquires a response from the slave device 104 and then transmits a response from the slave device 104 to the master device 101.

  At this time, the time until the response from the slave device 104 is transmitted varies depending on the performance and status of the slave device 104. Therefore, after the master device 101 issues a read command and arbitrates the right to use the bus according to a predetermined waiting time, the master device 101 can receive the response from the slave device 104 before the master device 101 obtains the slave device 102 or the slave device. 103 may be accessed. As a result, the desired data cannot be obtained, which may cause a malfunction.

  Therefore, when the slave device 103 receives a read command from the master device 101 to the slave device 104, the slave device 103 transmits a ready signal to the master device 101. The master device 101 extends the state of waiting for a response from the slave device 104 to the read command during the period of receiving the ready signal. By such control, the slave device 103 occupies the right to use the parallel bus until a response from the slave device 104 is received.

  After transmitting the ready signal, the slave device 103 converts the format of the control command acquired via the parallel bus 105 and transmits it to the slave device 104 via the transmission signal line of the serial bus. The slave device 104 generates response data according to the acquired command, and transmits the response data to the slave device 103 through the reception signal line of the serial bus 106.

  When the slave device 103 receives a response from the slave device 104, the slave device 103 transmits the response to the master device 101 via the data line of the parallel bus 105.

  FIG. 5 is a diagram illustrating an example of a transmission format for transmitting a read access command to the slave device 104 via the serial bus 106.

  When the master device 101 does not output a read access to the slave device 104, the transmission signal of the serial bus is fixed to “0”. When the master device 101 transmits a read access command to the slave device 104 to the slave device 103, the slave device 103 converts the received control command into the following format, and transmits the slave device 104 via the serial bus 106. Transmit to.

  First, 8-bit “1” is transmitted to the transmission signal of the serial bus 106. Thereafter, 7-bit data from the 15th bit to the 9th bit of the data is transmitted following “0” of 1 bit. Thereafter, 1-bit “0” and 7-bit control commands are continuously transmitted. When transmission of all 16-bit data is completed, the output is fixed to “0” again.

  When the slave device 103 receives 8-bit “1”, the slave device 103 detects that transmission of the control command has started. Then, the slave device 104 extracts a valid bit from the combination of “0” and 7-bit received data, and reconstructs a control command, here, a read command. Next, the slave device 104 generates a response to the read command, and transmits the response to the slave device 103 using the received signal of the serial bus 106. When the slave device 103 receives the response from the slave device 104, the slave device 103 outputs response data to the data signal of the parallel bus 105 and cancels the ready signal. The master device 101 monitors the release of the ready signal. When the ready signal is released, the master device 101 takes in the data signal to acquire response data, and releases the address signal, the read signal, and the chip select signal.

  A configuration when the signal processing apparatus 100 of FIG. 1 is applied to an imaging apparatus will be described with reference to FIG. In FIG. 6, an imaging unit 601 captures an image of a subject and outputs a moving image signal. The camera signal processing unit 602 performs processing such as image quality correction or screen size change on the moving image signal output from the imaging unit 601, and outputs the processed video signal to the correction unit 603 and the output processing unit 606. The correction unit 603 corrects the deterioration due to the flaw of the image sensor in the imaging unit 601 with respect to the moving image signal from the camera signal processing unit 602. The image processing unit 604 further performs necessary camera signal processing on the moving image signal from the correction unit 603 and outputs the processed signal to the recording processing unit 605. The recording processing unit 605 performs processing necessary for recording, such as compression encoding processing, on the moving image signal from the image processing unit 604, and records it on a recording medium. The output processing unit 606 performs processing necessary for outputting the moving image signal from the camera signal processing unit 402 to the outside, and outputs the processed signal to the outside of the apparatus.

  In FIG. 6, an image processing unit 604 corresponds to the master device 101 in FIG. The correction unit 603 and the camera signal processing unit 602 correspond to the slave devices 102 and 103 in FIG. The output processing unit 606 corresponds to the slave device 104 in FIG. In this embodiment, since a control command is transmitted between the camera signal processing unit 602 and the output processing unit 606 via the serial bus 106, the LSI constituting the output processing unit 606 is replaced with the camera signal processing unit 602. It can be arranged at a position relatively distant from the LSI to be configured. For example, the output processing unit 606 is preferably arranged in the vicinity of an external connection terminal. However, in this embodiment, the degree of freedom in design is improved in such a case.

Claims (7)

A first device connected to the parallel bus;
A second device connected to the parallel bus;
A third device connected to the second device via a serial bus,
The first device transmits a first command to the second device and a second command to the third device to the second device via the parallel bus;
The second device performs processing according to the first command received from the first device via the parallel bus, and also performs the second command from the first device via the parallel bus. When receiving a command, the signal processing apparatus transmits the second command to the third device via the serial bus.   The first device transmits a command together with an address signal, and the second device sends the first command and the second command based on the value of the address signal received from the first device. The signal processing apparatus according to claim 1, wherein the signal processing apparatus detects the signal processing apparatus.   The second device converts the second command received from the first device via the parallel bus into a format for transmission via the serial bus and transmits the second command to the third device. The signal processing device according to claim 1, wherein   When the second command received from the first device via the parallel bus is a command requesting a response from the third device, the second device receives the second command. 4. The signal processing apparatus according to claim 1, wherein the device occupies the right to use the parallel bus until receiving a response from the third device. 5.   5. The device according to claim 4, wherein the second device transmits the response received from the third device via the serial bus to the first device via the parallel bus. Signal processing device.   The signal processing apparatus according to claim 1, wherein the first device includes a CPU that generates the control command.   The signal processing apparatus according to claim 1, wherein each of the first device, the second device, and the third device is configured as a single LSI. .

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