JP2013214343A - Semiconductor memory device and test method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a test time.SOLUTION: A semiconductor memory device includes: memory cells provided with word lines and bit lines corresponding to a plurality of ports; a word driver circuit that activates the word lines by a timing signal corresponding to each of the plurality of ports; a bit line level control circuit that generates a control signal which controls the potential of the bit line corresponding to each of the plurality of ports on the basis of a test signal; and a column control circuit that controls the bit line potential on the basis of the output of the bit line level control circuit. During testing, one bit line potential of an aggressive port to a test target port is held in a state that is lowered by the amount of a threshold value.

Description

  The present invention relates to a semiconductor memory device and a test method thereof, and more particularly to an SRAM (including a macro) having two or more read / write ports and a test method thereof.

In recent years, in order to perform data processing at high speed, SRAMs (including macros) having a multiport function for transmitting and receiving data within one clock cycle have been adopted.

  On the other hand, because of process miniaturization / low-voltage operation, if data writing to the same address and reading from another port occur simultaneously due to the influence of each transistor variation in the SRAM cell of the SRAM macro, the write data is guaranteed. The malfunction of being unable to do so has become apparent.

  In addition, each port is asynchronously operated, and while accessing a memory cell from one port, the same memory cell may be accessed from another port. Since the skew between clocks affects the power supply voltage margin, a test with a skew between clocks is required to perform an appropriate test with the clock skew during the actual operation of the LSI chip, and a huge amount of test time is required. It is.

  Therefore, a test circuit and a test method for improving the test quality of an SRAM (including a macro) having a multiport and reducing the test time are eagerly desired.

  FIG. 14 is a diagram showing a configuration of a circuit (X address decoder and word driver) for controlling the activation of the word line disclosed in the cited document 1. In FIG. Referring to FIG. 14, the circuit of the cited document 1 includes a clock terminal (A) for inputting a clock signal CLKA, a 2-input NAND circuit 11 having inputs connected to a TEST terminal (TESTB) of a port B, and a 2-input. An inversion buffer 12 that receives the output of the NAND circuit 11 is provided, and the internal clock signal ICLA is output from the inversion buffer 12.

  The operation of this circuit will be described. When the test control signal TESTB for the port B is LOW (the input of the test control signal TESTB is active at LOW in the NAND circuit 11), the NAND circuit 11 receives the clock signal CLKA for the port A. The inverted signal is output, and an internal clock signal (A) ICLA in phase with the clock signal CLKA is output from the inverting buffer 12. When the test control signal TESTB for port B is HIGH, the output of the NAND circuit 11 is fixed HIGH (the clock signal CLKA is masked) regardless of the value of the clock signal CLKA, and the internal clock signal ICLA from the inverting buffer 12 is output. Is fixed LOW.

  The circuit of the cited document 1 includes a clock terminal (B) for inputting the clock signal CLKB, a 2-input NAND circuit 13 whose input is connected to the TEST terminal (TESTA) of the port A, and an inversion receiving the output of the NAND circuit 13. The inversion buffer 14 outputs an internal clock signal ICLB.

  The operation of this circuit will be described. When the test control signal TESTA for port A is LOW (input of the test control signal TESTA is active LOW in the NAND circuit 13), the NAND circuit 13 receives the clock signal CLKB for port B. The inverted signal is output, and the inversion buffer 14 outputs the internal clock signal (B) ICLB in phase with the clock signal CLKB. When the test control signal TESTA for port A is HIGH, the output of the NAND circuit 13 is fixed HIGH (the clock signal CLKB is masked) regardless of the value of the clock signal CLKB, and the internal clock signal ICLB from the inverting buffer 14 is set. Is fixed LOW.

  Further, the circuit of the cited document 1 is a circuit that controls the driving of the word line WLA of the port A, a 2-input NAND circuit 15 that receives XKA and XEA that are the address selection signals (A) of the port A, and a NAND circuit 15 A CMOS transfer gate 17 comprising a PMOS transistor receiving the output at the gate and an NMOS transistor receiving the signal obtained by inverting the output of the NAND circuit 15 at the inverter 16 at the gate, and a drain connected to the output of the CMOS transfer gate 17 and a source connected to the power supply VSS. An NMOS transistor 18 having a gate connected to the output of the NAND circuit 15 is provided.

  Further, the circuit of the cited document 1 includes a test control signal TESTB of port B, a 2-input AND circuit 19 whose input is connected to an output of a CMOS transfer gate 24 described later, an output of the CMOS transfer gate 17 and an AND circuit 19 A two-input NOR circuit 20 that receives the output and an inverting word driver 21 that receives the output of the NOR circuit 20 are provided. Note that XKA and XEA of the address selection signal (A) are address selection signals output by a predecoder (not shown) as a result of decoding the input X address.

  The operation of this circuit will be described. When both XKA and XEA are HIGH, the output of the NAND circuit 15 becomes LOW, the CMOS transfer gate 17 is turned on, and the input internal clock signal ICLA is transmitted and output. When at least one of XKA and XEA is LOW (when the address of port A of the cell is not selected), the output of the NAND circuit 15 is HIGH, the CMOS transfer gate 17 is turned off, the NMOS transistor 18 is turned on, and the CMOS transfer is turned on. The output of the gate 17 is set to the LOW level.

  For example, when the test control signal TESTB of port B is LOW, the output of the AND circuit 19 becomes LOW, and the NOR circuit 20 supplies a signal obtained by inverting ICLA, which is the output of the CMOS transfer gate 17, to the inverting type word driver 21. .

  On the other hand, when the test control signal TESTB of port B is HIGH (ICLA is fixed LOW at this time), the NOR circuit 20 supplies a signal obtained by inverting the output of the AND circuit 19 to the inverting word driver 21. The inverting type word driver 21 receives the LOW pulse (signal having a phase opposite to ICLB) from the NOR circuit 20 and drives the word line WLA.

  Further, the circuit of the cited document 1 is a circuit that controls the driving of the word line WLB of the port B. The 2-input NAND circuit 22 that receives XKB and XEB that are the address selection signals (B) of the port B; A CMOS transfer gate 24 composed of a PMOS transistor receiving the output at the gate and an NMOS transistor receiving the signal obtained by inverting the output of the NAND circuit 22 at the inverter 23 at the gate, and a drain connected to the output of the CMOS transfer gate 24 and a source connected to the power supply VSS. An NMOS transistor 25 having a gate connected to the output of the NAND circuit 22 is provided. Further, the circuit of the cited document 1 receives the test control signal TESTA of port A, the 2-input AND circuit 26 whose input is connected to the output of the CMOS transistor 17, the output of the CMOS transfer gate 24, and the output of the AND circuit 26. A two-input NOR circuit 27 and an inverting type word driver 28 that receives the output of the NOR circuit 27 are provided. Note that XKB and XEB of the address selection signal (B) are address selection signals output by a predecoder (not shown) as a result of decoding the input X address.

The operation of this circuit will be described. When both XKB and XEB are HIGH, the output of the NAND circuit 22 becomes LOW, the CMOS transfer gate 24 is turned on, and the input internal clock signal ICLB is transmitted and output. When at least one of XKB and XEB is LOW (when the address of port B of the cell is not selected), the output of the NAND circuit 22 is HIGH, the CMOS transfer gate 24 is turned off, the NMOS transistor 25 is turned on,
The output of the CMOS transfer gate 24 is set to the LOW level.

  For example, when the test control signal TESTA for port A is LOW, the output of the AND circuit 26 becomes LOW, and the NOR circuit 27 supplies a signal obtained by inverting ICLB, which is the output of the CMOS transfer gate 24, to the inverting driver 28.

  On the other hand, when the test control signal TESTA of port A is HIGH (ICLA is fixed LOW at this time), the NOR circuit 27 supplies a signal obtained by inverting the output of the AND circuit 26 to the inverting word driver 28. The inverting type word driver 28 receives the LOW pulse (signal having a phase opposite to ICLB) from the NOR circuit 27 and drives the word line WLB.

  FIG. 15 is a diagram for explaining the timing operation of the prior art shown in FIG. The operation of the circuit of FIG. 14 will be described below with reference to FIG.

<Independent operation>
When both TESTA and TESTB are LOW (see “independent operation” in FIG. 15), the NAND circuits 11 and 13 output signals obtained by inverting the clock signals CLKA and CLKB, respectively, and the internal clock signals ICLA and ICLB are clocks. It is in phase with the signals CLKA and CLKB. Since TESTB is LOW, the output of the AND circuit 19 is fixed LOW, and when XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of ICLA output from the CMOS transfer gate 17 and The word line (A) WLA is activated in synchronization with the internal clock signal ICLA, and hence the clock signal CLKA. Since TESTA is LOW, the output of the AND circuit 26 is fixed LOW, and when XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of ICLB output from the CMOS transfer gate 24, and the port B The word line (B) WLB is activated in synchronization with the clock ICLB, and hence the clock signal CLKB. That is, the word lines of port A and port B are controlled independently of each other.

<Simultaneous READ: A port test>
When TESTA is HIGH and TESTB is LOW (see “A port test” in FIG. 15), the output of the NAND circuit 13 is HIGH regardless of the value of the clock signal CLKB, and ICLB is fixed LOW. Since the output of the AND circuit 19 is fixed to LOW, when XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of ICLA output from the CMOS transfer gate 17 and the word line (A) WLA of the port A Are activated in synchronism with the clock ICLA and thus with the clock signal CLKA. ICLB is fixed to LOW. When XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of the AND circuit 26. When ICLA is HIGH, the AND circuit 26 is HIGH, and the word driver 28 sets the word line WLB to HIGH. That is, WLB rises simultaneously with WLA, and read data is simultaneously output to the bit line pair DTA / DBA of the A port and the bit line pair DTB / DBB of the B port.

<Simultaneous READ: B port test>
When TESTB is HIGH and TESTA is LOW (see “B port test” in FIG. 15), the output of the NAND circuit 11 is HIGH regardless of the value of the clock signal CLKA, and ICLA is fixed LOW. Since the output of the AND circuit 26 is fixed to LOW, when XKB and XEB are HIGH, the NOR circuit 27 outputs an inverted signal of ICLB output from the CMOS transfer gate 24 and the word line (B) WLB of the port B Are activated in synchronization with the clock ICLB, and hence the clock signal CLKB.

  ICLA is fixed LOW. When XKA and XEA are HIGH, the NOR circuit 20 outputs an inverted signal of the AND circuit 19, and when ICLB is HIGH, the AND circuit 19 becomes HIGH, and the word driver 21 sets the word line WLA to HIGH. That is, WLA rises simultaneously with WLB, and read data is simultaneously output to the bit line pair DTB / DBB of the B port and the bit line pair DTA / DBA of the A port.

  Thus, in the prior art, in the control of the rise of the word line on the same row, the logic of the test control signal of one port and the word line rise signal of the other port is added, When the test control signal is enabled, the word line on the other port side is also driven with exactly the same signal transition timing as the rise of the word line on one port side. The logic of the test control signal of one port and the clock signal of the other port inputted from the outside is taken so as not to disturb the driving of the other word line, and the test control signal of one port is enabled (HIGH) In this case, the internal clock signal of the other port is not output.

JP 2008-282515, FIG. 1, FIG. 2, pages 10-12

  It is known that due to mutual interference between ports in an SRAM having a multi-port, the operation margin of the SRAM macro is deteriorated and becomes defective (hereinafter referred to as a write operation failure mode) particularly during a write operation. This method has a problem that it is difficult to detect the write operation failure mode described above.

  The reason will be described below. For the sake of explanation, the port controlled by the first clock signal CLKA (hereinafter referred to as port A) is the test target port, and the port controlled by the second clock signal CLKB (hereinafter referred to as port B). Is the harm port.

  There are two factors that cause the operation margin to deteriorate during the write operation due to mutual interference. The first is that the bit line capacity is doubled by connecting the bit line of the port under test to the bit line of the port under test by opening the word line of the port under test while the word line of the port under test is open. It is caused by becoming. The second is that the word line of the harm port opens before the test target port, so that one of the bit line pair of the harm port starts to discharge by the memory cell, and the potential of the bit line of the harm port is lowered. is there.

  A mechanism for deteriorating the operation margin during the write operation due to mutual interference will be described with reference to the SRAM cell 200 of FIG. 2 and FIG.

  A state in which the latch nodes CELLT and CELLB of the SRAM cell 200 are HIGH and LOW, respectively, is referred to as HIGH data retention. A state in which the latch node CELLT is LOW and CELLB is HIGH is referred to as LOW data retention. An example will be described in which the high-data holding SRAM cell 200 is written to LOW data. FIG. 5 shows word lines WLA, WLB, bit lines DTA, DBA, DTB, DBB, SRAM cell 200, and latch nodes CELLT, CELLB when port A is a test target.

  FIG. 5A shows a case where the word lines WLA and WLB rise simultaneously, and the word lines WLA and WLB are opened at the same time while the bit line of the B port which is the harming port is in the HIGH level. When the word lines WLA and WLB are opened, the potentials of the bit lines DTA, DBA, DTB, and DBB are precharged to HIGH, and the bit line DTA becomes LOW by writing from the port A and latches via the NMOS transistor 201. Although the operation of rewriting the node CELLT from HIGH to LOW is performed, since the bit line DTB of the harming port is HIGH, the charge of the bit line DTB through the NMOS transistor 203 hinders the movement of lowering the latch node CELLT to LOW.

  Further, when the word line WLB is opened, HIGH data is read, that is, since the latch node CELLB is LOW, the potential of the bit line DBB starts to drop through the NMOS transistor 204. At the same time, since the word line WLA is opened and LOW data is written, the latch nodes CELLT and CELLB become LOW and HIGH, respectively, so that the NMOS transistor 204 is turned OFF, the bit line DBB stops at the potential drop Va, and the bit line DBB Is (VDD−Va). That is, the operation in FIG. 5A can be tested by the A port test in FIG. 10 of the prior art in which the word lines WLA and WLB are simultaneously started up.

  FIG. 5B shows a waveform when the word line WLB rises ahead of the word line WLA and the write fails. The word line WLB rises, and the HIGH data of the SRAM cell 200 appears as a potential drop Vb of the bit line DBB by reading the harming port, and the potential of the bit line DBB drops to (VDD−Vb). The potential of the bit line DBB has a relationship of (VDD−Va)> (VDD−Vb). When the word line WLB is opened before the word line WLA, the potential of the bit line DBB is increased when the word line WLA rises. The strength of inhibiting the operation of the latch node CELLB going HIGH through the NMOS transistor 204 is increased.

  At the time of rising of the word line WLA, the bit line DTB is HIGH, which hinders the operation of rewriting the latch node CELLT from HIGH to LOW. If the margin for the write operation is lost due to the influence of the bit lines DTB and DBB, the latch nodes CELLT and CELLB cannot be inverted, and the write operation fails. In the prior art, the skew between the word lines WLA and WLB cannot be shifted. Therefore, if the SRAM macro operates with the skew during actual operation and the writing fails, the market becomes defective. In order to screen the defect, it is necessary to perform a test in which the skews of the clock signals CLKA and CLKB are swung and the skews of the word lines WLA and WLB are swung several times for each address address in the independent operation of FIG. .

  FIG. 13 is a flowchart for performing the skew swing in a general test when the independent operation of the prior art is used. First, in step S301, arbitrary initial values are written in all the SRAM cells, and in step S302, clock skews of the clocks CLKA / CLKB of both ports are set. Next, in step S303, writing and reading to the same address from both ports (hereinafter referred to as the same address access) are performed at an arbitrary address, and the address is read in step S304. In step S305, it is determined whether or not the writing is normally performed. Since a plurality of tests are required while changing the clock skew, it is determined in step S306 whether the number of tests is a specified number.

  When the number of skew swings reaches the specified number in step S306 (YES in step S306), the address is changed, and steps S302, S303, S304, S305, and S306 are performed again. In step S307, it is determined whether all addresses have been tested. If the test has been completed (YES in step S307), the test ends.

  Here, for example, when the clock skew difference of each port is within a range of 10 ns, and the clock skew swing interval is 0.01 ns, it is necessary to repeat steps S302, S303, S304, and S305 in FIG. The time is very long. As described above, it can be understood that it takes an enormous amount of test time to find a write operation failure mode in the same address access by the conventional technique.

  One embodiment of the present invention is a semiconductor memory device having a plurality of write / read ports, and includes a bit line potential control circuit at the time of testing, a bit line potential at the time of reading, and a bit line potential of the harming port at the time of testing. It has a column control circuit to be controlled, a test signal controlled by BIST, and an SRAM internal signal generated in response to the test signal. When testing for the same address access, the precharge control of the bit line of the harm port is tested. The test operation is performed in a state where the bit line potential of the harm port is lowered to a potential that drops during the read operation, according to the data to be written from the target port.

  As a result, it is possible to perform a test in a state where the disturbing word line is preceded by the same address access without disturbing the clock and the disturbance due to the potential drop of the harming port bit line potential. I can do it.

  According to the semiconductor memory device of one embodiment of the present invention, the test time can be shortened.

It is a block diagram of the 1st Example of this invention. 1 is a configuration diagram according to a first embodiment of the present invention. It is a timing chart concerning the 1st example of the present invention. It is a test mode truth table concerning the 1st example of the present invention. This is an operation waveform when accessing the same address. It is a test flow concerning the 1st example of the present invention. 1 is a configuration diagram of an internal clock output circuit according to a first embodiment of the present invention. It is a block diagram of the 2nd Example of this invention. It is a timing chart which concerns on 2nd Example of this invention. It is a block diagram concerning the 2nd example of the present invention. It is a block diagram concerning the 3rd example of the present invention. It is a block diagram concerning the 4th example of the present invention. It is a timing chart of a prior art. It is a block diagram which concerns on the Example of a prior art. It is a timing chart which concerns on the Example of a prior art.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention. This semiconductor device includes an SRAM (Static Random Access Memory) macro 100 and a BIST 101 (Build In Self Test) that controls the operation of the SRAM during a test.

  The SRAM macro 100 includes an internal clock output circuit 107, a bit line level control circuit 112, a word driver 109, an address decoder 113, a write control circuit 114, a column control circuit 111, and a memory cell array 110.

  The BIST 101 includes clock signals CLKA and CLKB, test signals TESTA, TESTB, TDISTA, TDISTB, TD0, and TD1, an address signal ADDn (n is an arbitrary natural number), and data signals DAi and DBi (i is an arbitrary natural number). Write enable signals WAE and WBE are generated and output to the SRAM macro 100.

  Next, connection of the SRAM macro 100 will be described. First, the internal clock output circuit 107 receives the clock signals CLKA and CLKB and the test signals TESTA and TESTB, and generates internal clock signals ICLB and ICLA synchronized with the clock signals CLKA and CLKB that serve as reference signals for the memory array operation. , Output to the word driver 109, the address decoder 113, and the write control circuit 114.

  The write control circuit 114 receives the internal clock signals ICLB and ICLA, the data signals DAi and DBi, and the write enable signals WAE and WBE, generates the write data signals WDTA, WDBA, WDTB, and WDBB, and outputs them to the column control circuit 111. .

  The address decoder 113 receives the internal clock signals ICLB and ICLA and the address signal ADDn, generates the internal address signals XKA, XKB, XEA, XEB, YSLA, and YSLB, and the internal address signals XKA, XKB, XEA, and XEB are word drivers. The internal address signals YSLA and YSLB are output to the column control circuit 111.

  The bit line level control circuit 112 receives the test signals TDISTA, TDISTB, TD0, and TD1, generates test signals DISTB, DISTA, TDB1, TDB0, TDA1, and TDA0 and outputs them to the column control circuit 111.

  The column control circuit 111 receives test signals DISTA, DISTB, TDB0, TDB1, TDA0, TDA1, write data signals WDTA, WDBA, WDTB, WDBB and internal address signals YSLA, YSLB, and a bit line DTA of the memory cell array 110. , DBA, DTB, DBB.

  The word driver 109 receives internal address signals XKA, XKB, XEA, XEB, internal clock signals ICLA, ICLB, and test signals TESTA, TESTB, generates word signals WLA, WLB, and outputs them to the memory array 110.

  FIG. 2 is a diagram showing a column control circuit 111 and a multi-port SRAM cell 200 which is one SRAM cell circuit in the memory cell array 110. The SRAM cell 200 is configured in a matrix in the memory cell array 110. The column control circuit 111 includes a B port column control circuit 210 and an A port column control circuit 220.

  The SRAM cell 200 is an SRAM cell having two write / read ports. The SRAM cell 200 includes inverters 205 and 206 and NMOS transistors 201, 202, 203, and 204. Inverters 205 and 206 are cell data holding latches. The NMOS transistor 201 inputs the word line WLA to the gate, and connects the positive logic bit line DTA of the port A and the cell data holding latch. The NMOS transistor 202 inputs the word line WLA to the gate, and connects the inverse logic bit line DBA of the port A and the cell data holding latch. The NMOS transistor 203 inputs the word line WLB to the gate, and connects the positive logic bit line DTB of the port B and the cell data holding latch. The NMOS transistor 204 inputs the word line WLB to the gate, and connects the inverse logic bit line DBB of the port B and the cell data holding latch.

  Next, the configuration of the B port column control circuit 210 will be described. The B port column control circuit 210 includes NMOS transistors 213 and 214, PMOS transistors 211 and 212, an OR circuit 215, and a precharge circuit 216. The NMOS transistor 213 connects the write data signal WDTB and the bit line DTB. The NMOS transistor 214 connects the write data signal WDBB and the bit line DBB. In the PMOS transistor 211, the test signal TDA0 output from the bit line level control circuit 112 is input to the gate, and one is connected to the power supply VDD and the other is connected to the bit line DTB. In the PMOS transistor 212, the test signal TDA1 output from the bit line level control circuit 112 is input to the gate, and one is connected to the power supply VDD and the other is connected to the bit line DBB.

  The OR circuit 215 receives the bit line control signal DISTA output from the bit line level control circuit 112 and the internal address signal YPLB output from the address decoder 113, and supplies the precharge signal PCB to the precharge circuit 216 and the NMOS transistor 213, Output to the gate of 214. The precharge circuit 216 is activated when the input precharge signal PCB is LOW and deactivated when HIGH.

  Next, the configuration of the A port column control circuit 220 will be described. The A port column control circuit 220 includes NMOS transistors 223 and 224, PMOS transistors 221 and 222, an OR circuit 225, and a precharge circuit 226. The NMOS transistor 223 connects the write data signal WDTA and the bit line DTA. The NMOS transistor 224 connects the write data signal WDBA and the bit line DBA. The PMOS transistor 221 receives the test signal TDB0 output from the bit line level control circuit 112 at its gate, and one is connected to the power supply VDD and the other is connected to the bit line DTA. In the PMOS transistor 222, the test signal TDB1 output from the bit line level control circuit 112 is input to the gate, one of which is connected to the power supply VDD and the other is connected to the bit line DBA.

  The OR circuit 225 receives the bit line control signal DISTB output from the bit line level control circuit 112 and the internal address signal YSLA output from the address decoder 113, and outputs the precharge control signal PCA as the precharge circuit 226 and the NMOS transistor 223. 224 to the gate. The precharge circuit 226 is activated when the input precharge signal PCA is LOW and deactivated when HIGH.

  Next, the operation of the semiconductor device according to the first embodiment of the present invention will be described. The operation of the semiconductor device according to the first embodiment will be described using the configuration diagram of FIG. 2, the timing chart of FIG. 3, and the truth table of FIG. For the sake of explanation, the port controlled by the first clock signal CLKA (hereinafter referred to as port A) is the test target port, and the port controlled by the second clock signal CLKB (hereinafter referred to as port B) is the harm port. To do. The access to the same address by the port A for the write operation and the port B for the read operation is referred to as the same address access. The power supply VDD level is called HIGH, the GND level is called LOW, the write operation of HIGH data is called HIGH write, and the write operation of LOW data is called LOW write. Since the output circuit after the bit line uses a general output circuit, the detailed operation description in the present invention is omitted.

  FIG. 3 is a timing chart for testing the port A write operation with the same address access. The initial state of the memory cell array 110 is assumed to hold HIGH data. From time T1 to time T4, operation waveforms of a successful write example of the port A LOW write test in the same address access are shown. In addition, from time T4 to time T8, operation waveforms of a write failure example are shown in the HIGH write test of port A with the same address access. In addition, from time T8 to time T9, read operation waveforms for reading the written data are shown.

  First, the time T0 is an initial state, and the clock signals CLKA, CLKB output from the BIST 101 and the test signals TESTA, TESTB, TDISTA, TDISTB, TD0, TD1, the write data signals DAi, DBi, the write enable signals WAE, WBE are All are LOW.

  The internal clock output circuit 107 receives the clock signal CLKA and the test signals TESTA and TESTB LOW, and sets the internal clock signal ICLA to LOW. The internal clock output circuit 107 receives the clock signal CLKB and the test signals TESTA and TESTB LOW, and sets the internal clock signal ICLB to LOW.

  When the internal clock signal ICLA is LOW, the word line WLA and the internal address signal YSLA are LOW. When the internal clock signal ICLB is LOW, the word line WLB and the internal address signal YSLB are LOW. Since the output data WDTA, WDBA, WDTB, and WTBB from the write buffer 114 are in the standby state, they are HIGH.

  In the B port column control circuit 210, since the test signal TDISTA and the internal address signal YSLB are LOW, the output PCB of the OR circuit 215 becomes LOW, the NMOS transistors 213 and 214 are turned OFF, and the precharge circuit 216 activated by LOW. The bit lines DTB and DBB are HIGH precharged via the.

  In the A port column control circuit 220, since the test signal TDISTB and the internal address signal YSLA are LOW, the precharge control signal PCA output from the OR circuit 225 is LOW, the NMOS transistors 223 and 224 are turned OFF, and LOW. The bit lines DTA and DBA are HIGH precharged through the precharge circuit 226 activated at the same time.

  The SRAM cell is initialized with HIGH data, the latch node CELLT is HIGH, and the latch node CELLB is LOW.

  At time T0, the test signals TDISTA and TD1 from the BIST 101 change from LOW to HIGH. When the test signal TDISTA is HIGH and the test signal TESTA is LOW, the propagation of the clock signal CLKA to the internal clock signal ICLA is stopped. The port A write enable signal WAE changes from LOW to HIGH, and the port A is set from the read mode to the write mode.

  When the test signal TDISTA becomes HIGH and the bit line control signal DISTA (or the internal address signal YSLB) output from the bit line level control circuit 112 becomes HIGH, the precharge signal PCB becomes HIGH in the B port column control circuit 210. The precharge circuit 216 is turned off, and the NMOS transistors 213 and 214 are turned on. Since the write data signals WDTB and WDBB from the write control circuit 114 are HIGH except during B port write, if the threshold voltage of the NMOS transistors 213 and 214 of the B port column control circuit 210 is Vc, the bit line of the B port The potentials of DTB and DBB are limited by the drop voltage Vc, and the potential drops only from VDD to (VDD−Vc).

  At time T1, the clock signal CLKB changes from LOW to HIGH, and the internal clock signal ICLB changes from LOW to HIGH via the internal clock output circuit 107. The internal clock signal ICLB raises the word line WLB from LOW to HIGH via the word driver 109. As the word line WLB rises, HIGH data is read from the SRAM cell, and the bit line DBB drops to (VDD−Vc).

  At time T2, the test signal TESTA changes from LOW to HIGH, and the propagation of the clock signal CLKB to the internal clock signal ICLB stops.

  At time T3, the clock signal CLKA changes from LOW to HIGH, and the internal clock signal ICLA changes from LOW to HIGH via the internal clock output circuit 107. In response to the internal clock signal ICLA being HIGH, the test signal TESTA being HIGH, TDISTA being HIGH, and TDISTB being LOW, the word driver 109 simultaneously changes the word lines WLA and WLB from LOW to HIGH. The write control circuit 114 also receives the LOW of the data signal DAi from the BIST 101 and the HIGH of the internal clock signal ICLA, and the write data signal WDTA, which is the output of the write control circuit 114, changes from HIGH to LOW, and the A port column control circuit The bit line DTA of the port A is changed from HIGH to LOW through the 220 NMOS transistor 223.

  The bit line DTA is LOW, DBA is HIGH, DTB is HIGH, DBB is (VDD−Vc), the word lines WLA and WLB are HIGH, and the NMOS cell 201, 202, 203, 204 is connected to the SRAM cell 200. Through the port A. At this time, the potential (VDD−Vc) of the bit line DBB hinders the operation in which the latch node CELLB becomes HIGH.

  At time T4, in response to the clock signal CLKA changing from HIGH to LOW, the SRAM internal signal returns to the standby state. Further, the test signal TESTA changes from HIGH to LOW, and the propagation of the clock CLKB to the internal clock signal ICLB becomes effective.

  At time T5, the test signal TD0 changes from LOW to HIGH, and the bit line control signal TDA0 changes from HIGH to LOW. Further, the test signal TD1 changes from HIGH to LOW, and the bit line control signal TDA1 changes from LOW to HIGH. In the B port column control circuit 210, since the test signal TDA0 becomes LOW, the bit line DBB is precharged to HIGH via the PMOS transistor 212, and when the test signal TDA1 becomes HIGH, the PMOS transistor 211 is turned OFF.

  The clock signal CLKB changes from LOW to HIGH, and the internal clock signal ICLB changes from LOW to HIGH via the internal clock output circuit 107. The internal clock signal ICLB raises the word line WLB from LOW to HIGH via the word driver 109. As the word line WLB rises, LOW data is read from the SRAM cell and DTB drops to (VDD-Vc).

  At time T6, the test signal TESTA changes from LOW to HIGH, and the propagation of the clock signal CLKB to the internal clock signal ICLB stops.

  At time T7, the clock signal CLKA changes from LOW to HIGH, and the internal clock signal ICLA changes from LOW to HIGH via the internal clock output circuit 107. In response to the internal clock signal ICLA being HIGH, TESTA being HIGH, TDISTA being HIGH, and TDISTB being LOW, the word driver 109 simultaneously changes the word lines WLA and WLB from LOW to HIGH.

  Further, the write control circuit 114 receives HIGH (not shown) of the data signal DAi from the BIST 101 and HIGH of the internal clock signal ICLA, and the write data signal WDBA that is the output of the write control circuit 114 changes from HIGH to LOW. The bit line DBA of the port A is changed from HIGH to LOW through the NMOS transistor 224 of the port column control circuit 220. When the bit line DTA is HIGH, DBA is LOW, DTB is (VDD−Vc), DBB is HIGH, and the word lines WLA and WLB are HIGH, the NMOS transistors 201, 202, 203, 204 are connected to the SRAM cell 200. Then, HIGH data is written from port A.

  At this time, since the potential of DTB is (VDD−Vc), the operation of the latch node CELLT becoming HIGH via the NMOS transistor 203 of the SRAM cell 200 is inhibited. At time T7 in FIG. 3, an operation waveform in which the write operation fails is shown, and the data of the latch nodes CELLT and CELLB of the SRAM cell 200 is not inverted.

  At time T8, the SRAM macro 100 enters a standby state in response to the clock signal CLKA changing from HIGH to LOW. When the test signals TDISTA, TD1, and TSETTA from the BIST 101 are changed from HIGH to LOW, and the bit line control signals TDA0 and TDA1 are changed to HIGH, the PMOS transistors 211 and 212 of the B port column control circuit 210 are turned OFF, and the precharge circuit 216 is turned ON. Then, the bit lines DTB and DBB are precharged to VDD. The port A write enable signal WAE changes from HIGH to LOW to set the port A to the read mode.

  At time T9, the clock signal CLKA changes from LOW to HIGH, the internal clock signal ICLA changes from LOW to HIGH, and the word line WLA changes from LOW to HIGH. When the word line WLA becomes HIGH, the data of the SRAM cell 200 is read to the bit lines DTA and DBA. Since writing of HIGH data has failed at time T7, the bit lines DTA and DBA of the port A become (VDD−Vc) and VDD, respectively, and LOW data is read. Here, the potential drop Vc is a voltage determined by the threshold value of the NMOS transistor 223. Even though the expected read value is HIGH, the LOW data is read out, so the expected value does not match, and a defective write operation is detected.

  4A and 4B are truth tables showing the operations of the bit line level control circuit 112 and the column control circuit 111 of the semiconductor device according to the first embodiment. FIG. 4A shows the bit line control signal and the bit line potential of the B port that becomes the harming port when the port A is the test target port. FIG. 4B shows the bit line control signal and the bit line potential of the A port that becomes the harming port when the port B is the test target port. The column control circuit 111 includes an A port column control circuit 220 and a B port column control circuit 210.

  The values of the bit line control signals DISTA, TDA0, TDA1, DISTB, TDB0, and TDB1, which are the outputs of the bit line level control circuit 112, are determined from the values of the test signals TDISTA, TDISTB, TD0, and TD1 generated from the BIST 101. The A port column control circuit 220 receives the bit line control signals DISTB, TDB0, and TDB1, and sets the precharge levels of the A port bit lines DTA and DBA to a state where the VDD level or the lower limit is (VDD−Vc), respectively. .

  The B port column control circuit 210 receives the bit line control signals DISTA, TDA0, TDA1, and sets the precharge levels of the B port bit lines DTB, DBB to a state where the VDD level or the lower limit is (VDD−Vc), respectively. .

  First, FIG. 4A shows a truth table of the bit line level control circuit when the port A is the test target port and the port B is the harmful port. Since the test mode is OFF when the test signal TDISTA is LOW, the bit line control signals TD0 and TD1 do not affect the test mode by either HIGH or LOW, and the internal signal DISTA is LOW, the bit line control signal TDA0, Both TDA1 are HIGH, and the B port column control circuit 210 causes the B port bit lines DTB and DBB to both be VDD precharged via the precharge circuit 216.

  Next, in the test mode in which 0 is written from the port A to the memory cell, the test signals TDISTA are HIGH, TDO, and TD1 are LOW and HIGH, respectively, and the bit line control signals TDA0 and TDA1 output from the bit line level control circuit 112 are used. Becomes LOW and HIGH, respectively. Then, the bit line DTB of the B port which is the harming port is precharged to VDD by the PMOS transistor 212 of the B port column control circuit 210, and the lower limit potential of the bit line DBB is limited to (VDD−Vc) by the NMOS transistor 214. .

  Next, in the test mode in which one write is performed from the port A to the memory cell, the test signals TDISTA are HIGH, TDO, and TD1 are HIGH and LOW, respectively, and the bit line control signals TDA0 and TDA1 output from the bit line level control circuit 112 are used. Become HIGH and LOW, respectively. The bit line DBB on the B port side is precharged to VDD by the PMOS transistor 212 of the B port column control circuit 210, and the lower limit potential of the bit line DTB is limited to (VDD−Vc) by the NMOS transistor 213.

  Next, FIG. 4B shows a truth table of the bit line level control circuit when the port B is the test target port and the port A is the harmful port. When the test signal TDISTB is LOW, the test mode is in the OFF state. Therefore, the test signals TD0 and TD1 do not affect the test mode by either HIGH or LOW, and the internal signal DISTB is LOW and the data signals TDB0 and TDB1 are both Become HIGH. Then, the A port column control circuit 220 causes both the A port bit lines DTA and DBA to be precharged to VDD via the precharge circuit 226.

  Next, in the test mode in which LOW write is performed from the port B to the memory cell, the test signal TDISTA becomes HIGH, TDO, TD1 becomes LOW, HIGH, respectively, and the bit line control signals TDB0, TDB1 output from the bit line level control circuit 112 are , LOW and HIGH respectively. The bit line DTA of the A port is precharged to VDD by the PMOS transistor 221 of the A port column control circuit 220, and the lower limit potential of the bit line DBA is limited to (VDD−Vc) by the NMOS transistor 224.

  Next, in the test mode in which a HIGH write is performed from the port B to the memory cell, the test signals TDISTB are HIGH, TDO, and TD1 are HIGH and LOW, respectively, and the bit line control signals TDB0 and TDB1 output from the bit line level control circuit 112 are used. Become HIGH and LOW, respectively. The bit line DBA of the A port is precharged to VDD by the PMOS transistor 222 of the A port column control circuit 220, and the lower limit potential of the bit line DTA is limited to (VDD−Vc) by the NMOS transistor 223.

  Next, an operation flow at the time of testing the semiconductor device according to the first embodiment will be described with reference to FIG. The test of the semiconductor device according to the first embodiment includes a port A simultaneous operation test S401 and a port B simultaneous operation test S402. That is, after the port A operation test S401, the port B operation test S402 is performed.

  First, detailed step S422 of the simultaneous operation test S401 will be described. In step S403, HIGH data is written to all memory cells of the SRAM macro 100. In step S404, the test mode is set from the BIST 101, and the precharge of the bit line DBB of the offending port is turned off so as to inhibit the operation of the LOW data write from the test target port. As a result, the amplitude range of the bit line DBB is limited from VDD to (VDD−Vc).

  In step S405, HIGH data is read from the B port which is the harm port, and the bit line DBB is lowered to (VDD-Vc). In step S406, LOW write is performed from the test target port with the same address access. In step S407, it is determined whether all addresses to be tested have been tested. If the final address has not been tested, the address is incremented by one, and the process returns to step S406.

  In step S408, the test mode is canceled from the BIST 101, and the control of the precharge level of the bit line is canceled.

  In step S409, reading is performed. In step S410, it is determined whether the read data matches the expected value LOW. If they match, the address is incremented by one. If they do not match, the test ends as test FAIL.

  In step S411, it is determined whether all addresses to be tested have been read. If the final address has not been read, the process returns to step S409.

  Steps S413 to S422 are a test flow of the reverse data (executed with the read / write data values reversed) of steps S403 to S410, and the same processing is performed.

  Step S402 is a test flow in which the port in step S401 is replaced (port A is replaced with the harm port and port B is replaced with the test target port), and the same processing as in step S401 is performed. Note that description of this process is omitted.

  FIG. 7 shows details of the internal clock output circuit 107 arranged in the SRAM macro 100. The internal clock output circuit 107 inputs the output of the NAND circuit 701 that receives the opposite phases of the test signals TESTA and TDISA and the opposite phase of the clock signal CLKA and the test signal TESTB to the NAND circuit 702. The output of the NAND circuit 702 is output as an internal clock signal ICLA via the inverter 703.

  Further, the output of the NAND circuit 711 that receives the opposite phases of the test signals TESTB and TDISB and the opposite phase of the clock signal CLKB and the test signal TESTA are input to the NAND circuit 712. The output of the NAND circuit 712 is output as an internal clock signal ICLB via the inverter 713.

  According to the semiconductor device according to the first embodiment, the operation margin is poor due to the mutual interference between the ports generated in the multi-port SRAM, which was difficult to test with the prior art (write when the read operation of the harmful port precedes). Can be implemented in a short test. As a result, testing can be performed under conditions with the strictest operating margin in testing before product shipment, reducing the occurrence rate of defects after product shipment and eliminating the need for clock skew swing testing. Shortening is possible.

  The reason is that the bit line potential is reduced only to a certain potential during the read operation, and one of the bit lines of the harming port is set to HIGH, and one is lowered to the lowest potential that can be taken during the read operation. The same address access test is performed in which the word lines WLA and WLB are simultaneously activated. As a result, it is possible to perform a test that reproduces the lowest potential of the bit line potential of the harming port caused by the difference in clock skew between ports without performing clock skew swing between ports.

  A more detailed operation will be described with reference to the block diagram of the semiconductor device according to the present embodiment in FIG. 2 and the timing chart in FIG. When the same address access test is performed from the test target port and the harming port shown in FIG. 2 and an operation margin failure is detected, the test mode signal TDISTA is HIGH and the TESTA is LOW as shown at time T5 in the operation description of FIG. Therefore, the clock signal CLKB becomes valid and the word line WLB changes from LOW to HIGH.

  The bit line control signals TDA0 and TDA1 are LOW and HIGH, respectively, the bit line DBB of the harm port is precharged to HIGH, and the PMOS transistor 211 of the B port column control circuit 210 connected to the bit line DTB is turned OFF. The word line WLB becomes HIGH, LOW data is read from the SRAM cell, and the bit line DBB is lowered to VDD and the bit line DTB is lowered to (VDD−Vc). Since the test signal TDISTA is HIGH, the bit line DTB is not precharged and holds (VDD−Vc). That is, the bit lines DTB and DBB of the harm port are held at the potential (VDD−Vc) that drops during reading.

  At time T7, the test signals TESTA and TDISTA are HIGH, and the clock signal CLKA is changed from LOW to HIGH, so that the same address access in which the word lines WLA and WLB are simultaneously changed from LOW to HIGH is performed. The bit lines DTA, DBA, DBB are at VDD and the bit line DTB is at (VDD-Vc), and the word lines WLA, WLB are simultaneously changed from LOW to HIGH. Simultaneously with the movement of the latch nodes CELLT and CELLB to HIGH and LOW by the HIGH data write from the port A, the latch node CELLT is affected by the bit line DTB of the harming port to inhibit the operation of the latch node CELLT becoming HIGH. As a result, the operation margin is reduced and the latch nodes CELLT and CELLB cannot be inverted.

  By performing a read using the HIGH data written at time T9 as an expected value and confirming that data different from the expected value has been output, it is possible to detect a defect in the operation margin at the same address access.

Embodiment 2. FIG.
Next, a semiconductor device according to the second embodiment of the present invention will be described. The semiconductor device shown in FIG. 8 is obtained by changing the column control circuit 1112 and the write control circuit 1142 from the first embodiment, and the standby write data signals WDTA, WDBA, WDTB, and WDBB are changed from HIGH to HiZ. It is an example. This is the difference between driving the write data signals WDTA, WDBA, WDTB, and WDBB with a binary driver of HIGH and LOW or driving with a ternary driver of HIGH, LOW, and HiZ.

  When driven by a ternary driver and the write data signals WDTA, WDBA, WDTB, and WDBB are set to HiZ during standby, the write control circuit 1142 outputs the write control signals WEA and WEB to the column control circuit 1112. FIG. 10 shows details of the column control circuit 1112. The column control circuit 1112 includes PMOS transistors 802 and 805 to which the test signals TDA0 and TDA1 are input to the gates respectively, and an NMOS circuit 810 that receives the reverse phase of the write control signal WEB and the test signal DISTA to be input to the gates. Transistors 803 and 806 are provided.

  A PMOS transistor 802 and an NMOS transistor 803, one of which is connected to the power supply VDD, are connected to the bit line DTB, and a PMOS transistor 805 and an NMOS transistor 806, one of which is connected to the power supply VDD, are connected to the bit line DBB. . The OR circuit 807 that receives the bit line control signal DISTA and the internal address signal YSLB outputs the precharge signal PCB to the precharge circuit 801 and the gates of the NMOS transistors 808 and 809.

  Next, the operation of the semiconductor device according to the second embodiment configured as described above will be described. FIG. 9 is a timing chart showing the operation of the semiconductor device according to the second embodiment of the present invention. Write data signals WDTA, WDBA, WDTB, and WDBB at the time of standby are HiZ. Since the bit line control signal DISTA is HIGH, the output of the NAND circuit 810 is HIGH, the gates of the NMOS transistors 803 and 806 are HIGH, the NMOS transistors 803 and 806 are turned ON, and the bit line is controlled by the threshold voltage of the NMOS transistors 803 and 806. The lower limit (VDD−Vc) of the level is determined, and the same bit line level control as in the first embodiment is realized. Further, since the OR circuit 807 is turned ON and the gates of the NMOS transistors 808 and 809 are HIGH, the NMOS transistors 808 and 809 are turned ON, and the write data signals WDTB and WDBB are HiZ, so that the potentials of the bit lines DTB and DBB are set. It does not affect.

  In a normal read operation, the bit line control signal DISTA is LOW, the write control signal WEB is LOW, and the internal address signal YSLB is HIGH. Therefore, the NMOS transistors 803, 806, 808, and 809 are turned on, Similar bit line level control is performed.

  The difference from the first embodiment is that, during normal reading, the write control signal WEB is set to LOW and the NMOS transistors 803 and 806 are turned ON, so that the port to be read depends on the threshold value (Vc) of the NMOS transistors 803 and 806. By setting the lower limit potential of the bit lines DTB and DBB to (VDD−Vc) and setting the bit line control signal DISTA to HIGH during the test, the NMOS transistors 803 and 806 of the harm port are turned ON, and the bit line of the harm port is The lower limit potential of DTB and DBB is (VDD−Vc).

  By this operation, the same bit line level control as in the first embodiment can be performed, and the same effect can be obtained by performing the test in the same flow as in the first embodiment.

Embodiment 3 FIG.
Next, a semiconductor device according to the third embodiment of the present invention will be described. The semiconductor device according to the third embodiment shown in FIG. 11 is obtained by changing the configuration of the column control circuit 1112 of the second embodiment, and the operation timing is the same as that in FIG.

  FIG. 11 shows an example of the configuration of the column control circuit. The output of the NAND circuit 810 that receives the opposite phases of the write control signal WEB and the test signal DISTA is input to the gate of the NMOS transistor 813, one of which is connected to the power supply VDD. At the same time, it is input to the gate of the PMOS transistor 812 as a signal inverted by the inverter 814 (signal WENBB). A PMOS transistor 802 having one connected to the power supply VDD and a PMOS transistor 811 having a gate connected to the signal WENBB are connected to the bit line DTB, and a PMOS transistor 804 having one connected to the power supply VDD is connected to the bit line DBB. A PMOS transistor 812 is connected. The other of the NMOS transistor 813 is connected to the other of the PMOS transistor 811 and the PMOS transistor 812.

  Next, the operation of the semiconductor device configured as described above will be described. As shown in FIG. 9, since the bit line control signal DISTA is HIGH during the test, the output of the NAND circuit 810 is HIGH, the output of the inverter 814 is LOW, the gates of the PMOS transistors 811 and 812 are LOW, and the PMOS transistor 811 812 is turned ON. Further, when the gate of the NMOS transistor 813 becomes HIGH and the potentials of the bit lines DTB and DBB become (VDD−Vc) or less, the NMOS transistor 813 is turned ON, and the lower limit (VDD−Vc) of the bit line level is set by the threshold voltage of the NMOS transistor 813. The same bit line level control as in the first and second embodiments can be realized.

  Next, the operation of the semiconductor device configured as described above will be described. The difference from the first embodiment is that the write control signal WEB is set to LOW during normal reading, the gate of the NMOS transistor 813 is set to HIGH, and the gates LOW of the PMOS transistors 811 and 812 are set. ), The lower limit potential of the bit lines DTB and DBB of the read target port is set to (VDD−Vc), and during the test, the bit line control signal DISTA is set to HIGH, so that the NMOS transistor 813 of the harming port is set to HIGH, PMOS. By setting the gates of the transistors 811 and 812 to LOW, the lower limit of the bit line DTB and DBB potential of the harm port is set to (VDD−Vc). By this operation, the same bit line level control as in the first embodiment can be performed, and the same effect can be obtained by performing the test in the same flow as in the first embodiment.

Embodiment 4 FIG.
Next, a semiconductor device according to Embodiment 4 of the present invention will be described. The semiconductor device according to the fourth embodiment shown in FIG. 12 is obtained by changing the configuration of the column control circuit 1112 of the second embodiment, and the operation timing is the same as FIG. FIG. 12 shows an example of the configuration of the column control circuit 1112. An inverter 814 that receives the output of the NAND circuit 810 that receives the reverse phase of the write control signal WEB and the test signal DISTA, and the output of the inverter 814 (signal WENBB) PMOS transistors 811 and 812 that are input to the gate, and one of them is connected to the power supply VDD, and a PMOS transistor 815 that connects a contact point between the PMOS transistors 811 and 812 to the gate and the drain are provided. PMOS transistors 802 and 811 and an NMOS transistor 808 are connected to the bit line DTB, and PMOS transistors 804 and 812 and an NMOS transistor 809 are connected to the bit line DBB.

  During the test, since the bit line control signal DISTA is HIGH, the output of the NAND circuit 810 is HIGH, the output of the inverter 814 is LOW, the gates of the PMOS transistors 811 and 812 are LOW, and the PMOS transistors 811 and 812 are ON. When the potentials of the bit lines DTB and DBB become (VDD−Vc) or less, the PMOS transistor 815 is turned on, and the lower limit (VDD−Vc) of the bit line level is determined by the threshold voltage of the PMOS transistor 815. The same bit line level control is realized.

  The difference from the first embodiment is that during normal reading, the write control signal WEB is set to LOW, and the gates of the PMOS transistors 811 and 812 are set to LOW. By setting the lower limit potential of the bit lines DTB and DBB of the read target port to (VDD−Vc) according to the threshold value (Vc) of the PMOS transistor 815, and setting the bit line control signal DISTA to HIGH during the test, By setting the gates of the transistors 811 and 812 to LOW, the lower limit of the bit line DTB and DBB potential of the harm port is set to (VDD−Vc). By this operation, the same bit line level control as in the first embodiment can be performed, and the same effect can be obtained by performing the test in the same flow as in the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the first to fourth embodiments, the column control circuit 111 controls the bit line potential of one of the harming ports to a potential that is lowered by the threshold value, but the bit line level control circuit 112, the write control circuit Various circuits such as 114 and address decoder 113 may be configured to control the bit line potential of the harm port.

CLKA, CLKB Clock signal ICLA, ICLB Internal clock signal ADDn Address signal DAi, DBi Data signal WAE, WBE Write enable signal WEA, WEB Write control signal XKA, XEA, XKB, XEB Internal address signal YSLA, YSLB Internal address signal WLA, WLB Word line DTA, DBA, DTB, DBB Bit line TDISTA, TDISTB, TD0, TD1 Test signal DISTA, DISTB, TDA0, TDA1, TDB0, TDB1 Bit line control signals WDTA, WDTB, WDBA, WDBB Write data signal PCA, PCB Precharge Control signal CELLT, CELLB Latch nodes Va, Vb, Vc Potential drop 100 SRAM macro 101 BIST
107 Internal clock output circuit 109 Word driver 110 Memory cell array 111 Column control circuit 112 Bit line level control circuit 113 Address decoder 114 Write control circuit 1112 Column control circuit 1142 Write control circuit 200 SRAM cells 201, 202, 203, 204 NMOS transistor 205, 206 Inverter 210 B port column control circuit 211, 212, 221, 222 PMOS transistor 213, 214, 223, 224 NMOS transistor 215, 225 OR circuit 216, 226 Precharge circuit 220 A port column control circuit 701, 702, 711, 712 NAND circuit 703, 713, 814 Inverter 801 Precharge circuit 802, 805, 811, 812, 815 PMOS transistor 803, 806, 808, 809, 813 NMOS transistor 807 OR circuit 810 NAND circuit 814 Inverter 11, 13, 15, 22 NAND circuit 12, 14 Inverting buffer 16, 23 Inverter 17, 24 CMOS transfer gate 18, 25 NMOS transistor 19 , 26 AND circuit 20, 27 NOR circuit 21, 28 Inverted word driver (inverter)

Claims (4)

A word line corresponding to a plurality of ports;
A bit line corresponding to the plurality of ports and controlled to a first potential or a second potential higher than the first potential according to write data;
Memory cells connected to the word lines and the bit lines corresponding to the plurality of ports;
A word driver circuit that activates the word line with a timing signal corresponding to each of the plurality of ports;
A bit line level control circuit for generating a control signal for controlling a potential of the bit line corresponding to each of the plurality of ports based on a test signal;
A column control circuit for controlling the potential of the bit line based on the output of the bit line level control circuit,
The semiconductor memory device, wherein at the time of testing, at least one bit line potential of the harm port with respect to the test target port is controlled to be lower than the second potential by a threshold.   2. The bit line of the harm port corresponding to one bit line controlled to the second potential of the test target port is controlled to be lower than the second potential by a threshold value. Semiconductor memory device. A word line corresponding to a plurality of ports;
A bit line corresponding to the plurality of ports and controlled to a first potential or a second potential higher than the first potential according to write data;
For a semiconductor memory device having a memory cell having the word line and the bit line corresponding to the plurality of ports,
During the write test of the test target port, the same data is written as an initial value to all the memory cells,
After activation of the word line to be tested, at least one of the bit lines of the harm port is precharged to a potential lower than the second potential by a threshold value,
In the state where the harming port is precharged, the initial value and the reverse data are written from the test target port to the same address of the test target memory cell,
A test method for a semiconductor memory device, which activates a word line of the harm port for the same address of the test target memory cell and determines whether or not the test target memory cell is rewritten with the reverse data.   4. The test method for a semiconductor memory device according to claim 3, wherein the test method is controlled by a BIST built in the semiconductor device.

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