JP2001093297A - Test device for semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a peak current generated by batch selection of word lines, non-selection control, setting of a write-in level of a bit line, and batch control of recovery, when accelerated stress is applied to a memory cell in burn-in and the like and screening is performed. SOLUTION: This device is provided with a cell 11 connected to word lines WL and a pair of bit line BL, /BL, a transistor 13 conducted in a normal operation state and charging a pair of bit line, a test mode setting means setting a test mode, a control means controlling so that the transistor 13 becomes in a non-conduction state at the time of a test mode, a dummy word line DWL brought into a selection state at the time of a test mode, and a dummy cell 16 connected to a dummy word line and a pair of bit line and having same constitution as the cell 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a static semiconductor memory device, and more particularly to an improvement for avoiding an increase in test cost in a burn-in test.

[0002]

2. Description of the Related Art In general, when a semiconductor device is manufactured and shipped, in order to ensure the reliability of the device, a potential defect of the device is exposed so that a non-defective device is not deteriorated or made defective. Screen for removal. As a screening method, a burn-in test capable of simultaneously realizing electric field acceleration and temperature acceleration is often used.

In this burn-in test, the device is operated at a voltage higher than that in actual use and at a temperature higher than that in actual use, so that the device experiences a stress in a short period of time longer than the initial failure period under actual use conditions. Devices that may cause initial operation failures are selected and screened in advance before shipment.

As a result, a device that may cause an initial operation failure can be efficiently removed, and the reliability of a product can be increased.

In the screening of a semiconductor memory device having a large number of memory cells, destruction of a memory cell is checked by applying stress to an operating state of the memory cell, for example, a write state. Here, the time for applying the stress is much longer than the normal operation cycle, for example, it is necessary to take several seconds. Therefore, if the test is performed for each address while incrementing the address, an enormous test time is required. It is not realistic. Therefore, it has been conventionally performed that all cells are simultaneously selected and a stress is simultaneously applied.

FIG. 9 shows a partial configuration of an address buffer circuit and a row decoder in a conventional semiconductor memory device that performs simultaneous selection of all cells. Address buffer circuit 1
00 are provided as many as the number of input pads 101, and each address buffer circuit 100
And two NAND circuits 103 and 104 to which an output from the buffer circuit 102 and an all-cell test signal / test which is set to “L” level during the all-cell test are input. It is composed of The output from the buffer circuit 102 is directly sent to the NAND circuit 103 by the NAND circuit 104.
Are input in a state where the output from the buffer circuit 102 is inverted.

The address buffer circuit 100 receives external address inputs Aiin, Ajin,... And receives a pair of complementary internal addresses Ai, / Ai, Aj, / A.
j ... are output. A combination of these complementary internal addresses is input to a plurality of AND circuits 105 constituting a predecoder of a row decoder via an address signal bus, and is decoded by these AND circuits 105 to thereby generate a predecode signal bus. Is finally determined, and the word line is finally driven to perform cell selection.

Here, in the all-cell selection test mode, the all-cell test signal / test is set to "L" level, and the output addresses Ai, / Ai,
Aj, / Aj... Are all fixed at the H level. As a result, as the decoding result of the row decoder, all the decoding signals are in the selected state, all the word lines are driven, and all the cells are simultaneously selected.

Next, the manner in which stress is applied to actual memory cells will be described with reference to the circuit diagram of FIG. 10 by taking as an example the case where write stress is applied to a cell array of a static semiconductor memory device (SRAM). .

In the case of normal writing, one word line is selected from a plurality of word lines WL0 to WLn by a row decoder, and a plurality of pairs of column transfer gates CTG for writing are written by column decoders 111 to 111.
0-0, CTG0-1,... CTGm-0, CTGm-1
A pair of column transfer gates is selected from
The data of the data signal line pair Din, / Din is transferred to one bit line pair of the plurality of bit lines BL0, / BL0... BLm, / BLm, and the selected memory cell 112 is selected.
, Data is supplied and writing is performed.

On the other hand, in the case of the all-cell test, all the word lines WL0 to WLn are set to the selected state, and all the outputs from the column decoders 111,... Column transfer gates CTG0-0, CTG0-1,.
TGm-0 and CTGm-1 are selected, and data is transferred to all bit line pairs BL0, / BL0... BLm, / BLm. By doing so, all the memory cells 112 are in the written state, and a desired stress is applied.

Incidentally, a recent SRAM cell has a CMO
A so-called 6-transistor type cell using an S flip-flop is mainly used.

FIG. 11 shows a circuit configuration of the six-transistor type cell. Here, reference numerals 121 and 122 denote P-channel MOS transistors, respectively.
Reference numeral 26 denotes N-channel MOS transistors, and N1 and N2 denote cell nodes.

At the time of writing data to a cell, the cell node N1 or N2 is pulled down to the "L" level by overcoming the PMOS load, that is, the transistor 121 or 122, which is the active element of the flip-flop storing the cell data. Needs to be inverted. For this reason, as compared with the case of a Hi-R (high resistance) type cell using a high resistance as a load, "L"
The value of the write current flowing through the bit line on the level which has become the level increases. Therefore, when data of many cells connected to the same bit line is written at the same time (data is inverted), a large current flows and the driving capability of the writing circuit is exceeded.

Therefore, when all the cells are selected for the burn-in test, a normal write operation for each address is performed for all the addresses, and all the cells are set in advance so that the data to be stressed is obtained. It is necessary to write data to the In this way, even if all cells are selected at the same time, the already written cell data is the same as the data to be written, so that the flip-flop output state is inverted in the memory cell. No such problem occurs.

Next, consider the charge / discharge current when all the word lines are selected or all the bit lines are set to the write level state. If all the word lines are selected at the same time as the test starts, all the word line capacitances will be charged to the selected level at the same time, and at the end of the test, the corresponding charges will be discharged. In any case, a peak transient current occurs.

On the column side, a general SRA
In the case of M, writing is performed by discharging one bit line of the bit line pair to the ground level. Therefore, at the time of the stress test, the charges in one of the bit line pairs are discharged at the same time, and the test ends. Sometimes it is necessary to recharge them (write recovery) at the same time, and a peak transient current occurs like a word line.

In normal operation, charging and discharging of these word lines and bit lines are performed for each address. Therefore, the peak current when all cells are selected is such that only a small number of rows and columns are selected. It can be easily understood that the value becomes much larger than the normal operating current. Furthermore, in stress application, in order to test long-term reliability in a short time, it is necessary to perform an accelerated test. Generally, the power supply level is set to be higher than a normal value and the operation is performed.
The current value becomes larger as compared with the normal operation.

The burn-in test is a time-consuming test as described above. However, on the other hand, since it is not necessary to perform detailed control for each chip and check output data of each chip, it is common to arrange a large number of chips in a rack and drive them simultaneously by one tester at the same time. Therefore, the number of chips that can be tested simultaneously is determined by the relationship between the current drive capability of the power supply of the tester and the current consumption of each chip.

Here, at the start and end of the test described above, if an excessively large peak current occurs transiently, regardless of the amount of current in the original stress state, the peak current becomes much larger than this. In addition, the number of chips that can be simultaneously measured is limited, and the test cost may be extremely increased.

In a general SRAM, the bit line is normally charged to "H" level. This is to prevent erroneous writing of data in a state other than writing since the cell data is inverted when the bit line goes to “L” level. Therefore, a load circuit for charging to the “H” level is connected to the bit line. 12 to 14 show various configurations of these load circuits.

FIG. 12 shows a P-channel MOS transistor 131 having a gate connected to the ground potential. The transistor 131 is always on and prevents a load at the time of reading and prevents data destruction due to a decrease in bit line potential.

FIG. 13 shows a P-channel MOS transistor 1 having a gate supplied with a recovery pulse signal.
32. The transistor 132 is controlled so as to be turned on by a recovery pulse signal at the time of reading or writing, and recharging (recovery) of the bit line potential is performed.

The circuit shown in FIG. 14 comprises a flip-flop 133, and the bit line potential is fed back and latched. In the configuration shown in FIG. 14, the amplification effect of the flip-flop mainly accelerates the level-up at the time of recovery, and at the same time, plays a role of preventing the bit line potential from swinging unnecessarily in the read state.

The recovery of the bit line is particularly important at the end of the write operation in which the bit line potential decreases to near the ground potential. However, as described above with reference to FIG. , The bit line is generally recovered to the power supply potential. Further, since the potentials of the data signal line pair Din and / Din for transferring the write data to the bit line shown in FIG. 10 are both recovered to the “H” level after the end of the write, the write column gate is not selected. By delaying the return timing with respect to the recovery timing of the data signal line, the recovery state of the data signal line is transmitted to the bit line via the column gate and contributes to the recovery of the bit line.

[0026]

As described above, conventionally,
At the start and end of the burn-in test, a transiently large peak current flows, so that the number of chips that can be measured simultaneously is limited, and the test cost may be extremely increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of preventing an increase in test cost when performing a burn-in test.

[0028]

A static semiconductor memory device according to the present invention is electrically connected to a word line and a bit line pair and a static cell connected to the word line and the bit line pair in a normal operation state. A load transistor for charging the bit line pair, test mode setting means for setting a test mode, load control means for controlling the load transistor to be in a non-conductive state in the test mode, and a selected state in the test mode And a dummy cell connected to the dummy word line and the bit line pair and having a configuration equivalent to the static cell.

According to the static type semiconductor memory device of the present invention, the word line and the bit line pair, the static cell connected to the word line and the bit line pair are electrically connected to each other for a certain period after the end of the write operation. A bit line load circuit that charges a line pair; a test mode setting unit that sets a test mode; a load control unit that controls the bit line load circuit to be in a non-conductive state during the test mode; A dummy word line to be selected and a dummy cell connected to the dummy word line and the bit line pair and having a configuration equivalent to the static cell.

A static semiconductor memory device according to the present invention comprises: a bit line pair; a flip-flop circuit connected to each bit line of the bit line pair so as to hold the potential of the bit line pair; A load transistor that conducts and charges the bit line pair; a test mode setting unit that sets a test mode; and a load control unit that controls the load transistor to be in a non-conductive state in the test mode. I have.

According to the static semiconductor memory device of the present invention, a plurality of word lines, a test mode setting means for setting a test mode, a row address control means for setting a row address to an all-selected state in the test mode, and a test mode And a word line selecting means for starting a selecting operation for each of the plurality of word lines at a different timing regardless of the row address, and setting the selected state for a substantially equal period of time. ing.

According to the semiconductor memory device of the present invention, there is provided a semiconductor memory device having a test mode in which all of a plurality of word lines are set to a selected state. There is provided a selection control means for setting all of the plurality of word lines to a selected state by making different timings for transitioning the word lines to a selected state every time.

According to the semiconductor memory device of the present invention, there is provided a semiconductor memory device having a test mode in which a plurality of bit lines are all set to a selected state, wherein the plurality of bit lines are divided into certain units. There is provided a selection control means for setting all of the plurality of bit lines to a selected state by making different timings for transitioning the bit lines to a selected state every time.

According to the present invention, there is provided a semiconductor memory device having a test mode in which a plurality of word lines and a plurality of bit lines are all set to a selected state and all of a plurality of memory cells are simultaneously selected. Selection control means for dividing the plurality of memory cells into a certain unit, and changing the timing at which the memory cells transition to the selected state for each of the divided units to set all of the plurality of memory cells to the selected state; I have it.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described by way of embodiments with reference to the drawings.

FIG. 1 shows a circuit configuration according to a first embodiment when the semiconductor memory device according to the present invention is applied to an SRAM which performs a synchronous operation.

In the figure, a plurality of word lines WL0 to WL
n and a plurality of pairs of bit lines BL0, / BL0 to BLm, / B
Lm intersect with each other, and at the intersection of each bit line pair and the word line, an SRAM cell (hereinafter simply referred to as a cell) composed of a 6-transistor type cell as shown in FIG. ) 11 are arranged. Each of these cells 11 is connected to a corresponding bit line pair and word line. The plurality of word lines WL0 to WL0
WLn is selectively driven by the output of the row decoder 12.

P-channel MOS transistors 13 and 14 acting as load transistors are inserted in parallel between each bit line of the plurality of bit line pairs and the supply node of power supply voltage Vcc. I have. When a first test mode (test mode 1) is set to each gate of the one transistor 13 according to a test mode supplied from the outside, the gate is set to “H” level by a control circuit (not shown). Test control signal tes
t1 is input. The other transistor 14
The output of the OR circuit 15 to which the test control signal test1 and the recovery pulse signal are input is input to each of the gates.

A test dummy word line DWL is provided in parallel with the word lines WL0 to WLn. The dummy word line DWL and the plurality of pairs of bit lines BL0, / BL0 to BLm, / BLm are provided. At each intersection with the dummy cell 1 having a circuit configuration equivalent to the cell 11 respectively.
6 are arranged. The dummy word line DWL is connected to the buffer circuit 17 to which the test control signal test1 is input.
Driven by the output of

One end of each of the plurality of bit line pairs has one end of a write column gate 18 composed of an N-channel MOS transistor and a read column gate composed of a P-channel MOS transistor. 19 is connected to one end. Similarly, one end of a write column gate 20 composed of an N-channel MOS transistor and a P bit
One end of a read column gate 21 composed of a channel type MOS transistor is connected. The other end of the write column gate 18 is commonly connected to one of the pair of data signal lines Din and / Din, and the other end of the write column gate 20 is connected to the other data signal line Din. Commonly connected to signal line / Din. Further, the other ends of the read column gates 19 are connected to one of a pair of input nodes of a sense amplifier 22 provided for each column, and the other ends of the read column gates 21 are connected to each other. It is connected to the other input node of the sense amplifier 22 of the corresponding column.

The column gates 18 and 20 for writing provided for each column are connected to AND gates 23, respectively.
The gate is controlled by a signal formed by a circuit composed of the OR circuit 24 and the OR circuit 25. That is, the AND circuit 23 has a column address decode signal ad consisting of a plurality of bits.
d is input to the OR circuit 24 and the test control signal tes
t1 and a data write control signal (internal write enable signal) write are input, and the output of the AND circuit 23 and the output of the OR circuit 24 are input to the OR circuit 25. The output of the OR circuit 25 is input to each of the column gates 18 and 20 provided for each column.

The read column gates 19 and 21 provided for each column are connected to the NOR circuit 26, respectively.
And a gate formed by a signal formed by a circuit including the NAND circuit 27. That is, the test control signal test1 and the data write control signal w
write, and the output of the NOR circuit 26 is input to the NAND circuit 27 together with a column address decode signal add consisting of a plurality of bits. The output of the NAND circuit 27 is input to each of the column gates 19 and 21 provided for each column.

Further, a pair of data signal lines Din, / D
In order to provide predetermined write data to in and recover the data signal line, the data signal line is provided with a circuit composed of two OR circuits 28 and 29. One OR circuit 28 has write data Dat
a and the recovery signal are input, and the output of the OR circuit 28 is input to one data signal line Din. The other O
The write data Data is inverted and input to the R circuit 29, and the recovery signal is input to the R circuit 29.
The output of R circuit 29 is input to the other data signal line / Din.

FIG. 2 shows the configuration of a pad to which an external row address is input and the configuration of an input first-stage circuit connected to this pad. The external row address input to the pad 31 is directly input to the NAND circuit 33 via the buffer circuit 32, and is inverted and input to the NAND circuit 34. When the second test mode (test mode 2) is set according to the test mode supplied from the outside, both of the NAND circuits 33 and 34 are set to “L” level by a control circuit (not shown). The test control signal test2 is input. And the two NAs
The ND circuits 33 and 34 output internal row addresses Ai and / Ai at mutually complementary levels. Such circuits are provided by the number of pads 31.

FIG. 3 shows a configuration of a pad to which an external column address is input and an input first-stage circuit connected to the pad. The external column address input to the pad 41 is directly input to the NOR circuit 43 via the buffer circuit 42, and is also inverted and input to the NOR circuit 44. The test control signal test2 is input to both the NOR circuits 43 and 44. The two NOR circuits 43 and 44 output internal column addresses Aj and / Aj at mutually complementary levels. Such circuits are provided by the number of pads 41.

Next, the operation will be described.

When the burn-in test mode is set by the external control in the circuit having the above configuration, basically the following operation control is performed.

(1) All the load circuits of the bit lines are turned off.

(2) The test dummy word line DWL is set to the selected state.

(3) The column gates divided into the write path and the read path are controlled so that only the column gates in the write path conduct.

(4) The timing of closing the column gate after the end of writing is made earlier than the timing of recovering the data signal line pair.

Hereinafter, these operations will be described in detail with reference to the timing charts of FIGS.

First, before the stress is applied, the above-described pre-writing for each address is performed. First, test mode 1 is set by external control, and test control signal test1 is set to “H” level. In this pre-writing, the memory address is sequentially incremented in synchronization with the clock signal CLK, and the memory cells 11 are sequentially selected. Then, for example, if data “0” is written to all the memory cells 11 first, the write data Data “0” is supplied to the data signal lines Din and / Din. Here, the control of the above (3) is not different from the control performed in the case of performing normal writing, so that it has no influence.

That is, in the pre-writing, the write column gates 18 and 20 of the corresponding column are turned on according to the column address, and the data signal lines Din and / Din are turned on.
Is transferred to the bit line pair of the corresponding column.
On the other hand, one word line is selectively driven by the row decoder 12 according to the row address. The memory cell 11 corresponding to the selected column and row is selected, and “0” data is written in the memory cell 11.

When the test control signal test1 is at "H" level, all the transistors 13 and 14, which are the bit line loads, are turned off.
Is performed. At this time, even if the "L" level recovery pulse signal is input to the OR circuit 15, since the test control signal test1 is at "H" level, each bit line is recovered even after writing is completed, that is, charged to "H" level. It will not be done.

When the pre-writing is completed, the column gates 18 and 20 for writing are controlled to be closed before the recovery of the data signal line is performed by the recovery signal. This control is performed by setting the timing of lowering the data write control signal (internal write enable signal) write to "L" level earlier than the timing of raising the recovery signal to "H" level. As a result, the control of (4) is performed, and the potentials of the data signal lines Din and / Din both return to the “H” level.
At this time, all the column gates 18 for writing have already been
Since 20 is closed, the bit line pair will not be recovered. That is, the bit line pair is not subjected to the recovery via the write column gate described above. Therefore, the potential of the bit line once selected and attained the write level is not recovered.

In FIG. 5, CSi indicates an output signal of the OR circuit 25 for controlling the write column gates 18 and 20. After the CSi falls to the "L" level first, the data signal lines Din, / Din has been recovered.

On the other hand, the test control signal test1 is set to "H".
Therefore, the test dummy word line DWL is in a selected state, and all the dummy cells 16 connected between the dummy word line DWL and each bit line pair are selected. When in the selected state, each of these dummy cells 1
Numeral 6 functions as a latch for holding the write data for the corresponding bit line pair, so that the already written column is in a state where the write data is held. Then, charge is discharged to the write level for each column in the order in which the write is performed, and in the state where the pre-write has been completed over all the addresses, all the bit line pairs are set in the stress applied state. The level to be set is set in advance. Therefore, there is no need to discharge the bit line potential at the start of the stress test, and there is no peak current which has conventionally been a problem.

Subsequently, the value of the power supply voltage is raised from the normal value, and the stress is actually started to be applied to the cell by setting the word line to the selected state. For this purpose, the test mode 2 is set by external control. And the test control signal t
est2 is set to the “H” level for a predetermined period. At this time,
The address is arbitrary (indicated by X in FIG. 4). When the test control signal test2 is at the "H" level, in the circuit shown in FIG. 2, the internal row addresses Ai and / Ai are both at the "H" level regardless of the external row address, and all rows are selected. Similarly, in the circuit shown in FIG. 3, the internal column address A
Both j and / Aj are at "L" level, and all columns are in a non-selected state.

When the write operation is started in this state, all the word lines are selected and all the cells 11 are selected. As for the bit lines, all the column gates are in the non-selected state, but the potentials of all the bit line pairs are originally set to the same data write state, and the same data is written to all the selected cells. Therefore, the flip-flops of the total size of all cells on the column hold the bit line potential, and the potential of the bit line pair is strongly fixed to the write potential. In other words, from the viewpoint of one cell, the flip-flop of the total size of all the other cells on the same column receives a fixed stress, and all the cells stress each other. Become.

Therefore, it is not necessary to transfer the data on the data signal line to the bit line pair by the write operation as in the related art. Then, the stress operation is completed by terminating the write operation and deselecting the word line.

Next, the process exits from the test mode 2, returns to the state of only the test mode 1, and executes the pre-writing. In this case, data reverse to the above, that is, "1" data is written for each address in the same sequence as above,
After the end of the pre-writing, the stress is applied again in the test mode 2. As a result, a full stress test can be performed on the inverse data.

When the application of the reverse data stress is completed, the column is still in a state where the write potential of the reverse data is held. That is, if the test mode 1 is exited here, the bit line load is turned on, all bit line pairs are recovered at the same time, and a large peak current is generated. Therefore, next, the read operation is performed over all the columns in the test mode 1 state. The inside is in a read operation state, and a recovery signal is supplied to the OR circuit 29, so that the data signal line pair Din, /
Din both enter the recovery state ("H" level). Here, originally, the column gates 19 and 21 for reading are selected as the column gates according to the column address, and the bit line pair is connected to the corresponding sense amplifier 22 for each column. By the control of (3) described above, the column gates 18 and 20 for writing are controlled to be selectively turned on. Thus, the column selected according to the column address is connected to the data signal line pair Din, / Din in the recovery state, and the bit line pair is recovered. Therefore, by scanning the columns according to the column addresses, it is possible to sequentially perform recovery for each column, and after scanning all the columns, all the columns return to the recovery state. Thereafter, even if the process exits from the test mode 1 and returns to the normal state, the bit line pair is not collectively recovered, and no peak current is generated. Therefore, at the start and end of stress application, the problem of peak current generation due to collective discharge and collective charge of columns is avoided.

After returning to the normal operation, one transistor 13 used as a bit line load is always turned on to charge the corresponding bit line, and the other transistor 14 is used when a recovery pulse signal is input. Only turns on to recover the corresponding bit line.

In the above embodiment, the case where the above-mentioned two P-channel type MOS transistors 13 and 14 are used as the bit line load has been described. Instead of these two transistors, FIG. A flip-flop 133 as shown may be used. However, in this case, the potential of each bit line pair is held by the flip-flop 133 at the time of pre-writing in the previous burn-in test, so that the dummy word line DW
L, the buffer circuit 17 and the dummy cell 16 can be omitted. When these are omitted, the control of the above (2), that is, the test dummy word line D
The control for setting the WL to the selected state is, of course, unnecessary, and by performing the above-described controls (1), (2), and (4) during the operation in the test mode 1, generation of the peak current due to the batch charging and discharging of the columns. Avoidance becomes possible.

Next, a second embodiment of the present invention will be described. In the first embodiment, the case where attention is paid only to the charge / discharge current of the column and the word line is simultaneously selected at the time of applying the stress to perform the writing operation has been described.
In the second embodiment, generation of a peak current due to a batch charge / discharge current in a row decoder is avoided.

FIG. 6 shows a circuit configuration of a row decoder part of the SRAM according to the second embodiment. n A
The ND circuits 51 constitute a predecoder 52. Each of the AND circuits 51 has an internal row address add composed of a plurality of bits and n control signals S1 to Sn.
And any one of the control signals is input. The n control signals S1 to Sn are generated by a control signal generation circuit described later, and in the test mode, the signals S1 to Sn are generated.
1 to Sn are such that the timings of rising to “H” level are temporally shifted, and the periods during which they are at “H” level are substantially equal. The predecode signal output from the n AND circuits 51 is the same as the other m predecode signals (not shown) and l
Together with the predecode signals, the signals are inputted to a total of (n × m × 1) AND circuits 54 constituting the main decoder 53. The outputs of the (n × m × l) AND circuits 54 are supplied to the corresponding number of word lines.

Here, each of the predecode signals output from the n AND circuits 51 to which the signals S1 to Sn are input, respectively, is given by (m × x) in the main decoder 53.
l) The signals are input to the AND circuits 54 in parallel, and all the rows (all the word lines) are divided into 1 / n.

FIG. 7 shows a configuration of a control signal generation circuit for generating the control signals S1 to Sn. AND circuit 6
1 receives a data write control signal (internal write enable signal) write and a test control signal test2. The output of the AND circuit 61 is input to one input terminal of the AND circuit 62 and to the delay circuit 63. The output of the delay circuit 63 is inverted and input to the other input terminal of the AND circuit 62. The AND circuit 62
And the delay circuit 63 constitute a pulse generation circuit for generating an "H" level pulse signal having a predetermined pulse width in synchronization with the rise of the output of the AND circuit 61. The pulse signal generated here is a trigger. Output as signal trig. The trigger signal trig is output from the inverter 6
4 and output as an inverted trigger signal / trig.

Further, the test control signal test 2 is input to one input terminal of the NOR circuit 65 and to the delay circuit 66. The output of the delay circuit 66 is inverted and input to the other input terminal of the NOR circuit 65. The NOR circuit 65 and the delay circuit 66 constitute a pulse generation circuit that generates an "H" level pulse signal having a predetermined pulse width in synchronization with the fall of the test control signal test2.

Two NOR circuits 67 each having two inputs,
Reference numeral 68 denotes a flip-flop 69 in which one input terminal and an output terminal are cross-connected so that each output becomes the other input, and the trigger signal trig is provided as the other input of the NOR circuit 67. The output of the NOR circuit 65 is input as the other input of the NOR circuit 68.

70-1, 70-2, 70-3,... 70-
n is a signal delay circuit, respectively, and these n signal delay circuits are connected in series. All of the n signal delay circuits have the same circuit configuration. As illustrated in the signal delay circuit 70-1, an inverter 71 receiving an input signal, an output node of the inverter 71 and a ground voltage. Between the supply node and the trigger signal tr
an N-channel MOS transistor 72 whose gate is controlled by ig, and a capacitor 73 inserted between an output node of the inverter 71 and a supply node of the power supply voltage Vcc.
A capacitor 74 inserted between an output node of the inverter 71 and a ground voltage supply node; an inverter 75 to which a signal of the output node of the inverter 71 is input; V
and a P-channel MOS transistor 76 which is inserted between the cc supply node and the gate of which is controlled by the inverted trigger signal / trig.

The output S0 of the inverter INV for inverting the output from the flip-flop 69 is supplied as an input signal to the first-stage signal delay circuit 70-1. The output of the first-stage signal delay circuit 70-1 is The control signal S1 is supplied to the signal delay circuit 70-2 of the next stage as an input signal and inverted by the inverter 80 to generate the control signal S1. The output of the next-stage signal delay circuit 70-2 is further supplied to the next-stage signal delay circuit 70-3 as an input signal and inverted by the inverter 80 to generate the control signal S2. Hereinafter, similarly, the output of the preceding signal delay circuit is supplied to the next signal delay circuit as an input signal and is inverted by the inverter 80 to generate the control signal Si (i = 1 to n).

Next, the operation of the row decoder of FIG. 6 including the control signal generating circuit having the structure shown in FIG. 7 will be described with reference to the timing chart of FIG.

First, the test control signal test2 is set to "H".
After rising to the level, the data write control signal wr
Item rises to “H” level. This signal writ
e, the rising of “e” is detected, and “H”
A level trigger signal trig is output. At this time,
The flip-flop 69 is set and its output is "H".
Level, and the output S0 of the inverter that inverts the level becomes “L” level. In addition, it is assumed that all of the control signals S1 to Sn are at “H” level in advance. When the trigger signal trig goes high in this state, the transistors 72 and 76 in each of the signal delay circuits 70-1 to 70-n are turned on, the input node of each inverter 75 goes low and the output is low. The node is set to “H” level. As a result, all the outputs from the signal delay circuits are at the "H" level, and the output of each inverter 80 for inverting the output of each signal delay circuit is also at the "L" level.

On the other hand, the "L" level at the input node of the inverter 75 in the signal delay circuit 70-1 changes the trigger signal trig from the "H" level to the "L" level, and the transistor 72 is turned off. After that, it is held for a while by the capacitors 73 and 74 connected to the node, but after a certain time elapses,
The battery is charged by the output of the inverter 71, and after a predetermined time, the output of the inverter 75 is inverted to the “L” level.
Therefore, first, the control signal S1, which is the output of the inverter 80 to which the output of the signal delay circuit 70-1 is input, is set to "L".
The level is inverted from the “H” level. After the output of the signal delay circuit 70-1 is inverted to the "L" level, the output of the inverter 71 in the signal delay circuit 70-2 at the next stage is inverted to the "H" level. The output of inverter 75 in signal delay circuit 70-2 is inverted to "L" level. As a result, the control signal S2, which is the output of the inverter 80 to which the output of the signal delay circuit 70-2 is input, is inverted from "L" level to "H" level. Hereinafter, similarly, the control signals S3 to Sn sequentially rise from the "L" level to the "H" level.

Here, all the signal delay circuits 70-1 to 70-7
0-n has an equivalent circuit configuration, and if the values of the elements and the values of the capacitors and the like are substantially equal, the control signal generated by the signal delay circuit of the preceding stage and the signal of the next stage are used. The delay times between the control signal generated by the delay circuit and the control signal are all equal.

Next, when the test control signal test2 falls from the "H" level to the "L" level, this falling is detected, and the "H" level pulse signal is output from the NOR circuit 65. Thereby, the flip-flop 69
Is reset, its output is inverted to "L" level, and the signal S0 output from the inverter INV is also inverted to "H" level. The signal S0 is sequentially delayed by each signal delay circuit in the same manner as described above, and the control signal S0
1 to Sn sequentially fall from the “H” level to the “L” level.

In each signal delay circuit, one end of the capacitor 7 connected to the supply node of the power supply voltage Vcc is provided.
3 serves to delay the time when the input node of the inverter 75 is inverted from the “H” level to the “L” level, and the capacitor 74 having one end connected to the ground voltage supply node is connected to the input node of the inverter 75. Works to delay the inversion from "L" level to "H" level.

As described above, from the control signal generation circuit of FIG. 7, n control signals S1 to Sn whose rising timings are sequentially shifted in time and in which the "H" level periods are substantially equal are obtained. Is output. Since each of such control signals S1 to Sn is input to the same number of AND circuits 54 in the main decoder 53 via the predecoder 52 shown in FIG. 6, as shown in FIG. Lines, that is, (n × m × l) word lines are 1 / n
The word lines (WL (1 / n)) having these (m × l) lines as one unit are simultaneously selected and driven for each unit, and are simultaneously brought into a non-selected state.

Therefore, the unit by which the word lines are collectively selected is 1 / n of the whole, and the peak current flowing when driving the word lines is also reduced to 1 / n. Further, the application of stress is started in a unit in which the word line is selected.

Next, the end of stress application will be considered. Before terminating the writing mode in which the stress is applied, the mode exits from the test mode 2 and returns to the state of only the test mode 1. Here, in the case of the synchronous type SRAM, since the address fetched at the start of the operation is held in the register, the state of the row address all selection is held even after exiting from the test mode 2.

On the other hand, when the word line is deselected,
In order that the unit to be deselected becomes 1 / n of the whole, and the word lines sequentially selected at the start of the stress application transition to the non-selection state in the same order with the same delay at the end of the stress application. , 1 / n, the times in the selected state are all substantially the same, so that there is no difference in the stress time condition for all the word lines.

During normal operation, the control signals S1 to S
Since n is all at “H” level, it has no effect on the decode signal.

As described above, the peak current due to charging and discharging when the word line is selected or not selected can be reduced to 1 / n. As a result, when arranging a large number of chips in a rack and driving them in parallel with one tester at the same time, the number of chips that can be tested at the same time can be increased compared to the conventional case, and the test cost for performing burn-in test increases. Can be prevented.

Here, as shown in FIG. 6, extra wiring for inputting control signals S1 to Sn to AND circuit 51 in the row decoder is required.
Decoder non-selection due to redundancy and word line non-selection control after data sensing are generally performed in the row decoder. If shared with the wiring used for these controls, logic is added to the critical path. Can be avoided, and the addition of this function does not cause deterioration in speed characteristics.

Further, these controls are performed by so-called late
In the case of the write specification, a cycle in which an address input is reflected in a cell or a cycle in which an internal write control signal is activated is shifted, so that it is needless to say that the same operation can be performed as long as cycle consistency is taken into consideration.

Instead of selecting all of the word lines at once as in the second embodiment, the first method is to shift the time by a certain unit and to select them sequentially for the same time. The embodiment may be performed when a column is selected.

[0089]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of preventing an increase in test cost when performing a burn-in test.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment when a semiconductor memory device according to the present invention is implemented in an SRAM.

FIG. 2 is a circuit diagram showing a configuration of a pad to which an external row address is input and an input first-stage circuit according to the first embodiment;

FIG. 3 is a circuit diagram showing a configuration of a pad to which an external column address is input and an input first-stage circuit according to the first embodiment;

FIG. 4 is a timing chart showing an example of the operation of the SRAM according to the first embodiment.

FIG. 5 is a timing chart showing an example of the operation of the SRAM according to the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a portion of a row decoder of an SRAM according to a second embodiment;

FIG. 7 is a circuit diagram of a control signal generation circuit that generates a control signal used in the circuit of FIG. 6;

8 is a timing chart showing an example of the operation of the row decoder of FIG. 6 including the control signal generation circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a configuration of a part of an address buffer circuit and a row decoder in a conventional semiconductor memory device performing simultaneous selection of all cells.

FIG. 10 is a circuit diagram showing a configuration of a part of a conventional semiconductor memory device.

FIG. 11 is a circuit diagram of a 6-transistor cell used as a memory cell in the related art and the present invention.

FIG. 12 is a circuit diagram illustrating an example of a bit line load circuit.

FIG. 13 is a circuit diagram showing an example of a bit line load circuit different from FIG. 12;

FIG. 14 is a circuit diagram showing an example of a bit line load circuit different from FIGS. 12 and 13;

[Explanation of symbols]

 11: cell (SRAM cell), 12: row decoder, 13, 14: P-channel MOS transistor, 15: OR circuit, 16: dummy cell, 17: buffer circuit, 18, 20: column gate for writing, 19, 21: Column gate for reading, 22: Sense amplifier, 23: AND circuit, 24, 25, 28, 29: OR circuit, 26: NOR circuit, 27: NAND circuit, WL0 to WLn: Word line, BL0, / BL0 ~ BLm, / BLm ... bit line pair, DWL ... dummy word line, Din, / Din ... data signal line pair, 31, 41 ... pad, 32, 42 ... buffer circuit, 33, 34, 43, 44 ... NAND circuit, 51, 54: AND circuit, 52: Predecoder, 53: Main decoder, 61, 62: AND circuit, 63, 66 Delay circuit, 64 inverter, 65 NOR circuit, 69 flip-flop, 70-1 to 70-n signal delay circuit, 71, 75, 80 inverter, 72 N-channel MOS transistor, 73, 74 capacitor , 76 ... P-channel MOS transistor.

Claims (14)

[Claims] 1. A word line and bit line pair, a static cell connected to the word line and bit line pair, a load transistor conducting in a normal operation state to charge the bit line pair, and a test mode. Test mode setting means for setting; load control means for controlling the load transistor to be in a non-conductive state in the test mode; a dummy word line to be selected in the test mode; A static semiconductor memory device, comprising: a dummy cell connected to a bit line pair and having a configuration equivalent to the static cell. 2. A write data signal line pair; a first column gate pair for selectively connecting the bit line pair to the write data signal line pair in accordance with an address; a sense amplifier having a pair of input nodes; A second column gate pair for selectively connecting the bit line pair to a pair of input nodes of the sense amplifier in accordance with the following: and deactivating the second column gate pair during a data read operation in the test mode. 2. The static semiconductor memory device according to claim 1, further comprising control means for controlling said first column gate pair to an active state. 3. A recovery means for recovering the potential of the write data signal line pair after the first column gate pair has transitioned from an active state to an inactive state at the end of a data read operation in the test mode. 3. The static semiconductor memory device according to claim 2, further comprising: 4. A word line and bit line pair, a static cell connected to the word line and bit line pair, and a bit line load that conducts during a period after a write operation is completed to charge the bit line pair. Circuit, test mode setting means for setting a test mode, load control means for controlling the bit line load circuit to be in a non-conductive state in the test mode, and a dummy word line to be selected in the test mode And a dummy cell connected to the dummy word line and the bit line pair and having a configuration equivalent to the static cell. 5. A write data signal line pair, a first column gate pair for selectively connecting the bit line pair to the write data signal line pair according to an address, a sense amplifier having a pair of input nodes, A second column gate pair for selectively connecting the bit line pair to a pair of input nodes of the sense amplifier in accordance with the following: and deactivating the second column gate pair during a data read operation in the test mode. 5. The static semiconductor memory device according to claim 4, further comprising control means for controlling said first column gate pair to an active state. 6. A recovery means for recovering the potential of the write data signal line pair after the first column gate pair transitions from an active state to an inactive state at the end of a data read operation in the test mode. 6. The static semiconductor memory device according to claim 5, further comprising: 7. A bit line pair, a flip-flop circuit connected to each bit line of the bit line pair so as to hold the potential of the bit line pair, and conducting in a normal operation state to connect the bit line pair. A static semiconductor memory comprising: a load transistor to be charged; test mode setting means for setting a test mode; and load control means for controlling the load transistor to be in a non-conductive state in the test mode. apparatus. 8. A write data signal line pair, a first column gate pair for selectively connecting the bit line pair to the write data signal line pair according to an address, a sense amplifier having a pair of input nodes, A second column gate pair for selectively connecting the bit line pair to a pair of input nodes of the sense amplifier in accordance with the following: and deactivating the second column gate pair during a data read operation in the test mode. 8. The static semiconductor memory device according to claim 7, further comprising control means for controlling said first column gate pair to an active state. 9. A recovery means for recovering the potential of the write data signal line pair after the first column gate pair transitions from an active state to an inactive state at the end of a data read operation in the test mode. 9. The static semiconductor memory device according to claim 8, further comprising: 10. A plurality of word lines, test mode setting means for setting a test mode, row address control means for setting a row address to an all-selected state in the test mode, and a row address in the test mode regardless of the row address. A word line selecting means for starting a selecting operation for each of the plurality of word lines at different timings and setting the selected state for a substantially equal period of time. Semiconductor storage device. 11. The static semiconductor memory device according to claim 10, further comprising column address control means for setting a column address to a fully selected state in said test mode. 12. A semiconductor memory device having a test mode in which a plurality of word lines are all set to a selected state, wherein the plurality of word lines are divided into certain units, and the word lines are divided into the divided units. A semiconductor memory device comprising selection control means for setting all of the plurality of word lines to a selected state by changing timings for transition to a selected state. 13. A semiconductor memory device having a test mode for setting all of a plurality of bit lines to a selected state, wherein the plurality of bit lines are divided into certain units, and the bit lines are divided into the divided units. A semiconductor memory device comprising selection control means for setting all of the plurality of bit lines to a selected state by making different timings for transition to a selected state. 14. A semiconductor memory device having a test mode in which a plurality of word lines and a plurality of bit lines are all set to a selected state and all of a plurality of memory cells are simultaneously selected. Selection control means for setting all of the plurality of memory cells to the selected state by differentiating the memory cells into the selected state by dividing the memory cells into the selected state for each of the divided units. Semiconductor storage device.