JP2013210961A - Cache memory device, method of controlling cache memory, and information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that it takes a long time to complete all the responses to a plurality of access requests.SOLUTION: A cache memory device 100 includes: a plurality of tag memories 121 to 12n; a plurality of data memories 131 to 13n corresponding to each tag memory; and a controller unit 110 that performs cache hit determination to the plurality of tag memories 121 to 12n for a first access request AR and in the course of access processing to any of the plurality of data memories based on a second access request, initiates access processing to the data memory when the data memory corresponding to the tag memory identified in a cache hit in the first access request AR is not in the course of access processing based on the second access request.

Description

  The present invention relates to a cache memory device, a cache memory control method, and an information processing device. For example, the present invention relates to a cache memory device, a cache memory control method, and an information processing device for processing a plurality of access requests.

  The speed improvement of the external memory is limited to the speed improvement of the processor. Therefore, a technique for improving memory latency and throughput of the entire system by providing a cache memory between the processor and the external memory is used.

  Here, the cache memory is generally hierarchized into a plurality of layers from the relationship between response speed and cost (capacity). In other words, the primary cache of the highest hierarchy is limited in capacity for maintaining high speed and power consumption instead of enabling high speed access. Therefore, the primary cache is often used as a private cache of an IP core (Intellectual Property Core) that plays the role of a processor.

  On the other hand, after the secondary cache, the access speed is relatively slow instead of securing the capacity compared to the primary cache. Therefore, after the secondary cache, it is often used as a shared cache memory shared by a plurality of IP cores. Here, the shared cache memory needs to respond to a plurality of access requests. For this purpose, for example, techniques such as multi-bank and multi-port can be cited.

  Non-Patent Document 1 discloses a technique related to multibank. The L2 cache memory according to Non-Patent Document 1 is an instruction or data cache, and is physically divided into 8 banks. The L2 cache memory is logically shared among all CPUs. The L2 cache memory is interleaved using lower bits of the physical address (64 bytes) of the cache line.

  Patent Document 1 discloses a technique related to multiport. The multi-port cache memory according to Patent Document 1 has a plurality of input / output ports for each memory cell. For this reason, even if a plurality of access requests are generated for the same cache memory, a plurality of memory cells can be processed in parallel.

JP 2006-139401 A

Luiz Andre Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese, "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing", International Symposium of Comupter Architecture 2000, pp 282-293

  However, Non-Patent Document 1 has a problem that it may take a long time to complete all responses to a plurality of access requests. This is because when access addresses of a plurality of access requests indicate the same bank (so-called bank conflict), the access requests cannot be processed in parallel. Therefore, it may be necessary to tune a program to be executed in parallel to reduce bank contention.

  Note that the multi-port cache memory according to Patent Document 1 is intended for a primary cache. In general, the multi-port memory has a large area cost and is not suitable for a cache memory whose capacity is important like a cache memory after the secondary cache. Therefore, in patent document 1, the subject mentioned above cannot be solved.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the cache memory device performs a cache hit determination on a plurality of tag memories in response to the first access request, and accesses any one of the plurality of data memories based on the second access request. During processing, if the data memory corresponding to the tag memory specified at the time of the cache hit in the first access request is not being accessed based on the second access request, the data memory is accessed. Start processing.

  Further, according to another embodiment, the cache memory device may perform second data other than the first access request during data access to any of the plurality of ways based on the first access request to the associative cache memory. If the way specified by the cache hit in the access request is not being accessed based on the first access request, data access to the specified way is started.

  Furthermore, according to another embodiment, the cache memory control method specifies a tag memory that has a cache hit based on the first access request, and a plurality of cache memory control methods based on second access requests other than the first access request. The data memory corresponding to the identified tag memory in the first access request is being accessed based on the second access request other than the first access request. It is determined whether or not there is an access process, and when it is determined that the access process is not in progress, the access process is started based on the first access request.

  Further, according to another embodiment, the information processing apparatus performs cache hit determination to a plurality of tag memories in response to a first access request from any of a plurality of processor cores, and performs the first access During access processing to any of the plurality of data memories based on a second access request different from the request, a data memory corresponding to a tag memory specified at the time of a cache hit in the first access request, When access processing is not being performed based on the second access request, access processing to the data memory is started.

  According to the one embodiment, it is possible to shorten the time until all responses to a plurality of access requests are completed.

1 is a block diagram illustrating a configuration of a cache memory device according to a first embodiment; 3 is a flowchart showing a flow of control processing of the cache memory device according to the first embodiment; FIG. 3 is a block diagram illustrating a configuration of a multiprocessor system according to a second embodiment. 10 is a flowchart showing a flow of control processing of the cache memory device according to the second embodiment; 6 is a timing chart for explaining the operation of the cache memory device according to the second embodiment; 6 is a timing chart for explaining the operation of the cache memory device according to the second embodiment; 6 is a timing chart for explaining the operation of the cache memory device according to the second embodiment; 14 is a flowchart showing a flow of control processing of the cache memory device according to the third embodiment; It is a block diagram which shows the structure of the information processing apparatus concerning this Embodiment 6. It is a block diagram which shows the structure of the processor system by the multibank concerning related technology.

  Hereinafter, specific embodiments to which means for solving the above-described problems are applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1>
FIG. 1 is a block diagram illustrating a configuration of the cache memory device 100 according to the first embodiment. The cache memory device 100 accepts a plurality of access requests AR and partially performs parallel processing of data transfer DT as a response to each request source. Note that the response to the access request includes access processing to the data memory such as write processing in addition to data transfer. The cache memory device 100 includes a control unit 110, a tag memory group 120, and a data memory group 130.

  The tag memory group 120 includes a plurality of tag memories 121 to 12n. The data memory group 130 includes a plurality of data memories 131 to 13n. Here, the tag memories 121 to 12n and the data memories 131 to 13n correspond to each other. For example, the tag memory 121 and the data memory 131 correspond, and this correspondence is defined as way W1. Similarly, the correspondence relationship between the tag memory 122 and the data memory 132 is the way W2, and the correspondence relationship between the tag memory 12n and the data memory 13n is the way Wn. The tag memories 121 to 12n and the data memories 131 to 13n are different memory modules. As the memory module, for example, an SRAM (Static Random Access Memory) can be adopted. Therefore, the cache memory determination access can be made in parallel to the tag memories 121 to 12n. The data memories 131 to 13n can perform data access processing in parallel. For example, data can be transferred from the data memory 131 and the data memory 132 in parallel.

  The control unit 110 performs cache hit determination on the plurality of tag memories 121 to 12n in response to the first access request AR. Then, the control unit 110 determines whether the data memory corresponding to the tag memory specified at the time of the cache hit in the first access request AR is in the process of accessing any of the plurality of data memories based on the second access request. When access processing is not being performed based on the second access request, access processing to the data memory is started. That is, the control unit 110 determines whether the way in which the access request AR hits the cache hit and the way in which another access request hits the cache hit are different, and if the way is different, the control unit 110 performs the data access process to the way. Start. Further, it is assumed that other access requests are received prior to the access request AR. In particular, the control unit 110 performs burst transfer of data read from the data memory to the request source of the access request AR as an access process.

  As a result, data transfer of a plurality of access requests can be partially processed in parallel, so that the data transfer processing time can be shortened as a whole.

  FIG. 2 is a flowchart showing a flow of control processing of the cache memory device 100 according to the first embodiment. First, the control unit 110 determines whether or not the received access request AR is a cache hit (S101). If it is determined in step S101 that the cache hit has occurred, the control unit 110 identifies the hit way (S102). That is, the control unit 110 specifies a tag memory that has a cache hit based on the first access request.

  Here, it is assumed that, at this time, an access process for any one of the data memories in the data memory group 130 is being executed based on at least the access request that has been received in advance or simultaneously by the access request AR. At this time, the control unit 110 determines whether or not the data memory associated with the identified way is being accessed (S103).

  If it is determined in step S103 that the access process is being performed, the control unit 110 waits for an access process based on the access request AR (S104). Then, after a predetermined time, step S103 is executed again. If it is determined in step S103 that access processing is not being performed, the control unit 110 starts access processing based on the access request AR (S105). For example, even if the data memory 132 is being accessed based on the second access request other than the first access request, the data memory 131 corresponding to the tag memory identified in step S102 is not in the second access request. Since the access process is not being executed based on the first access request, the access process is started based on the first access request. If the access process based on the second access request is completed during the standby in step S104, it is determined in step S103 that the access process is not in progress.

  If it is determined in step S101 that there is a cache miss, the control unit 110 loads the corresponding data (S106).

  Therefore, for example, when a subsequent access request is received during data transfer from an arbitrary data memory based on the preceding access request, the cache memory device 100 determines that the data memory specified as the access target of the subsequent access request is If data transfer is not in progress based on the preceding access request, data transfer of the subsequent access request is started. Therefore, data transfer based on the preceding access request and the subsequent access request is partially executed in parallel. Therefore, the entire data transfer time can be shortened as compared with the case where sequential processing is performed in which the data transfer of the preceding access request is completed.

  The cache memory device 100 according to the first embodiment can be rephrased as follows. That is, the cache memory device is specified by a cache hit in the second access request other than the first access request during data access to any of the plurality of ways based on the first access request to the associative cache memory. If the way is not accessing data based on the first access request, data access to the specified way is started.

  As described above, the first embodiment can be realized, for example, by expanding a set associative cache having a normal plurality of ways. That is, the cache tag searches sequentially, and the result allows data access in parallel if the way is not being accessed. In other words, if the way to be accessed is different, the access processing is not in progress, so that parallel access is possible from different initiators, and the throughput is improved. This is particularly effective when the access cycle to the data array becomes longer than the tag pulling cycle due to burst transfer.

  As described above, the shared cache memory needs to respond to access requests from a plurality of IP cores. For this reason, when an application with a low private cache hit rate is executed, the shared cache memory becomes an access bottleneck, which may limit the performance.

  Subsequently, the problem in Non-Patent Document 1 and the solution and effect of the problem according to the first embodiment will be described in detail. The shared cache memory has a cache neck as described above, but the multi-bank cache memory described above is often used. In the multi-bank method, a specific bit of an address is assigned as an identification bit, and the corresponding cache memory is determined by the identification bit from a plurality of cache memories and accessed. Thereby, access requests from different IP cores can be permitted for cache memories having different identification bits (bank addresses).

FIG. 10 is a block diagram illustrating a configuration of a multi-bank processor system according to Non-Patent Document 1. The L2 cache memories L2 _{0 to} L2 ₇ are instruction or data caches, and are physically divided into 8 banks. Further, the L2 cache memories L2 _{0 to} L2 ₇ are logically shared among all CPUs. The L2 cache memories L2 _{0 to} L2 ₇ are interleaved using the lower bits of the physical address (64 bytes) of the cache line. This is described in Non-Patent Document 1, pp285, lines 15-17 on the left side as "The L2 banks are interleaved using the lower address bits of a cache line's physical address (64-byte line)." It is clear from

  Therefore, in Non-Patent Document 1, for example, when two access requests access one L2 cache memory (bank), a cache hit determination is performed by one access request. Read the corresponding data from the memory and transfer the data to the request source. Then, after the data transfer is completed, processing such as hit determination for the other access request is started. That is, in the case of bank contention, access requests must be processed sequentially, and as a result, the time until all responses to a plurality of access requests are completed becomes long.

  In addition, in the multi-bank system as in Non-Patent Document 1, the cache memory to be uniquely accessed can be determined by the address, so that the configuration becomes easy. However, there are the following three main issues. The first is that control logic such as determination of a plurality of cache hit misses is necessary. Second, tuning to distribute bank addresses is necessary. This is because when the bank addresses are not distributed, accesses are concentrated only on a specific bank of the cache memory. Third, it is difficult to cope with an increase or decrease in cache capacity due to power-off, etc., against an access load on the cache memory.

  Therefore, it is conceivable to use a set associative method in which one bank is managed by a plurality of ways. In the set associative method, data at a certain address can be stored in one of a plurality of cache entries, that is, ways. However, in the set associative method, when a cache hit occurs for a certain access request, the processing for another access request cannot proceed until the data transfer in the hit way is completed. That is, it does not support parallel access requests.

  Here, since such a shared cache memory is mainly accessed through a higher-level private cache, burst transfer in which a plurality of data is transferred in several cycles is mostly performed. Here, in single data transfer, it is necessary to compare cache tags for each transfer. On the other hand, in burst transfer, it is only necessary to compare cache tags at the start of transfer. That is, in the burst transfer, the cache tags are compared in the first cycle, and when the cache hits, the data stored in the data memory is burst transferred in a plurality of cycles. As described above, hit miss determination for the cache tag is possible in one cycle, but hit miss determination for other access requests is kept waiting even during the cycle between burst transfers.

  Therefore, in the first embodiment, a plurality of cache entry candidates, that is, ways, are accessed in parallel after the cache tag is accessed. That is, the first embodiment is a cache memory device that performs access to a tag memory in series and accesses data memory in parallel in response to a plurality of access requests. Thereby, throughput can be improved, and throughput comparable to the multi-bank method can be achieved. In addition, problems such as the tuning cost, capacity increase / decrease, and logical amount of the multi-bank cache can be solved.

<Embodiment 2>
The second embodiment is a specific example of the first embodiment described above, and arbitrates access requests when a plurality of access requests are received simultaneously.

  FIG. 3 is a block diagram showing a configuration of the multiprocessor system 200 according to the second embodiment. The multiprocessor system 200 includes IP cores 211 to 214, L1 caches 221 to 224, a cache memory device 230, and an SDRAM (Synchronous Dynamic Random Access Memory) 240. That is, the multiprocessor system 200 includes hierarchical memories of L1 caches 221 to 224, a cache memory device 230 that is an L2 cache, and a lower layer SDRAM 240.

  The IP cores 211 to 214 make access requests for reading and writing data to the hierarchical memory. The IP cores 211 to 214 include L1 caches 221 to 224, respectively. In the case of an L1 cache miss, the IP cores 211 to 214 issue an access request to the arbiter scheduler 231 via the access request bus B20. The number of IP cores is not limited to this.

  The arbiter scheduler 231 receives a plurality of access requests, performs arbitration, and issues access requests one by one to the L2HIT / MISS determination unit 232. It should be noted that any known algorithm or the like for realizing the arbitration may be employed. The L2HIT / MISS determination unit 232 performs cache hit determination for the WAY 0 tag 2330 and the WAY 1 tag 2331 in response to the access request.

  The WAY 0 data array 2350 and the WAY 1 data array 2351 are data memories that are configured by independent SRAMs and store data corresponding to some addresses in the SDRAM 240 for each line. Note that data corresponding to the same address in the SDRAM 240 can be stored in either the WAY 0 data array 2350 or the WAY 1 data array 2351.

  The WAY 0 access status flag 2340 is access status information indicating whether or not the WAY 0 data array 2350 is performing read or write access processing. Similarly, the WAY 1 access state flag 2341 is access state information indicating whether or not the WAY 1 data array 2351 is performing a read or write access process. The WAY 0 access state flag 2340 and the WAY 1 access state flag 2341 are data that can be referred to at least by the L2HIT / MISS determination unit 232. For example, the WAY 0 access status flag 2340 is stored in the control area in the WAY 0 data array 2350, for example. Similarly, the WAY 1 access status flag 2341 is stored in the control area in the WAY 1 data array 2351. Alternatively, access state information may be stored as a management table in a storage area in the cache memory device 230. Here, the management table stores information indicating whether or not the data memory is being accessed.

  The access state flag may be a value indicating either “Free” or “Busy”. For example, “0” may be “Free”, “1” may be “Busy”, or other examples. Here, “Free” indicates “access not being processed”, and “Busy” indicates “access is being processed”. The L2HIT / MISS determination unit 232 updates the access state flag to “1” when locking the way, and updates the access state flag to “0” when unlocking the way.

  The WAY 0 tag 2330 is address information corresponding to each line of the WAY 0 data array 2350. Similarly, the WAY 1 tag 2331 is address information corresponding to each line of the WAY 1 data array 2351. Note that the WAY 0 tag 2330 and the WAY 1 tag 2331 may be realized by a single SRAM.

  The WAY 0 tag 2330, the WAY 0 access status flag 2340, and the WAY 0 data array 2350 are associated as WAY 0. Similarly, the WAY1 tag 2331, the WAY1 access state flag 2341, and the WAY1 data array 2351 are associated as WAY1. 3 illustrates a two-way cache memory device, the number of ways may be two or more.

  The SDRAM controller 236 controls access to the SDRAM 240 according to the access request determined as a cache miss by the L2HIT / MISS determination unit 232, transfers the response data to the request source, and transmits the response data to the WAY0 data array 2350. Alternatively, the data is loaded into the WAY 1 data array 2351.

  The SDRAM 240 is a main memory, and stores data including data not stored in the L1 caches 221 to 224, the WAY0 data array 2350, and the WAY1 data array 2351.

  The above-described L2HIT / MISS determination unit 232 is an example of the control unit 110. Therefore, when the control unit according to the second embodiment starts an access process based on an access request in the case of a cache hit, the control target data memory is being processed and the access process is completed. The access state information is updated assuming that the data memory targeted for access processing is not being processed. In other words, the control unit locks the data memory targeted for access processing for exclusive control at the start of the access processing. In addition, after the access process is completed, the control unit unlocks the data memory targeted for the access process. In addition, the control unit refers to the access state information for the data memory corresponding to the tag memory specified when the access request is a cache hit, and if the access state information is not being processed, Start the access process. In this way, by using the access state information, it is possible to easily confirm whether or not the access processing is being performed in units of data memory, that is, in units of ways, and exclusive control can be easily realized.

  The arbiter scheduler 231 described above is an arbitration unit that accepts a plurality of access requests and performs arbitration. When the data memory corresponding to the tag memory identified when the subsequent access request that has been arbitrated is a cache hit is in the process of access based on the previous access request that has been arbitrated, The subsequent access request is returned to the arbitration unit. In this way, by using the arbitration unit, even when a plurality of access requests are issued at the same time, the access processing is performed in the same manner as described above while performing hit miss determination of one request that is arbitrated in one cycle. , Partially parallel processing.

  FIG. 4 is a flowchart showing a flow of control processing of the cache memory device 230 according to the second embodiment. First, the arbiter scheduler 231 receives a plurality of access requests (S201). Next, the arbiter scheduler 231 arbitrates a plurality of access requests (S202). Then, the arbiter scheduler 231 selects an access request to be processed (S203). That is, the arbiter scheduler 231 notifies the L2HIT / MISS determination unit 232 of the access request determined as the highest priority by arbitration among the plurality of access requests. For example, when two access requests are received, an access request processed in advance by arbitration is set as the second access request described above, and an access request processed subsequent to the second access request by arbitration is set as described above. 1 access request.

  Then, the L2HIT / MISS determination unit 232 performs L2 cache hit miss determination (S204). That is, the L2HIT / MISS determination unit 232 determines whether or not the access request is a cache hit. Specifically, the L2HIT / MISS determination unit 232 compares the address included in the access request with the WAY0 tag 2330 and the WAY1 tag 2331 to determine whether or not they match. To do.

  If it is determined in step S204 that there is a cache hit, the L2HIT / MISS determination unit 232 determines whether or not the flag of the access target way is “Free” (S205). The L2HIT / MISS determination unit 232 makes the determination with reference to the access state information. For example, when WAY 0 has a cache hit, the L2HIT / MISS determination unit 232 determines “Free” if the WAY 0 access status flag 2340 is “0”, and determines “Busy” if “1”. To do. That is, the L2HIT / MISS determination unit 232 determines whether the data memory is in the access process depending on whether the data memory corresponding to the tag memory specified based on the first access request is locked. Determine whether or not.

  If it is determined in step S205 that the flag of the way to be accessed is not “Free”, that is, “Busy”, the access request is returned to the arbiter scheduler 231 and arbitration is performed again. That is, when the arbiter scheduler 231 determines that the data memory subject to the access process of the first access request is being accessed based on the second access request, the arbiter scheduler 231 reassigns the first access request to the arbitration target. And For example, if access processing has already been started for the same way due to a preceding access request, processing for the same SRAM cannot be performed, and access must be made after a predetermined time.

  If it is determined in step S205 that the flag of the access target way is “Free”, the L2HIT / MISS determination unit 232 updates the flag of the access target way to “Busy” (S206). That is, when the access process is started based on the access request, the L2HIT / MISS determination unit 232 locks the data memory targeted for the access process and sets the access process in progress. In other words, when the L2HIT / MISS determination unit 232 determines that the lock is not applied, the L2HIT / MISS determination unit 232 locks the data memory targeted for access processing of the first access request. As a result, it is possible to eliminate access processing for subsequent access requests for the way.

  For example, when there is no access request for which access processing is being performed in parallel, “Free” is used for any way. In addition, a remarkable case in the present embodiment is a case where an access process has already been started by another access request. At this time, the way accessed by another access request is “Busy”, but other ways can be accessed if they are “Free”. Therefore, in such a case, access processing can be executed in parallel for a plurality of access requests.

  Then, the L2HIT / MISS determination unit 232 starts access processing to the target data array (S207). For example, when the access request is a read command, data transfer is performed to the requesting IP core.

  After the data transfer is completed, the L2HIT / MISS determination unit 232 updates the target tag and updates the way flag to “Free” (S208). That is, the L2HIT / MISS determination unit 232 releases the lock of the data memory targeted for access processing after the access processing is completed, and assumes that the access processing is not in progress. As a result, subsequent access requests can be processed for the way.

  If it is determined in step S204 that there is a cache miss, the SDRAM controller 236 determines a load target way (S209). Then, the SDRAM controller 236 determines whether or not the flag of the way to be loaded is “Free” (S210). If it is determined in step S209 that the flag of the access target way is “Free”, the L2HIT / MISS determination unit 232 updates the flag of the load target way to “Busy” (S211). Thereafter, the SDRAM controller 236 loads data to the load target way (S212).

  FIG. 5 is a timing chart for explaining the operation of the cache memory device 230 according to the second embodiment. Here, an example is shown in which the access request X has WAY 0 as an access target, and the access request Y has WAY 1 as an access target.

  First, it is assumed that the cache memory device 230 simultaneously receives access requests X and Y from IP cores A and B, respectively (S201). Therefore, the arbiter scheduler 231 arbitrates the access requests X and Y (S202). At this time, it is assumed that the access request X is preceded by arbitration. Therefore, in the next cycle, the arbiter scheduler 231 selects the access request X as a processing target (S203).

  Subsequently, the L2HIT / MISS determination unit 232 performs a hit miss determination for the access request X (S204). That is, the L2HIT / MISS determination unit 232 performs hit miss determination on both the WAY 0 tag 2330 and the WAY 1 tag 2331. Here, it is assumed that a cache hit occurs in WAY 0 (YES in S204).

  Therefore, the L2HIT / MISS determination unit 232 determines whether or not the WAY 0 access state flag 2340 is “Free” (S205). Here, it is assumed that the WAY 0 access state flag 2340 is “Free”. Therefore, the L2HIT / MISS determination unit 232 updates the WAY 0 access status flag 2340 to “Busy” (S206), and starts an access process to the WAY 0 data array 2350 (S207). Here, it is assumed that the access request X is data reading. Therefore, D0, D1,... D15 are read from the WAY0 data array 2350 and transferred to the IP core A from the next cycle of hit / miss determination. In this example, 16 cycles are required for data transfer, but generally 2 or more cycles such as 32, 64 cycles, etc. are required depending on the amount of data per line.

  Simultaneously with the cycle of reading D0 from the WAY0 data array 2350, the arbiter scheduler 231 selects the subsequent access request Y as a processing target (S203), and the L2HIT / MISS determination unit 232 performs the hit miss determination of the access request Y. Perform (S204). Here, it is assumed that a cache hit occurs in WAY 1 (YES in S204).

  Therefore, the L2HIT / MISS determination unit 232 determines whether or not the WAY1 access state flag 2341 is “Free” (S205). Here, it is assumed that the WAY 1 access state flag 2341 is “Free”. Therefore, the L2HIT / MISS determination unit 232 updates the WAY1 access state flag 2341 to “Busy” (S206), and starts an access process to the WAY1 data array 2351 (S207). Here, it is assumed that the access request Y is data reading. Therefore, D0, D1,... D15 are read from the WAY1 data array 2351 from the next cycle of the hit miss determination, that is, the timing at which D1 is read from the WAY0 data array 2350, and the data is transferred to the IP core B. At this time, data transfer based on the access requests X and Y is partially processed in parallel.

  Thereafter, the L2HIT / MISS determination unit 232 updates the WAY 0 access state flag 2340 to “Free” by reading D15 from the WAY 0 data array 2350 (S208). Further, the L2HIT / MISS determination unit 232 updates the WAY1 access state flag 2341 to “Free” by reading D15 from the WAY1 data array 2351 (S208).

  In this way, in the example of FIG. 5, all data transfer can be completed with a difference of only one cycle with respect to the access requests X and Y issued simultaneously.

  FIG. 6 is a timing chart for explaining the operation of the cache memory device 230 according to the second embodiment. Here, an example is shown in which both access requests X and Y target WAY 0 as an access target. Hereinafter, the difference from FIG. 5 will be mainly described.

  First, D0 is read from the WAY0 data array 2350 as an access process based on the preceding access request X. Simultaneously with this cycle, the arbiter scheduler 231 selects the subsequent access request Y as a processing target (S203), and the L2HIT / MISS determination unit 232 performs hit miss determination of the access request Y (S204). Here, it is assumed again that a cache hit occurs in WAY 0 (YES in S204).

  Therefore, the L2HIT / MISS determination unit 232 determines whether or not the WAY 0 access state flag 2340 is “Free” (S205). Here, since the WAY 0 access status flag 2340 is “Busy” (NO in S205), the arbitration in the arbiter scheduler 231 is performed again for the access request Y. Thereafter, the L2HIT / MISS determination unit 232 updates the WAY 0 access state flag 2340 to “Free” by reading D15 from the WAY 0 data array 2350 (S208). Then, the access request Y can be accessed to WAY 0, and data transfer is started.

  In this way, simultaneous access to the same way can be appropriately eliminated by the access status flag, and the consistency of response data can be maintained.

  FIG. 7 is a timing chart for explaining the operation of the cache memory device 230 according to the second embodiment. Here, an example is shown in which both access requests X and Y have WAY 0 as an access target, and access request Z has WAY 1 as an access target. Hereinafter, the difference from FIGS. 5 and 6 will be mainly described.

  First, it is assumed that the cache memory device 230 simultaneously receives access requests X and Y from IP cores A and B, respectively (S201). Then, it is assumed that access request X is preceded by arbitration. Then, the L2HIT / MISS determination unit 232 performs a hit miss determination on the access request X, and assumes that a cache hit occurs in WAY 0 (YES in S204).

  At the same time, it is assumed that the cache memory device 230 has received an access request Z from the IP core C. At this time, the arbiter scheduler 231 arbitrates the access requests Y, Z, and Y (S202). At this time, it is assumed that the access request Y is preceded by arbitration. Therefore, in the next cycle, the arbiter scheduler 231 selects the access request Y as a processing target (S203).

  Subsequently, the L2HIT / MISS determination unit 232 performs hit miss determination for the access request Y (S204). At this time, as described above, data transfer based on the access request X is started in parallel. Similarly to FIG. 6, since the WAY 0 access state flag 2340 is “Busy”, the arbitration in the arbiter scheduler 231 is performed again for the access request Y.

  Next, simultaneously with the cycle of reading D1 from the WAY0 data array 2350 based on the access request X, the arbiter scheduler 231 selects the subsequent access request Z as a processing target (S203), and the L2HIT / MISS determination unit 232 Z hit / miss determination is performed (S204). Here, it is assumed that a cache hit occurs in WAY 1 (YES in S204). Therefore, data transfer is started from the WAY 1 data array 2351 based on the access request Z. At this time, data transfer based on the access requests X and Z is partially processed in parallel.

  Thereafter, for the access request Y, data transfer is started after completion of data transfer based on the access request X, as in FIG. Data transfer based on access requests Y and Z is partially processed in parallel.

  As described above, the WAY 0 data array 2350 and the WAY 1 data array 2351 according to the second embodiment are configured as separate SRAM macros, and by providing the response bus B 21 and the response bus B 22, parallel access processing is performed. Can be realized.

  Further, the cache memory device 230 uses access state information for managing BUSY and FREE for WAY0 and WAY1, respectively. The arbiter scheduler 231 reschedules an access request to the way determined to be BUSY.

  The second embodiment is particularly effective when burst transfer is performed. Therefore, it can be applied to a cache memory of L2 or less. Further, unlike the multi-bank method, the second embodiment does not require address allocation.

  Here, the second embodiment will be described again. First, when a plurality of access requests to the shared cache are generated, the access request to the cache is arbitrated by the arbiter scheduler, and then tags of a plurality of ways are pulled. Here, the hit or miss of the cache is determined, and the way to be accessed is determined. If the way to be accessed is free, the state is changed to busy and data access is performed. On the other hand, if it is busy, the cache access request is in a wait state, rescheduled by the arbiter scheduler, and reconciled with other access requests, while the access request hits the cache until the way becomes free. A process of repeating the error determination is performed.

  Even when WAY 0 is in burst transfer, the tags of WAY 0 and WAY 1 can both be accessed, and when a subsequent access request is an access to WAY 1, WAY 0 and WAY 1 have different IPs. Data can be exchanged with the core.

  Therefore, according to the second embodiment, partial parallel access to the cache memory becomes possible. Further, since parallel access is performed in units of ways, there is an effect that program tuning is not required unlike the multi-bank method described above.

  Note that the cache memory device 230 according to the second embodiment is shared by a plurality of processor cores, and receives an access request from each processor core individually. As a result, a shared cache memory can be realized for a plurality of access request issuers, and access processing can be partially performed in parallel. In addition, the cache memory device 230 according to the second embodiment is desirably set associative or full associative as described above. Thereby, access can be distributed even in the case of bank competition.

<Embodiment 3>
The cache memory device according to the third embodiment determines the load destination after confirming the WAY 0 access state flag 2340 and the WAY 1 access state flag 2341 at the time of a cache miss. Since the cache memory device according to the third embodiment is the same as that shown in FIG. 3, the illustration and detailed description thereof are omitted.

  FIG. 8 is a flowchart showing a flow of control processing of the cache memory device according to the third embodiment. In FIG. 8, the same processes as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

  If it is determined in step S204 that there is a cache miss, the SDRAM controller 236 determines whether there is a way whose way flag is “Free” (S309). For example, the SDRAM controller 236 refers to the WAY 0 access status flag 2340 and the WAY 1 access status flag 2341 and determines whether or not “Free” is 1 or more.

  If there is no way that is “Free” in step S309, that is, if all the ways are being accessed, the process returns to step S202.

  If it is determined in step S309 that there is a “Free” way, the SDRAM controller 236 determines a load target way from among the “Free” ways (S310). That is, when it is determined that the first access request is a cache miss, a data memory that is not locked among a plurality of data memories is determined as a load destination. Conventionally, it is determined whether or not to load a way determined based on LRU (Least Recently Used) or the like, and if the way is in use, the load must be waited. However, in the third embodiment, by referring to the access state flag of each way in advance, when a load target is determined, a way that can be loaded reliably can be determined.

  That is, the SDRAM controller 236 is a load store unit that loads data requested by an access request from a lower layer memory to one of a plurality of data memories when the access request is determined to be a cache miss by the cache hit determination. is there. Then, the SDRAM controller 236 refers to the access state information and determines a data memory other than that being processed as a load destination.

  Alternatively, as shown in step S209 in FIG. 4, when a way is selected by an existing technique such as LRU and the way is BUSY in step S210, the load target is determined from the ways whose access state flag is “Free”. It may be. As a result, when a new way to load data due to a cache miss and the selected way is BUSY, it is possible to perform parallel access as much as possible with another way as a load target, and performance by parallel access The improvement rate can be increased.

<Embodiment 4>
In the method of determining an existing way to be loaded, data is stored in one way and then stored in another way. In Embodiments 1 to 3, partial parallel processing is performed for access requests for a plurality of different ways. Therefore, it can be said that the parallel processing cannot be executed for the same way according to the first to third embodiments until the data is completely stored in the first way.

  Therefore, in the fourth embodiment, a way different from the way that was set as the load target immediately before is selected as the load target. For example, in the case of 2 ways, the way to be loaded is selected alternately. First, in the fourth embodiment, when an access request is determined to be a cache miss by a cache hit determination, a load for loading data requested by the access request from a lower layer memory to any of the plurality of data memories Equipped with a store unit. The load / store unit according to the fourth embodiment determines a data memory different from the data memory loaded immediately before as the load destination. That is, when loading continuously, a way different from the immediately preceding load destination is determined as the load destination. For example, in an initial stage where a plurality of ways are empty, new ways to be assigned are assigned alternately as WAY0, WAY1, WAY0,. As a result, data can be stored equally for each way, and the probability that parallel processing can be performed can be increased.

<Embodiment 5>
The hit rate of access to a plurality of ways in the cache memory may fluctuate depending on the application requesting the access request and the like and the processing process. Therefore, in the fifth embodiment, data to be loaded at the time of a cache miss is distributed over a plurality of ways. That is, first, in the fifth embodiment, when an access request is determined to be a cache miss by a cache hit determination, data requested by the access request is loaded from a lower layer memory to any of a plurality of data memories. Equipped with a load store unit. The load / store unit according to the fifth embodiment determines a data memory to be a load destination according to the access frequency in a plurality of data memories. The access frequency includes, for example, the usage ratio of the way. As a result, data can be stored in each way in a distributed manner, the hit rate for each way can be distributed, and the probability that parallel access processing can be performed can be improved.

<Embodiment 6>
FIG. 9 is a block diagram showing a configuration of the information processing apparatus 600 according to the sixth embodiment. The information processing apparatus 600 includes a plurality of processor cores 611 to 61m, a tag memory group 120, a data memory group 130, and a cache control unit 620.

  Each of the plurality of processor cores 611 to 61m issues an access request AR to the cache control unit 620. The plurality of processor cores 611 to 61m accept data transfer DT or the like as a response to the access request AR.

  The cache control unit 620 performs cache hit determination to the plurality of tag memories 121 to 12n in response to the first access request from any of the plurality of processor cores 611 to 61m. Then, the cache control unit 620 is specified at the time of a cache hit in the first access request during the access process to any of the plurality of data memories based on the second access request different from the first access request. When the data memory corresponding to the tag memory is not being accessed based on the second access request different from the first access request, the access processing to the data memory is started.

  The tag memory group 120 and the data memory group 130 are the same as those in FIG.

  Thereby, the same effects as those of the first embodiment can be obtained.

<Other embodiments>
As another embodiment, a plurality of hit miss determination units may be provided in parallel. Thereby, hit miss determination can be parallelized for a plurality of access requests.

  In the second embodiment described above, the multiprocessor system is targeted. However, the present invention can be applied to a case where a plurality of access requests are issued from one processor.

  In the first to sixth embodiments described above, since the SRAM macro of the data array is separated for each way, shutdown in units of ways can be easily realized. Therefore, when the access frequency is low, it is possible to save power by reducing the cache capacity by turning off the power.

  In addition, after step 203 in FIG. 4, when the way is “Free”, it is possible to speculatively start reading data on the assumption that the cache hits. Thereby, data reading can be started simultaneously with the hit miss determination of the subsequent access request. In addition, latency can be shortened.

  Furthermore, as another embodiment, there is the following cache memory system. In other words, the cache memory system has a cache memory shared by a plurality of IP cores. The shared cache memory has a set associative cache configuration having a plurality of associations. Then, busy or free state management is performed for each way. Further, the tag memory of the cache memory is accessed by a cache access request. Then, a way that needs to be accessed is determined, and if the way is free, access is permitted. At the same time, the state of the way is busy. In addition, after the data transfer is completed, the free state is restored. Then, it is determined that a subsequent access request accesses the tag memory in a subsequent cycle and accesses a different way, and if the way is free, data access based on the preceding access request and the subsequent access request In parallel.

  The present embodiment can be applied to a SoC (System on a Chip) in which a plurality of processors, processors and other hardware IP, and a shared cache memory are integrated.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

100 cache memory device 110 control unit 120 tag memory group 121 tag memory 122 tag memory 12n tag memory 130 data memory group 131 data memory 132 data memory 13n data memory W1 way W2 way Wn way AR1 access request AR2 access request DT1 data transfer DT2 data Transfer 200 Multiprocessor system 211 IP core 212 IP core 213 IP core 214 IP core 221 L1 cache 222 L1 cache 223 L1 cache 224 L1 cache 230 Cache memory device 231 Arbiter scheduler 232 L2HIT / MISS determination unit 2330 WAY0 tag 2331 WAY1 tag 2340 WAY1 tag 2340 Access status flag 2341 WAY 1 access Status flag 2350 WAY 0 data array 2351 WAY 1 data array 236 SDRAM controller 240 SDRAM
B20 access request bus B21 response bus B22 response bus A IP core B IP core C IP core X access request Y access request Z access request 600 information processing device 611 processor core 612 processor core 61m processor core 620 cache control unit L2 _{0 to} L2 ₇ L2 cache memory

Claims (17)

Multiple tag memories,
A plurality of data memories corresponding to each tag memory;
A cache hit in the plurality of tag memories is determined in response to the first access request, and the cache in the first access request is processed during access processing to any of the plurality of data memories based on the second access request. A control unit that starts an access process to the data memory when the data memory corresponding to the tag memory specified at the time of hit is not being accessed based on the second access request;
A cache memory device comprising:   The cache memory device according to claim 1, wherein the control unit performs burst transfer of data read from the data memory to the request source of the access request as the access processing. A storage area for storing access status information indicating whether or not the data memory is being accessed;
The controller is
When the access process is started based on the second access request in the case of the cache hit, the access process target data memory is being processed, and after the access process is completed, the access process target data memory And updating the access status information respectively,
When the first access request is the cache hit, the access state information is referred to for the data memory corresponding to the specified tag memory, and if the access state information is not being processed, the data memory is transferred to the data memory. The cache memory device according to claim 1, wherein an access process is started. It further includes an arbitration unit that accepts a plurality of access requests and arbitrates,
The controller is
If the data memory corresponding to the tag memory identified when the arbitrated subsequent access request is a cache hit is in the process of being accessed based on the arbitrated previous access request, the subsequent access The cache memory device according to claim 1, wherein the request is returned to the arbitration unit. A load store unit that loads data requested by the access request from a lower layer memory to any of the plurality of data memories when the access request is determined to be a cache miss by the cache hit determination;
4. The cache memory device according to claim 3, wherein the load store unit refers to the access state information and determines a data memory other than that during access processing as a load destination. 5. A load store unit that loads data requested by the access request from a lower layer memory to any of the plurality of data memories when the access request is determined to be a cache miss by the cache hit determination;
The cache memory device according to claim 1, wherein the load store unit determines a data memory different from the data memory loaded immediately before as a load destination. A load store unit that loads data requested by the access request from a lower layer memory to any of the plurality of data memories when the access request is determined to be a cache miss by the cache hit determination;
The cache memory device according to claim 1, wherein the load store unit determines a data memory to be a load destination according to an access frequency in the plurality of data memories.   The cache memory device according to claim 1, wherein the cache memory device is a set associative method.   The cache memory device according to claim 1, wherein the cache memory device is shared by a plurality of processor cores and receives an access request from each processor core individually.   During data access to any of the plurality of ways based on the first access request to the associative cache memory, the way specified by the cache hit in the second access request other than the first access request is the first way. A cache memory device that starts data access to the specified way when data access is not being performed based on an access request. Identify the tag memory that hits the cache based on the first access request,
During an access process to any of a plurality of data memories based on a second access request other than the first access request, a data memory corresponding to the identified tag memory in the first access request is the second To determine whether access processing is in progress based on the access request
A method for controlling a cache memory, which starts an access process based on the first access request when it is determined that the access process is not in progress. When starting the access process based on the second access request, the access target data memory is locked, and after the access process is completed, the access target data memory is unlocked,
Determining whether the data memory corresponding to the tag memory identified based on the first access request is locked;
The cache memory control method according to claim 11, wherein, when it is determined that the lock is not applied, a lock is applied to a data memory subject to access processing of the first access request. Mediation when multiple access requests are accepted,
An access request processed in advance by the arbitration is defined as the second access request, and an access request processed subsequent to the second access request by the arbitration is defined as the first access request.
When it is determined that the data memory subject to access processing of the first access request is undergoing access processing based on the second access request, the first access request is again subject to arbitration. The method of controlling a cache memory according to claim 11. When the first access request is determined to be a cache miss, a data memory that is not locked among a plurality of data memories is determined as a load destination;
13. The cache memory control method according to claim 12, wherein data requested by the first access request is loaded from a lower layer memory to the load destination. When it is determined that the first access request is a cache miss, a data memory different from the data memory loaded immediately before is determined as a load destination,
12. The cache memory control method according to claim 11, wherein data requested by the first access request is loaded from a lower layer memory to the load destination. When it is determined that the first access request is a cache miss, a data memory to be a load destination is determined according to an access frequency in a plurality of data memories,
12. The cache memory control method according to claim 11, wherein data requested by the first access request is loaded from a lower layer memory to the load destination. Multiple processor cores,
Multiple tag memories,
A plurality of data memories corresponding to each tag memory;
A cache hit determination to the plurality of tag memories is performed for the first access request from any of the plurality of processor cores, and the plurality of the plurality of tag cores are determined based on a second access request different from the first access request. When the data memory corresponding to the tag memory specified at the time of the cache hit in the first access request is not being accessed based on the second access request during the access processing to any of the data memories A cache control unit for starting access processing to the data memory;
An information processing apparatus comprising:

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