JP2013207138A - Thin film transistor manufacturing method and thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor manufacturing method which can suppress increase in a driving voltage while preventing deterioration in ease of handling.SOLUTION: A manufacturing method of a thin film transistor 10A comprises: a process S11 of forming first recesses 211, 212 on a top face 21 of a resin substrate 20A by an imprint method and forming a second recess 221 on an undersurface 22 of the resin substrate 20A by the imprinting method; a process S12 of forming a source electrode 31 in one first recess 211 and forming a drain electrode 32 in the other first recess 212 and forming a gate electrode 33 in the second recess 221; and a process S13 of forming an organic semiconductor layer 34 on the top face 21 of the resin substrate 20A so as to partially overlap the source electrode 31 and the drain electrode 32.

Description

  The present invention relates to a method for manufacturing a thin film transistor (TFT) and a thin film transistor.

  A thin film transistor is known in which a gate electrode is formed on one surface of a resin film substrate, and a source electrode, a drain electrode, and a semiconductor layer are formed on the other surface of the resin film substrate (see, for example, Patent Document 1). In this thin film transistor, the resin film substrate itself is used as a gate insulating film.

JP 2005-123290 A

  In the above thin film transistor, the thickness of the gate insulating film is uniquely determined by the thickness of the resin film substrate itself. In general, in order for the thin film transistor to operate properly, the thickness of the gate insulating film needs to be about 1 μm or less. However, when a resin film substrate having such a thickness is used, the ease of handling is impaired, and it becomes difficult to form a thin film transistor. On the other hand, when a thick resin film substrate is used, there is a problem that the driving voltage of the thin film transistor becomes large.

  The problem to be solved by the present invention is to provide a method of manufacturing a thin film transistor and a thin film transistor capable of suppressing an increase in driving voltage while preventing a decrease in ease of handling.

  [1] A method of manufacturing a thin film transistor according to the present invention includes: a first step of forming a pair of first recesses on a first main surface of an insulating substrate using at least an imprint method; A second step of forming a second recess at least on the second main surface opposite to the first main surface by using an imprint method; and forming a source electrode in one of the first recesses And a third step of forming a drain electrode in the other first recess, a fourth step of forming a gate electrode in the second recess, and each of the source electrode and the drain electrode. And a fifth step of forming a semiconductor layer on the first main surface so as to partially overlap with the first main surface.

  In the above invention, the first step and the second step may be performed simultaneously, or the third step and the fourth step may be performed simultaneously. In addition, the order of these steps is not particularly limited as long as the third step and the fifth step are executed after the first step, and the fourth step is executed after the second step.

  [2] In the above invention, in the third step, the source electrode is formed so that a surface of the source electrode is substantially flush with the first main surface, and the drain Forming the drain electrode such that the surface of the electrode is substantially coplanar with the first main surface, and the step (4) includes forming the surface of the gate electrode as the second surface. Forming the gate electrode so as to be substantially coplanar with the main surface.

  [3] A method of manufacturing a thin film transistor according to the present invention includes a first step of forming a first recess on a first main surface of an insulating substrate using at least an imprint method, and the first step in the insulating substrate. A second step of forming a second recess at least on the second main surface opposite to the first main surface by using an imprint method; and a third step of forming a semiconductor layer in the first recess. Forming a source electrode on the first main surface so as to partially overlap the semiconductor layer, and forming a drain electrode on the first main surface so as to partially overlap the semiconductor layer And a fifth step of forming a gate electrode in the second recess.

  In the above invention, the first step and the second step may be performed simultaneously, or the fourth step and the fifth step may be performed simultaneously. In addition, the order of these steps is not particularly limited as long as the third step and the fourth step are performed after the first step and the fifth step is performed after the second step.

  [4] In the above invention, the third step includes forming the semiconductor layer such that a surface of the semiconductor layer is located substantially on the same plane as the first main surface, The fifth step may include forming the gate electrode such that the surface of the gate electrode is substantially flush with the second main surface.

  [5] A method of manufacturing a thin film transistor according to the present invention includes a first step of forming a first recess having a narrow portion and a wide portion on the first main surface of the insulating substrate using at least an imprint method. A second step of forming a second concave portion on the second main surface opposite to the first main surface of the insulating substrate by using at least an imprint method; and a semiconductor layer in the narrow portion. And forming a source electrode in the wide portion so as to partially overlap the semiconductor layer, and forming a drain electrode in the wide portion so as to partially overlap the semiconductor layer. 4 and a fifth step of forming a gate electrode in the second recess.

  In the above invention, the first step and the second step may be performed simultaneously, or the fourth step and the fifth step may be performed simultaneously. In addition, the order of these steps is not particularly limited as long as the third step and the fourth step are performed after the first step and the fifth step is performed after the second step.

  [6] In the above invention, in the fourth step, the source electrode is formed so that a surface of the source electrode is substantially flush with the first main surface; and the drain Forming the drain electrode such that the surface of the electrode is substantially coplanar with the first main surface, and the fifth step includes the step of the surface of the gate electrode being the first surface. Forming the gate electrode so as to be substantially coplanar with the two main surfaces.

  [7] The thin film transistor according to the present invention is located on the opposite side of the first main surface where the first recess is formed and the second main portion where the second recess is formed. An insulating substrate having a surface; a semiconductor layer formed in the first recess; a source electrode formed on the first main surface so as to partially overlap the semiconductor layer; A drain electrode formed on the first main surface so as to partially overlap the semiconductor layer, and a gate electrode formed in the second recess are provided.

  [8] In the above invention, the surface of the semiconductor layer is located substantially on the same plane as the first main surface, and the surface of the gate electrode is substantially coplanar with the second main surface. It may be located above.

  [9] A thin film transistor according to the present invention includes a first main surface on which a first concave portion having a narrow portion and a wide portion is formed, and a second concave portion located on the opposite side of the first main surface. An insulating substrate having a second main surface on which is formed; a semiconductor layer formed in the narrow portion; and a source electrode formed in the wide portion so as to partially overlap the semiconductor layer; A drain electrode formed in the wide portion so as to partially overlap the semiconductor layer, and a gate electrode formed in the second recess are provided.

  [10] In the above invention, the surface of the source electrode is located substantially on the same plane as the first main surface, and the surface of the drain electrode is also substantially flush with the first main surface. The surface of the gate electrode may be located substantially on the same plane as the second main surface.

  According to the present invention, the driving voltage can be controlled by the depth of the first recess and the second recess formed in the insulating substrate even if the insulating substrate is thickened. An increase in driving voltage can be suppressed while preventing a decrease in ease of handling.

FIG. 1 is a cross-sectional view showing the configuration of the thin film transistor in the first embodiment of the present invention. FIG. 2 is a flowchart showing a method of manufacturing a thin film transistor in the first embodiment of the present invention. 3A to 3C are cross-sectional views of the thin film transistor in each step of FIG. FIG. 4 is a cross-sectional view showing the configuration of the thin film transistor in the second embodiment of the present invention. FIG. 5 is a flowchart showing a method of manufacturing a thin film transistor according to the second embodiment of the present invention. 6A to 6C are cross-sectional views of the thin film transistor in each step of FIG. FIG. 7 is a cross-sectional view showing a configuration of a thin film transistor according to the third embodiment of the present invention. FIG. 8 is a flowchart showing a method of manufacturing a thin film transistor in the third embodiment of the present invention. 9A to 9D are cross-sectional views of the thin film transistor at each step of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a cross-sectional view showing the configuration of the thin film transistor according to the first embodiment of the present invention.

  First, a thin film transistor (hereinafter simply referred to as TFT) 10A according to a first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, the TFT 10 </ b> A in this embodiment includes a resin substrate 20 </ b> A that functions as a gate insulating film, and functional layers 31 to 34 that are respectively formed on both surfaces 21 and 22 of the resin substrate 20 </ b> A. This is a so-called bottom contact type organic thin film transistor. The TFT 10A can be used for, for example, a mobile phone, a smartphone, a tablet terminal, a PDA (Personal Digital Assistant), a thin display, an electronic device such as electronic paper, and various sensors such as a pressure sensor.

  The resin substrate 20A is a flexible film having a thickness of, for example, about 10 to 25 [μm] and electrical insulation. The resin substrate 20A is made of a thermoplastic resin or a thermosetting resin, and specifically, a liquid crystal polymer (LCP), a thermoplastic polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN). And bismaleimide triazine (BT), epoxy resin, fluororesin, phenol resin and the like. The resin substrate 20A in the present embodiment corresponds to an example of an insulating substrate in the present invention.

  This resin substrate 20A has an upper surface 21 in which a pair of first recesses 211 and 212 is formed, and a lower surface 22 in which a second recess 221 is formed. The upper surface 21 of the resin substrate 20A in the present embodiment corresponds to an example of the first main surface of the insulating substrate in the present invention, and the lower surface 22 of the resin substrate 20A in the present embodiment is the second of the insulating substrate in the present invention. It corresponds to an example of the main surface.

  The source electrode 31 is embedded in the first recess 211 on one side (left side in the figure) of the resin substrate 20A, and as shown in the figure, the surface 311 of the source electrode 31 is the upper surface of the resin substrate 20A. 21 is located on substantially the same plane. If the TFT 10A operates normally, the surface 311 of the source electrode 31 may be positioned in the first recess 211, or the surface 311 of the source electrode 31 protrudes from the first recess 211. It may be.

  The source electrode 31 is formed, for example, by printing conductive ink containing nano metal particles such as gold (Au) or silver (Ag) in the first recess 211. In place of the conductive ink, a conductive paste containing gold (Au), silver (Ag), carbon (C), etc., an organic resinate obtained by pasting an organometallic compound, or PEDOT (3,4-ethylenedioxythiophene) The source electrode 31 may be formed using an organic conductive material such as).

  Further, instead of the printing method, the source electrode 31 may be formed by sputtering, vacuum vapor deposition, chemical vapor deposition (CVD (Chemical Vapor Deposition)), electroless plating, electrolytic plating, or a combination thereof. It may be formed. In this case, as a material constituting the source electrode 31, for example, chromium (Cr), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni) Gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (Sn), tantalum (Ta), or an alloy containing at least one of these.

  Similarly, the drain electrode 32 is embedded in the first recess 212 on the other side (the right side in the figure) of the resin substrate 20A. As shown in FIG. It is substantially flush with the upper surface 21 of 20A. The drain electrode 32 is formed by the same material and manufacturing method as the source electrode 31. If the TFT 10A operates normally, the surface 321 of the drain electrode 32 may be located in the first recess 212, or the surface 321 of the drain electrode 32 protrudes from the first recess 212. It may be.

  Thus, in this embodiment, the TFT 10A can be thinned by forming the source electrode 31 and the drain electrode 32 in the first recesses 211 and 212, respectively.

  Further, by forming the source electrode 31 and the drain electrode 32 in the first recesses 211 and 212, respectively, the pattern shape of the source electrode 31 and the drain electrode 32 can be formed with high definition, and a desired channel length ( The distance between the source electrode 31 and the drain electrode 32 can also be obtained.

  Further, when the source electrode 31 and the drain electrode 32 are formed by a printing method, the first recesses 211 and 212 suppress the spreading of the ink and prevent the source electrode 31 and the drain electrode 32 from being short-circuited. be able to.

  As shown in FIG. 1, the organic semiconductor layer (OSC: Organic Semiconductor) 34 is formed on the upper surface 21 of the resin substrate 20 </ b> A so as to partially overlap the source electrode 31 and partially overlap the drain electrode 32. The source electrode 31 and the drain electrode 32 are electrically connected. The organic semiconductor layer 34 in the present embodiment corresponds to an example of a semiconductor layer in the present invention.

  Here, in the present embodiment, as described above, the surfaces 311 and 321 of the source electrode 31 and the drain electrode 32 are located substantially on the same plane as the upper surface 21 of the resin substrate 20A. Is easily overlaid on the source electrode 31 and the drain electrode 32, and the TFT 10A is thinned.

  Examples of the material constituting the organic semiconductor layer 34 include polymer materials such as polythiophene such as P3HT (poly- (3-hexylthiophene)) and F8T2 (poly (9,9-dioctylfluorene-co-bithiophene)), pentacene, and the like. Examples of such low molecular weight materials or carbon compounds having semiconductor characteristics such as carbon nanotubes and fullerenes can be given.

  On the other hand, a gate electrode 33 is embedded in the second recess 221 of the resin substrate 20A, and as shown in the figure, the surface 331 of the gate electrode 33 is substantially the same as the lower surface 22 of the resin substrate 20A. Located on a plane. The gate electrode 33 is also formed by the same material and manufacturing method as those of the source electrode 31 and the drain electrode 32 described above. If the TFT 10A operates normally, the surface 331 of the gate electrode 33 may be located in the second recess 221 or the surface 331 of the gate electrode 33 protrudes from the second recess 221. It may be.

In this embodiment, the use of the resin substrate 20A as a gate insulating film, so to form a gate electrode 33 within the second recess 221, the depth h ₁ of the second recess 221, the gate insulating the resin substrate 20A The thickness h ₀ of the part functioning as a film (the part located between the organic semiconductor layer 34 and the gate electrode 33 in the resin substrate 20A) can be controlled. Further, the TFT 10A can be thinned by forming the gate electrode 33 in the second recess 221.

  Next, a manufacturing method of the TFT 10A according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 2 is a flowchart showing a method of manufacturing a TFT according to the first embodiment of the present invention, FIGS. 3A to 3C are cross-sectional views of the TFT in each step of FIG. 2, and FIG. 2 is a cross-sectional view of the TFT in step S11, FIG. 3B is a cross-sectional view of the TFT in step S12 of FIG. 2, and FIG. 3C is a cross-sectional view of the TFT in step S13 of FIG.

  First, in step S11 of FIG. 2, as shown in FIG. 3A, first recesses 211 and 212 are formed on both surfaces 21 and 22 of the resin substrate 20A by a thermal imprint method using imprint molds 51A and 52, respectively. And the 2nd recessed part 221 is formed, respectively. That is, both surfaces of the resin substrate 20A are heated in a state where the imprint molds 51A and 52 and the resin substrate 20A are heated to a predetermined temperature (a temperature higher than the glass transition point of the material constituting the resin substrate 20A, for example, 150 ° C. to 250 ° C.). The imprint molds 51 </ b> A and 52 are pressed against the surfaces 21 and 22 to transfer the shapes of the convex portions 511, 512 and 521 of the imprint molds 51 </ b> A and 52 to the resin substrate 20 </ b> A, thereby forming the concave portions 211, 212 and 221. Incidentally, the depth of the recesses 211 and 212 is, for example, about 1 μm to 30 μm.

  If necessary, the resin substrate 20A may be cleaned by brush cleaning, ultrasonic cleaning, or the like before imprinting, or the recesses 211, 212, and 221 may be cleaned using a solvent after imprinting.

The upper mold 51A used in this step S11 is, for example, silicon (Si), quartz (SiO ₂ ), silicon carbide (SiC), glassy carbon (GC), nickel (Ni), copper (Cu), tantalum (Ta ) And the like, and has convex portions 511 and 512 corresponding to the first concave portions 211 and 212. On the other hand, the lower mold 52 is also made of the same material as that of the upper mold 51 </ b> A, and has a convex portion 521 corresponding to the second concave portion 221.

In this embodiment, since the recesses 211, 212, and 221 are formed in the resin substrate 20A by the thermal imprint method, the thickness h ₀ (see FIG. 1) of the portion that functions as the gate insulating film in the resin substrate 20A is set to 1 for example. The thickness can be reduced to [μm] or less.

  Note that the concave portions 211, 212, and 221 may be formed in the resin substrate 20A by the UV imprint method instead of the thermal imprint method. By using the thermal imprinting method or the UV imprinting method, a portion functioning as a gate insulating film in the resin substrate 20A can be formed to a desired thickness without depending on the thickness of the resin substrate 20A.

  In addition, the resin substrate 20A is formed by an injection molding method prior to step S10 in FIG. 2, but it is difficult to obtain a resin substrate 20A having a uniform thickness by this manufacturing method. There is unevenness. Thus, even if the original thickness of the resin substrate 20A is non-uniform, if the first concave portions 211 and 212 and the second concave portion 221 are formed by using the imprint method, a gate insulation having a desired thickness is obtained. A film can be formed stably.

  Incidentally, it is difficult to process or mold the thickness of the resin substrate to 1 [μm] or less by the etching method, the injection molding method, and the sandblasting method. In addition, when the original thickness of the resin substrate is not uniform as described above, the thickness of the portion functioning as the gate insulating film can be controlled with high accuracy by the etching method or the sandblast method. difficult. As a result, the gate insulating film becomes thick and the driving voltage of the TFT becomes large, or the thickness of the gate insulating film becomes non-uniform and the operation of the TFT becomes unstable.

  In the present embodiment, all the concave portions 211, 212, and 221 are simultaneously formed on both surfaces 21 and 22 of the resin substrate 20A, but the present invention is not particularly limited thereto. For example, the first recesses 211 and 212 may be formed on the upper surface 21 of the resin substrate 20A by the upper mold 51A, and then the second recesses 221 may be formed on the lower surface 22 of the resin substrate 20A by the lower mold 52. Alternatively, the two concave portions 211 and 212 on the upper surface 21 of the resin substrate 20A may be formed by separate molds.

  In the present embodiment, the first recesses 211 and 212 and the second recess 221 are formed using only the imprint method. However, the present invention is not limited to this, and other methods may be used in addition to the imprint method. In combination, the first recess 211, 212 and the second recess 221 may be formed.

For example, the first recesses 211 and 212 and the second recess 221 may be formed by combining an etching method, a sandblasting method, and an imprint method. Specifically, first, a shallow concave portion may be formed in advance using an etching method or a sand blast method, and then the first concave portions 211 and 212 and the second concave portion 221 may be completed using an imprint method. Since it is necessary to control the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20A with high accuracy, the first recess 211, 212 and the second recess 221 are finally completed by using the imprint method. It is preferable to make it.

  Next, in step S12 of FIG. 2, as shown in FIG. 3B, the conductive ink 63 is printed on the resin substrate 20A by flexographic printing using the printing plates 61 and 62, whereby the first resin substrate 20A is printed. The source electrode 31 and the drain electrode 32 are formed in the recesses 211 and 212, and the gate electrode 33 is formed in the second recess 221 of the resin substrate 20A.

  Specifically, the conductive ink 63 attached to the convex portions 611 and 612 of the upper printing plate 61 is transferred to the first concave portions 211 and 212 of the resin substrate 20A, and the convex portion 621 of the lower printing plate 62 is transferred. After transferring the conductive ink 63 attached to the second recess 221 of the resin substrate 20A, the transferred conductive ink 63 is cured to form all the electrodes 31 to 33 simultaneously.

  In the present embodiment, the conductive ink 63 is printed on the resin substrate 20A by flexographic printing, but is not particularly limited thereto. Instead of flexographic printing, for example, the conductive ink may be printed on the resin substrate 20A by other printing methods such as gravure printing, offset printing, inkjet method, screen printing, and the like.

  Moreover, in this embodiment, although all the electrodes 31-33 of 20 A of resin substrates are formed simultaneously, it is not specifically limited to this. For example, after the source electrode 31 and the drain electrode 32 are printed by the upper printing plate 61, the gate electrode 33 may be printed by the lower printing plate 62. Alternatively, the source electrode 31 and the drain electrode 32 may be printed on separate printing plates.

  Moreover, in this embodiment, although the electrodes 31-33 were formed using the printing method, it is not limited to this in particular. For example, instead of the printing method, a conductive layer was formed on the entire surface of the resin substrate by sputtering, vacuum deposition, chemical vapor deposition (CVD), electroless plating, electroplating, or a combination thereof. The electrodes 31 to 33 may be formed later by processing the conductive layer by photolithography and etching. Alternatively, the electrodes 31 to 33 may be formed by performing sputtering or the like after forming a resist pattern on the resin substrate.

  Moreover, you may wash | clean or grind both surfaces 21 and 22 of 20 A of resin substrates after formation of the electrodes 31-33 as needed. Specific examples of the polishing method include tape polishing, CMP (Chemical Mechanical Polishing), and etching. By polishing both surfaces 21 and 22 of the resin substrate 20A, the TFT 10A can be thinned or flattened. In addition, after the electrodes 31 and 32 are formed, the other surface 21 of the resin substrate 20A is polished to clean the surfaces of the electrodes 31 and 32, and the bonding strength between the electrodes 31 and 32 and the organic semiconductor layer 34 is increased. improves.

  Next, in step S13 of FIG. 2, as shown in FIG. 3C, after the organic semiconductor material 72 converted into an ink is printed on the resin substrate 20 </ b> A by flexographic printing using the printing plate 71, the organic semiconductor material 72 is By curing, the organic semiconductor layer 34 is formed on the upper surface 21 of the resin substrate 20A. At this time, the organic semiconductor material 72 is printed on the upper surface 21 of the resin substrate 20 </ b> A so as to partially overlap the source electrode 31 and also partially overlap the drain electrode 32.

Note that, before printing the organic semiconductor material 72 on the resin substrate 20A, a self-assembled monolayer (SAM) may be formed on the printed portion of the upper surface 21 of the resin substrate 20A. Further, a doping layer may be formed at the contact interface with the source electrode 31 and the drain electrode 32 in the organic semiconductor layer 34. Furthermore, a protective layer (for example, a SiN _x film) covering the entire upper surface 21 of the resin substrate 20A including the organic semiconductor layer 34 or only the organic semiconductor layer 34 may be formed.

  Moreover, in this embodiment, although the organic-semiconductor material 72 is printed on the resin substrate 20A by flexographic printing, it is not limited to this. Instead of flexographic printing, for example, the organic semiconductor material may be printed on the resin substrate 20A by other printing methods such as gravure printing, offset printing, inkjet printing, and screen printing.

  Moreover, in this embodiment, although the organic-semiconductor layer 34 was formed using the printing method, it is not specifically limited to this. For example, instead of the printing method, the organic semiconductor layer 34 may be formed by using a vacuum deposition method, a spin coating method, a sputtering method, a chemical vapor deposition method (CVD method), or the like.

As described above, in the present embodiment, the resin substrate 20A is used as the gate insulating film, and the gate electrode 33 is formed in the second recess 221 formed in the resin substrate 20A. Therefore, even when the thickness of the resin substrate 20A, the thickness _{h 0} of the portion functioning as a gate insulating film in the resin substrate 20A, it is possible to control the driving voltage of the TFT 10A, the decrease in the ease of handling of the TFT 10A It is possible to suppress an increase in driving voltage while preventing it.

  The manufacturing procedure of the TFT 10A is not particularly limited to the above. For example, even if the first recesses 211 and 212 are formed in the resin substrate 20A and the source electrode 31 and the drain electrode 32 are formed, the second recess 221 is formed in the resin substrate 20A and the gate electrode 33 is formed. Good. Alternatively, after forming the organic semiconductor layer 34, the second recess 221 may be formed in the resin substrate 20A, and the gate electrode 33 may be formed. Alternatively, after forming the gate electrode 33, the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 may be formed.

  Step S11 in FIG. 2 in the present embodiment corresponds to an example of the first to second steps in the present invention, and step S12 in FIG. 2 in the present embodiment corresponds to an example of the third to fourth steps in the present invention. And step S13 of Drawing 2 in this embodiment is equivalent to an example of the 5th process in the present invention.

<< Second Embodiment >>
FIG. 4 is a cross-sectional view showing the configuration of the thin film transistor according to the second embodiment of the present invention.

  The TFT 10B in this embodiment is different from the first embodiment in the positional relationship between the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34, but the other configurations are the same as those in the first embodiment. Hereinafter, only the differences from the first embodiment of the TFT 10B in the second embodiment will be described, and portions having the same configuration as in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

  As shown in FIG. 4, the TFT 10B in the present embodiment is a so-called top contact type organic thin film transistor including a resin substrate 20B and functional layers 31 to 34 formed on the resin substrate 20B.

  The resin substrate 20B is the same film as the resin substrate 20A of the first embodiment, and is the same as the first embodiment in that the second recess 221 is formed on the lower surface 22 thereof, but on the upper surface 21 thereof. The first embodiment is different from the first embodiment in that one first recess 213 is formed. The first recess 213 overlaps the second recess 221 when viewed from the normal direction of the resin substrate 20B (Z direction in FIG. 4).

  In the present embodiment, the organic semiconductor layer 34 is embedded in the first recess 213 of the resin substrate 20B, and as shown in the figure, the surface 341 of the organic semiconductor layer 34 is the upper surface 21 of the resin substrate 20B. And are located on substantially the same plane. Note that if the TFT 10B operates normally, the surface 341 of the organic semiconductor layer 34 may be positioned in the first recess 213, or the surface 341 of the organic semiconductor layer 34 extends from the first recess 213. It may protrude.

  As described above, in the present embodiment, the organic semiconductor layer 34 is formed in the first recess 213, so that the TFT 10B is thinned.

  As shown in FIG. 4, the source electrode 31 is formed on the upper surface 21 of the resin substrate 20 </ b> B so as to partially overlap the organic semiconductor layer 34. Similarly, the drain electrode 32 is also formed on the upper surface 21 of the resin substrate 20 </ b> B so as to partially overlap the organic semiconductor layer 34. The source electrode 31 and the drain electrode 32 are formed at a predetermined distance on the upper surface 21 of the resin substrate 2 b and are electrically connected via the organic semiconductor layer 34.

  Here, in the present embodiment, as described above, the surface 341 of the organic semiconductor layer 34 is located substantially on the same plane as the upper surface 21 of the resin substrate 20B. Is not formed. For this reason, since the disconnection of the source electrode 31 and the drain electrode 32 is suppressed, the reliability of the TFT 10B can be improved.

  Further, since the surface 341 of the organic semiconductor layer 34 is located substantially on the same plane as the upper surface 21 of the resin substrate 20B, the source electrode 31 and the drain electrode 32 can be easily stacked, and the TFT 10B can be thinned. You can also plan.

  On the other hand, a gate electrode 33 is embedded in the second recess 221 of the resin substrate 20B, as in the first embodiment, and as shown in the figure, the surface 331 of the gate electrode 33 is formed on the resin substrate 20B. Is located substantially on the same plane as the lower surface 22 of the substrate. If the TFT 10B operates normally, the surface 331 of the gate electrode 33 may be positioned in the second recess 221 or the surface 331 of the gate electrode 33 protrudes from the second recess 221. It may be.

In the present embodiment, the resin substrate 20 </ b> B is used as a gate insulating film, the gate electrode 33 is formed in the second recess 221, and the organic semiconductor layer 34 is formed in the first recess 213. Therefore, it is the depth of the second recess 221 h ₁ and the depth h ₂ of the first recess 213, to control the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20B. In addition, the TFT 10B can be thinned by forming the gate electrode 33 in the second recess 221.

  Next, a manufacturing method of the TFT 10B in the second embodiment of the present invention will be described with reference to FIGS.

  FIG. 5 is a flowchart showing a manufacturing method of a TFT according to the second embodiment of the present invention, FIGS. 6A to 6C are cross-sectional views of the TFT in each step of FIG. 5, and FIG. FIG. 6B is a cross-sectional view of the TFT in step S22 of FIG. 5, and FIG. 6C is a cross-sectional view of the TFT in step S23 of FIG.

  First, in step S21 of FIG. 5, as shown in FIG. 6A, the first recess 213 and the first recess 213 are formed on both surfaces 21 and 22 of the resin substrate 20B by the thermal imprint method using the imprint molds 51B and 52. Two recesses 221 are formed respectively. The upper mold 51B used in the present embodiment has only one convex portion 513 corresponding to the first concave portion 213.

In the present embodiment, since the recesses 213 and 221 on the resin substrate 20B by thermal imprinting method, the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20B, thinned to example 1 [[mu] m] or less be able to. Note that the recesses 213 and 221 may be formed in the resin substrate 20B by the UV imprint method instead of the thermal imprint method.

  In the present embodiment, all the recesses 213 and 221 are simultaneously formed on both surfaces 21 and 22 of the resin substrate 20B, but the present invention is not particularly limited thereto. For example, after the first recess 213 is formed on the upper surface 21 of the resin substrate 20B by the upper mold 51B, the second recess 221 may be formed on the lower surface 22 of the resin substrate 20B by the lower mold 52.

  In the present embodiment, the first recess 213 and the second recess 221 are formed using only the imprint method. However, the present invention is not limited to this, and other methods are used in combination with the imprint method. Then, the first recess 213 and the second recess 221 may be formed.

For example, the first recess 213 and the second recess 221 may be formed by a combination of an etching method, a sandblasting method, and an imprint method. Specifically, first, a shallow concave portion may be formed in advance using an etching method or a sand blast method, and then the first concave portion 213 and the second concave portion 221 may be completed using an imprint method. Since it is necessary to control the thickness h ₀ of the portion functioning as the gate insulating film in the resin substrate 20B with high accuracy, the first recess 213 and the second recess 221 are finally completed by using the imprint method. Is preferred.

  Next, in step S22 of FIG. 5, as shown in FIG. 6B, the organic semiconductor material 72 converted into an ink is printed on the resin substrate 20 </ b> B by flexographic printing using the printing plate 71. By curing, the organic semiconductor layer 34 is formed in the first recess 213.

  Note that a self-assembled monolayer may be formed on the bottom surface of the first recess 213 before printing the organic semiconductor material 72 on the resin substrate 20B. Further, a doping layer may be formed at the contact interface with the source electrode 31 and the drain electrode 32 in the organic semiconductor layer 34.

  Moreover, in this embodiment, although the organic-semiconductor material 72 is printed on the resin substrate 20B by flexographic printing, it is not specifically limited to this. Instead of flexographic printing, the organic semiconductor material 72 may be printed on the resin substrate 20B by other printing methods such as gravure printing, offset printing, inkjet printing, and screen printing.

  Moreover, in this embodiment, although the organic-semiconductor layer 34 was formed using the printing method, it is not specifically limited to this. For example, instead of the printing method, the organic semiconductor layer 34 may be formed by using a vacuum deposition method, a spin coating method, a sputtering method, a chemical vapor deposition method (CVD method), or the like.

  If necessary, the upper surface 21 of the resin substrate 20B may be cleaned or polished after the organic semiconductor layer 34 is formed. Specific examples of the polishing method include tape polishing, CMP, and etching. By polishing the upper surface 21 of the resin substrate 20B, the TFT 10B can be thinned or flattened. In addition, after the organic semiconductor layer 34 is formed, the surface of the organic semiconductor layer 34 is cleaned by polishing the other surface 21 of the resin substrate 20 </ b> B, and the organic semiconductor layer 34, the source electrode 31, and the drain electrode 32. Bonding strength is improved.

  Next, in step S23 of FIG. 5, as shown in FIG. 6C, the conductive ink 63 is printed on the resin substrate 20B by flexographic printing using the printing plates 61 and 62, whereby the upper surface 21 of the resin substrate 20B. In addition, the source electrode 31 and the drain electrode 32 are formed, and the gate electrode 33 is formed in the second recess 221 of the resin substrate 20B.

  Specifically, the conductive ink 63 adhering to the convex portions 611 and 612 of the upper printing plate 61 is transferred to the upper surface 21 of the resin substrate 20B and the electric conductivity adhering to the convex portion 621 of the lower printing plate 62. After the ink 63 is transferred to the second recess 221 of the resin substrate 20B, the transferred conductive ink 63 is cured to form all the electrodes 31 to 33 simultaneously. At this time, the conductive ink 63 is printed on the upper surface 21 of the resin substrate 20B so that the source electrode 31 and the drain electrode 32 partially overlap with the organic semiconductor layer 34, respectively.

  In the present embodiment, the conductive ink 63 is printed on the resin substrate 20B by flexographic printing, but is not particularly limited thereto. Instead of flexographic printing, the conductive ink may be printed on the resin substrate 20B by other printing methods such as gravure printing, offset printing, inkjet printing, screen printing, and the like.

  Moreover, in this embodiment, although all the electrodes 3-33 of the resin substrate 20B are formed simultaneously, it is not specifically limited to this. For example, after the source electrode 31 and the drain electrode 32 are printed by the upper printing plate 61, the gate electrode 33 may be printed by the lower printing plate 62. Alternatively, the source electrode 31 and the drain electrode 32 may be printed on separate printing plates.

  Moreover, in this embodiment, although the electrodes 31-33 were formed using the printing method, it is not limited to this in particular. For example, instead of the printing method, the electrodes 31 to 33 may be formed by sputtering, vacuum deposition, chemical vapor deposition (CVD), electroless plating, electrolytic plating, or a combination thereof. Good.

  If necessary, the lower surface 22 of the resin substrate 20B may be cleaned or polished after the formation of the gate electrode 33. Further, a protective layer that covers the entire upper surface 21 of the resin substrate 20B including the source electrode 31 and the drain electrode 32 or only the source electrode 31 and the drain electrode 32 may be formed.

As described above, in this embodiment, the resin substrate 20B is used as the gate insulating film, the gate electrode 33 is formed in the second recess 221 and the organic semiconductor layer 34 is in the first recess 213. Form. Therefore, even when the thickness of the resin substrate 20B, the thickness _{h 0} of the portion functioning as a gate insulating film in the resin substrate 20B, it is possible to control the driving voltage of the TFT 10b, a decrease in handling ease of TFT 10b It is possible to suppress an increase in driving voltage while preventing it.

  The manufacturing procedure of the TFT 10B is not particularly limited to the above. For example, after forming the organic semiconductor layer 34, the second recess 221 may be formed in the resin substrate 20B, and the gate electrode 33 may be formed. Alternatively, after forming the source electrode 31 and the drain electrode 32, the second recess 221 may be formed in the resin substrate 20B, and the gate electrode 33 may be formed. Alternatively, after forming the gate electrode 33, the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 may be formed.

  Step S21 in FIG. 5 in the present embodiment corresponds to an example of the first and second steps in the present invention, and step S22 in FIG. 5 in the present embodiment corresponds to an example of the third step in the present invention. Step S23 of FIG. 5 in the embodiment corresponds to an example of fourth to fifth steps in the present invention.

<< Third Embodiment >>
FIG. 7 is a cross-sectional view showing the configuration of the thin film transistor according to the third embodiment of the present invention.

  The TFT 10C in this embodiment is different from the first embodiment in that all of the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 are embedded in the first recess 214 of the resin substrate 20C. Other configurations are the same as those in the first embodiment. In the following, only the differences between the TFT 10C in the third embodiment and the first embodiment will be described, and portions having the same configuration as in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

  As shown in FIG. 7, the TFT 10 </ b> C in this embodiment is a so-called top contact type organic thin film transistor including a resin substrate 20 </ b> C and functional layers 31 to 34 formed on the resin substrate 20 </ b> C.

  The resin substrate 20C is the same film as the resin substrate 20A of the first embodiment, and is the same as the first embodiment in that the second recess 221 is formed on the lower surface 22 thereof, but on the upper surface 21 thereof. This is different from the first embodiment in that one step-shaped first concave portion 214 is formed.

  The first concave portion 214 in the present embodiment has a narrow portion 215 at the lower portion thereof, and has a wide portion 216 wider than the narrow portion 215 at the upper portion thereof. A step 217 is formed between 215 and the wide portion 216. Similar to the first recess 213 of the second embodiment, the first recess 214 overlaps the second recess 221 when viewed from the normal direction of the resin substrate 20C (Z direction in FIG. 4). .

  In the present embodiment, the organic semiconductor layer 34 is embedded in the narrow portion 215 of the first recess 214 of the resin substrate 20 </ b> C, and the source electrode 31 is further embedded in the wide portion 216 of the first recess 214. The drain electrode 32 is embedded.

  At this time, as shown in FIG. 7, the source electrode 31 is formed in the wide portion 216 so as to partially overlap the organic semiconductor layer 34, and the upper surface 311 of the source electrode 31 is the upper surface of the resin substrate 20C. 21 is located on substantially the same plane. Note that if the TFT 10C operates normally, the surface 311 of the source electrode 31 may be positioned in the first recess 214, or the surface 311 of the source electrode 31 protrudes from the first recess 214. May be.

  Similarly, the drain electrode 32 is also formed in the wide portion 216 so as to partially overlap the organic semiconductor layer 34, and the upper surface 321 of the drain electrode 32 is substantially the same as the upper surface 21 of the resin substrate 20C. Located on a plane. If the TFT 10 </ b> C operates normally, the upper surface 321 of the drain electrode 32 may be positioned in the first recess 214, or the upper surface 321 of the drain electrode 32 protrudes from the first recess 214. May be.

  Thus, in this embodiment, the TFT 10C can be made to have the same thickness as the resin substrate 20C by forming the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 in the first recess 214. Further, the thinning of the TFT 10C can be achieved. Moreover, since the disconnection of the source electrode 31 and the drain electrode 32 can be suppressed or the organic semiconductor layer 34 can be protected, the reliability of the TFT 10B can be improved.

  In the present embodiment, the source electrode 31 and the drain electrode 32 are formed at a predetermined distance in the wide portion 315 and are electrically connected via the organic semiconductor layer 34. A sealing layer 35 is formed in the gap 218 between the source electrode 31 and the drain electrode 32 in the wide portion 315. The sealing layer 35 is made of an electrically insulating material such as a resin material. The sealing layer 35 may be formed so as to cover not only the gap 218 but also the upper surfaces 311 and 321 of the source electrode 31 and the drain electrode 32.

  On the other hand, the gate electrode 33 is embedded in the second recess 221 of the resin substrate 20C, as in the first embodiment, and as shown in the figure, the surface 331 of the gate electrode 33 is formed on the resin substrate 20B. Is located substantially on the same plane as the lower surface 22 of the substrate. If the TFT 10C operates normally, the surface 331 of the gate electrode 33 may be positioned in the second recess 221 or the surface 331 of the gate electrode 33 protrudes from the second recess 221. It may be.

In the present embodiment, the resin substrate 20C is used as a gate insulating film, the gate electrode 33 is formed in the second recess 221, and the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 are formed in the first recess. It is formed in the recess 214. Therefore, it is the depth of the second recess 221 h ₁ and the depth h ₂ of the first recess 214, to control the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20C. Further, by forming the gate electrode 33 in the second recess 221, the TFT 10C can be thinned.

  Next, the manufacturing method of TFT10C in 3rd Embodiment of this invention is demonstrated, referring FIG.8 and FIG.9.

  FIG. 8 is a flowchart showing a manufacturing method of a TFT according to the third embodiment of the present invention, FIGS. 9A to 9D are cross-sectional views of the TFT in each step of FIG. 8, and FIG. FIG. 9B is a cross-sectional view of the TFT in step S32 of FIG. 8, FIG. 9C is a cross-sectional view of the TFT in step S33 of FIG. 8, and FIG. FIG. 9 is a cross-sectional view of the TFT in step S34 of FIG.

  First, in step S31 of FIG. 8, the first concave portion 214 and the second concave portion 221 are formed on both surfaces 21 and 22 of the resin substrate 20C using the imprint molds 51C and 52, respectively, by the thermal imprint method. The upper mold 51 </ b> C in the present embodiment is a two-stage mold having a convex portion 514 having a shape corresponding to the stepped first concave portion 214. Note that two single-stage molds may be used instead of the upper mold 51C.

In the present embodiment, since the recesses 214, 221 on the resin substrate 20C by thermal imprinting method, the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20C, thinned to example 1 [[mu] m] or less be able to. Note that the recesses 214 and 221 may be formed in the resin substrate 20C by the UV imprint method instead of the thermal imprint method.

  In the present embodiment, all the recesses 214 and 221 are simultaneously formed on both surfaces 21 and 22 of the resin substrate 20C, but the present invention is not limited to this. For example, after the first recess 214 is formed on the upper surface 21 of the resin substrate 20C by the upper mold 51C, the second recess 221 may be formed on the lower surface 22 of the resin substrate 20C by the lower mold 52.

  In the present embodiment, the first recess 214 and the second recess 221 are formed using only the imprint method. However, the present invention is not limited to this, and other methods are used in combination with the imprint method. Then, the first recess 214 and the second recess 221 may be formed.

For example, the first recess 214 and the second recess 221 may be formed by combining an etching method, a sandblasting method, and an imprint method. Specifically, first, a shallow concave portion may be formed in advance using an etching method or a sand blast method, and then the first concave portion 214 and the second concave portion 221 may be completed using an imprint method. Since it is necessary to control the thickness h ₀ of the portion functioning as a gate insulating film in the resin substrate 20C with high accuracy, the first concave portion 214 and the second concave portion 221 are finally completed by using the imprint method. Is preferred.

  Next, in step S32 of FIG. 8, as shown in FIG. 9B, after the organic semiconductor material 72 that has been made into ink is printed on the resin substrate 20C by flexographic printing using the printing plate 71, the organic semiconductor material 72 is By curing, the organic semiconductor layer 34 is formed in the narrow portion 215 of the first recess 214.

  Note that a self-assembled monolayer may be formed on the bottom surface of the narrow portion 215 of the first recess 214 before printing the organic semiconductor material 72 on the resin substrate 20C. Further, a doping layer may be formed at the contact interface with the source electrode 31 and the drain electrode 32 in the organic semiconductor layer 34.

  Moreover, in this embodiment, although the organic-semiconductor material 72 is printed on the resin substrate 20C by flexographic printing, it is not limited to this. Instead of flexographic printing, the organic semiconductor material 72 may be printed on the resin substrate 20C by other printing methods such as gravure printing, offset printing, inkjet printing, and screen printing.

  Moreover, in this embodiment, although the organic-semiconductor layer 34 was formed using the printing method, it is not specifically limited to this. For example, instead of the printing method, the organic semiconductor layer 34 may be formed by using a vacuum deposition method, a spin coating method, a sputtering method, a chemical vapor deposition method (CVD method), or the like.

  Next, in step S33 of FIG. 8, as shown in FIG. 9C, the conductive ink 63 is printed on the resin substrate 20B by flexographic printing using the printing plates 61 and 62. Thereby, the source electrode 31 and the drain electrode 32 are formed in the wide portion 216 of the first recess 214 of the resin substrate 20C, and the gate electrode 33 is formed in the second recess 221 of the resin substrate 20C. .

  Specifically, the conductive ink 63 attached to the convex portions 611 and 612 of the upper printing plate 61 is transferred into the wide portion 216 of the first concave portion 214 of the resin substrate 20C, and the lower printing plate 62 is After the conductive ink 63 attached to the convex portion 621 is transferred to the second concave portion 221 of the resin substrate 20C, the transferred conductive ink 63 is cured to form all the electrodes 31 to 33 simultaneously. At this time, the conductive ink 63 is printed on the wide portion 216 of the first recess 214 so that the source electrode 31 and the drain electrode 32 partially overlap the organic semiconductor layer 34. If necessary, after forming all the electrodes 31 to 33, the both surfaces 21 and 22 of the resin substrate 20C may be cleaned or polished. By polishing both surfaces 21 and 22 of the resin substrate 20C, the TFT 10C can be thinned or flattened.

  In the present embodiment, the conductive ink 63 is printed on the resin substrate 20C by flexographic printing, but is not particularly limited thereto. Instead of flexographic printing, the conductive ink may be printed on the resin substrate 20C by other printing methods such as gravure printing, offset printing, inkjet printing, screen printing, and the like.

  Moreover, in this embodiment, although all the electrodes 31-33 of 20 C of resin substrates are formed simultaneously, it is not specifically limited to this. For example, after the source electrode 31 and the drain electrode 32 are printed by the upper printing plate 61, the gate electrode 33 may be printed by the lower printing plate 62. Alternatively, the source electrode 31 and the drain electrode 32 may be printed on separate printing plates.

  Moreover, in this embodiment, although the electrodes 31-33 were formed using the printing method, it is not limited to this in particular. For example, instead of the printing method, the electrodes 31 to 33 may be formed by sputtering, vacuum deposition, chemical vapor deposition (CVD), electroless plating, electrolytic plating, or a combination thereof. Good.

  Next, in step S34 of FIG. 8, as shown in FIG. 9D, the resin material 82 is printed and cured in the gap 218 between the source electrode 31 and the drain electrode 32 by flexographic printing using the printing plate 81. Thereby, the sealing layer 35 is formed.

  Instead of flexographic printing, for example, other printing methods such as gravure printing, offset printing, ink jet printing, screen printing, printing such as vacuum deposition, spin coating, sputtering, chemical vapor deposition (CVD), etc. The sealing layer 35 may be formed using a method other than the method.

As described above, in the present embodiment, the resin substrate 20C is used as the gate insulating film and is formed in the first recess 221 of the gate electrode 33, and the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 are formed. Is formed in the first recess 214. Therefore, even when the thickness of the resin substrate 20C, the thickness _{h 0} of the portion functioning as a gate insulating film in the resin substrate 20C, it is possible to control the driving voltage of the TFT 10 c, a decrease in handling ease of TFT 10 c It is possible to suppress an increase in driving voltage while preventing it.

  The manufacturing procedure of the TFT 10C is not particularly limited to the above. For example, after forming the organic semiconductor layer 34, the second recess 221 may be formed in the resin substrate 20C, and the gate electrode 33 may be formed. Alternatively, after forming the source electrode 31 and the drain electrode 32, the second recess 221 may be formed in the resin substrate 20C, and the gate electrode 33 may be formed. Alternatively, after forming the gate electrode 33, the source electrode 31, the drain electrode 32, and the organic semiconductor layer 34 may be formed.

  Step S31 in FIG. 8 in the present embodiment corresponds to an example of the first and second steps in the present invention, and step S32 in FIG. 8 in the present embodiment corresponds to an example of the third step in the present invention. Step S33 of FIG. 8 in the embodiment corresponds to an example of fourth to fifth steps in the present invention.

  The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

10A-10C ... TFT
20A to 20C: resin substrate 21 ... upper surface 211-214 ... first recess 22 ... lower surface 221 ... second recess 31 ... source electrode 32 ... drain electrode 33 ... gate electrode 34 ... organic semiconductor layers 51A-51C, 52 ... in Print mold 61, 62, 71 ... Printing plate 63 ... Conductive ink 72 ... Organic semiconductor material

Claims (10)

A method for manufacturing a thin film transistor, comprising:
A first step of forming a pair of first recesses on the first main surface of the insulating substrate using at least an imprint method;
A second step of forming a second recess at least on the second main surface opposite to the first main surface in the insulating substrate by using an imprint method;
Forming a source electrode in one of the first recesses and forming a drain electrode in the other first recess;
A fourth step of forming a gate electrode in the second recess;
And a fifth step of forming a semiconductor layer on the first main surface so as to partially overlap each of the source electrode and the drain electrode. A method of manufacturing a thin film transistor according to claim 1,
The third step includes
Forming the source electrode such that a surface of the source electrode is substantially coplanar with the first main surface;
Forming the drain electrode such that the surface of the drain electrode is substantially coplanar with the first main surface,
4. The method of manufacturing a thin film transistor, wherein the step 4 includes forming the gate electrode so that a surface of the gate electrode is located substantially on the same plane as the second main surface. A method for manufacturing a thin film transistor, comprising:
A first step of forming a first recess at least on the first main surface of the insulating substrate using an imprint method;
A second step of forming a second recess at least on the second main surface opposite to the first main surface in the insulating substrate by using an imprint method;
A third step of forming a semiconductor layer in the first recess;
A source electrode is formed on the first main surface so as to partially overlap the semiconductor layer, and a drain electrode is formed on the first main surface so as to partially overlap the semiconductor layer. And the process of
And a fifth step of forming a gate electrode in the second recess. A method of manufacturing a thin film transistor according to claim 3,
The third step includes forming the semiconductor layer such that a surface of the semiconductor layer is substantially flush with the first main surface;
The fifth step includes forming the gate electrode so that the surface of the gate electrode is positioned substantially on the same plane as the second main surface. . A method for manufacturing a thin film transistor, comprising:
Forming a first recess having a narrow portion and a wide portion on the first main surface of the insulating substrate by using at least an imprint method;
A second step of forming a second recess at least on the second main surface opposite to the first main surface in the insulating substrate by using an imprint method;
A third step of forming a semiconductor layer in the narrow portion;
Forming a source electrode in the wide portion so as to partially overlap the semiconductor layer, and forming a drain electrode in the wide portion so as to partially overlap the semiconductor layer;
And a fifth step of forming a gate electrode in the second recess. A method of manufacturing a thin film transistor according to claim 5,
The fourth step includes
Forming the source electrode such that a surface of the source electrode is substantially coplanar with the first main surface;
Forming the drain electrode such that the surface of the drain electrode is substantially coplanar with the first main surface,
The fifth step includes forming the gate electrode so that the surface of the gate electrode is positioned substantially on the same plane as the second main surface. . An insulating substrate having a first main surface on which a first recess is formed, and a second main surface on the opposite side of the first main surface and on which a second recess is formed;
A semiconductor layer formed in the first recess;
A source electrode formed on the first main surface so as to partially overlap the semiconductor layer;
A drain electrode formed on the first main surface so as to partially overlap the semiconductor layer;
A thin film transistor comprising: a gate electrode formed in the second recess. The thin film transistor according to claim 7,
The surface of the semiconductor layer is substantially coplanar with the first main surface;
A thin film transistor, wherein a surface of the gate electrode is located substantially on the same plane as the second main surface. A first main surface on which a first recess having a narrow portion and a wide portion is formed; and a second main surface on the opposite side of the first main surface and on which a second recess is formed. An insulating substrate having,
A semiconductor layer formed in the narrow portion;
A source electrode formed in the wide portion so as to partially overlap the semiconductor layer;
A drain electrode formed in the wide portion so as to partially overlap the semiconductor layer;
A thin film transistor comprising: a gate electrode formed in the second recess. The thin film transistor according to claim 9,
The surface of the source electrode is substantially coplanar with the first main surface;
The surface of the drain electrode is also located substantially on the same plane as the first main surface,
A thin film transistor, wherein a surface of the gate electrode is located substantially on the same plane as the second main surface.

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