JP2013206508A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can detect whether or not a fuse storing address information of a defective memory cell is in a cut-off state, before a trimming step.SOLUTION: The semiconductor device comprises a test circuit 11 which outputs a test mode signal (fuse set selection test mode signals FSTM1 to FSTMn) to a fuse set circuit 12 when receiving a test address together with a test command, and causes the fuse set circuit to compare the test address with the address stored by the address specifying fuse and output address hit signals AH1 to AHn regardless of information stored by an enable fuse storing information indicating whether or not an address specifying fuse in the fuse set circuit 12 is used.

Description

  The present invention relates to a semiconductor device.

  In a wafer test of a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective memory cell in a main area is replaced with a normal memory cell (redundant memory cell) in a redundant area, and the defective memory cell is repaired. . In order to perform this replacement, the semiconductor device has an addressing fuse that programs a relief address (address of a defective memory cell) and an enable fuse that stores information indicating whether or not the addressing fuse is used. Equipped with a fuse set. In the wafer trimming process, for the fuse set including the addressing fuse and the enable fuse, a wiring layer constituting each fuse is blown from the opening on the fuse of the semiconductor device using a laser beam. . Then, it is determined whether each fuse has been cut or remains uncut.

A general DRAM includes a fuse set circuit having a plurality of fuse sets in order to relieve a plurality of defective memory cells or to relieve defective memory cells in units of row addresses or column addresses. In the fuse set in which the enable fuse is cut, the relief address is programmed in the addressing fuse. The fuse set circuit compares the external address with the relief address when accessing a normal memory cell.
Only when the external address coincides with the relief address, the corresponding redundant memory cell is selected, and the data writing from the outside of the DRAM or the data reading operation to the DRAM is performed. For example, Patent Document 1 discloses a technique for replacing a defective memory cell with a redundant memory cell using a fuse set circuit.

  Further, the DRAM has a check roll call function (hereinafter referred to as a CRC function) in order to confirm whether or not a redundant memory cell in the redundant area has been selected with respect to the DRAM after the trimming process. In the test mode using the CRC function, for example, the fuse set circuit compares the row address input by the act command (ACT command) after the transition to the test mode with the relief address. When the row address and the relief address match, for example, data indicating the match is output via the data input / output terminal DQ of the DRAM. The test mode using the CRC function is similarly performed for the column address input together with the read command (READ command) or the write command (WRITE command) following the ACT command by using the above configuration.

  That is, in the DRAM, the fuse set circuit is programmed with the external input address for the fuse set in which the enable fuse is blown out of the plurality of fuse sets mounted corresponding to the row address or the column address, respectively. Compare with the relief address. When both addresses match in the fuse set, the fuse set circuit outputs an address hit signal indicating that they match. This address hit signal is output as an H level signal from the data input / output terminal DQ via an input / output circuit, for example. On the other hand, if both addresses do not match in the fuse set, an address hit signal indicating that they do not match is output. This address hit signal is output as an L level signal via the input / output circuit.

JP 2009-33029 A

  Conventionally, it has been checked whether a desired fuse is blown by the following steps. First, in the first wafer test process prior to the trimming process, the address of the defective memory cell (address to be relieved) is detected. Next, in the trimming step, the address (relief address) of the defective memory cell is programmed into the addressing fuse of the fuse set. Next, in the second wafer test process subsequent to the trimming process, the repair address programmed in the address setting fuse of the fuse set is detected using the CRC function. Then, the address to be repaired detected in the first wafer process and the repair address detected in the second wafer process are compared, and it is determined whether or not the desired fuse has been blown correctly.

  Conventionally, in the first wafer test process, data is written to and read from the redundant memory cell in the redundant area, and the redundant memory cell is not defective and is used as a replacement destination. I was checking if it was possible. However, no check has been made as to whether the fuse set can correctly program the relief address. For this reason, the resistance value of the fuse element constituting the fuse set may be a high resistance value due to, for example, process-to-process variation in the wafer manufacturing process. In such a case, it may be determined in the second wafer test process that a fuse set that was not the object of fusing in the trimming process is blown, and it may be determined that an incorrect program has been performed in the trimming process.

  In order to prevent this erroneous determination, in the first wafer process, for example, it is conceivable to check whether or not the fuse set can correctly program the relief address using the CRC function. However, in order to check using the CRC function, it is necessary to blow the enable fuse in the fuse set as described above. For this reason, before the trimming process, a check using the CRC function cannot be performed, and it is impossible to check a defect of each fuse set. That is, conventionally, there has been a problem that a fuse set that cannot be used for relief cannot be detected before the trimming process.

  The present invention includes an addressing fuse for storing an address of a defective memory cell, and an enable fuse for storing information indicating whether or not to use the addressing fuse. A fuse set circuit for indicating that a fuse for addressing is used, and outputting an address hit signal indicating a match when an externally input address and the address of the defective memory cell match, and a test command When a test address is input together, a test mode signal is output to the fuse set circuit, and regardless of the information stored in the enable fuse, the test address and the address stored in the addressing fuse And a test circuit for outputting the address hit signal by comparing A semiconductor device, characterized in that it comprises a.

  In the present invention, the test circuit outputs an address hit signal indicating that the test address matches the address stored in the addressing fuse to the fuse set circuit regardless of the information stored in the enable fuse. Let That is, if a check using the CRC function is performed before the trimming process, the fuse set circuit outputs an address hit signal. Thereby, it is possible to provide a semiconductor device capable of detecting whether or not a fuse for storing address information of a defective memory cell is in a cut state before the trimming process. Therefore, since a fuse set that cannot be used for relief can be detected before the trimming process, erroneous programming is not performed in the trimming process, and a decrease in yield in the wafer test can be suppressed.

1 is a block diagram showing a schematic configuration of a semiconductor device 10. FIG. 2 is a block diagram showing a configuration of a fuse set circuit 12 shown in FIG. It is a block diagram which shows schematic structure of the semiconductor device 10a. FIG. 4 is a block diagram showing a configuration of a fuse set circuit 12a and a test control circuit 13 shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a block diagram illustrating a schematic configuration of the semiconductor device 10. The circuit blocks shown in FIG. 1 are all formed on the same semiconductor chip made of single crystal silicon. Each circuit block includes a plurality of transistors such as a PMOS transistor (P-type channel MOS transistor) and an NMOS transistor (N-type channel MOS transistor). Also, the circles indicate pads as external terminals provided on the semiconductor chip.

  The semiconductor device 10 includes an address / command decoder circuit 5, an X decoder 6a, a Y decoder 6b, a memory cell array 7, an input / output circuit 8, a test circuit 11, a fuse set circuit 12, and an internal voltage generation circuit 9. The First, an outline of the semiconductor device 10 will be described.

  The semiconductor device 10 includes command terminals 1a to 1d, an address terminal 2, a data input / output terminal 3a, a data strobe terminal 3b, and power supply terminals 4a and 4b as external terminals. In addition, a clock terminal, a reset terminal, and the like are also provided, but these are not shown. In this specification, a signal having “/” at the end of the signal name means an inverted signal of the corresponding signal or a low active signal.

  The command terminals 1a to 1d are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a chip select signal / CS, and a write enable signal / WEN are supplied, respectively. A command signal CMD is constituted by a combination of signals input to these terminals. The command signal CMD is input to the address / command decoder circuit 5. The address / command decoder circuit 5 generates various internal command signals ICMD by holding and decoding the command signal CMD. The generated internal command signal ICMD is supplied to an X decoder 6a that is one of row-related control circuits and a Y decoder 6b that is a column-related control circuit.

  The address terminal 2 is a terminal to which an address signal ADD is supplied, and the supplied address signal ADD is input to the address / command decoder circuit 5. The address / command decoder circuit 5 latches the address signal ADD and outputs an internal address IADD according to the decoding result of the address / command decoder circuit 5. Of the internal address IADD, the row address is input to the X decoder 6a, and the column address is input to the Y decoder 6b.

  The memory cell array 7 has a plurality of memory cells at intersections of a plurality of sub-word lines, a plurality of bit lines, a word line, and a bit line. The memory cell array 7 has a redundant area including redundant memory cells that are accessed in place of the defective memory cells when there are defective memory cells in the main area and the main area.

  The X decoder 6 a is a circuit that selects any word line included in the memory cell array 7. The Y decoder 6 b is a circuit that selects one of the sense amplifiers included in the sense amplifier in the memory cell array 7. The sense amplifier selected by the Y decoder 6b is connected to a data amplifier (not shown), for example. This data amplifier further amplifies the read data amplified by the sense amplifier during the read operation, and outputs the read data to the input / output circuit 8 via the read / write bus. On the other hand, during the write operation, the write data input from the input / output circuit 8 via the read / write bus is amplified and output to the sense amplifier. X decoder 6a includes a redundant row driver for driving a redundant word line for selecting a redundant memory cell in the redundant area. Y decoder 6b includes a redundant column driver for conducting a redundant column switch that connects a redundant bit line connected to a redundant memory cell in the redundant area and a data amplifier.

  The data input / output terminal 3 a is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the input / output circuit 8. The input / output circuit 8 outputs the read data from the memory cell array 7 in parallel as read data DQ0-n to the data input / output terminal 3a during the read operation. Further, the input / output circuit 8 serially outputs the write data DQ0-n from the data input / output terminal 3a to the memory cell array 7 during the write operation. The number of data input / output terminals 3a is plural as shown in FIG. 1, but may be 4, 8, 16, or the like. Data strobe terminal 3b is a terminal for outputting data strobe signals DQS and / DQS output together with read data DQ0-n, and is connected to input / output circuit 8. This data strobe signal is a signal that serves as a reference when an external device connected to the semiconductor device 10 receives the read data DQ0-n. Data strobe signals DQS and / DQS are input to input / output circuit 8 together with write data DQ0-n. This data strobe signal is also a reference signal when the semiconductor device 10 receives the write data DQ0-n from an external device.

  The power supply terminals 4a and 4b are terminals to which an external voltage VDD and a ground voltage VSS are supplied, respectively. In this specification, the voltage between the external voltage VDD and the ground voltage VSS may be simply referred to as “external voltage VDD”. The power supply terminals 4a and 4b are connected to the internal voltage generation circuit 9, respectively. The external voltage VDD is supplied to the internal voltage generation circuit 9. The internal voltage generation circuit 9 includes, for example, a first internal voltage VODPP (for example, 1.6 V), a second internal voltage VPERI (for example, 1.2 V), and the operation of the memory cell array 7 as a plurality of internal voltages according to the role of the internal circuit. For example, a voltage VARY is generated. Each of these internal voltages is supplied to a corresponding internal circuit.

In the present embodiment, the semiconductor device 10 has a normal operation mode and a test operation mode.
In the normal operation mode, the following operation is performed. That is, an act command (ACT command) instructing selection of a word line is input to the address / command decoder circuit 5. Then, the address / command decoder circuit 5 takes in the row address simultaneously with this ACT command, and outputs the internal row address X to the fuse set circuit 12 as the internal address IADD. The fuse set circuit 12 compares the internal row address X with the relief address stored in the built-in fuse set, and if they match, sets one of the address hit signals AH1 to AHn to the high (H) level and the X decoder 6a. Output for. In the present embodiment, the fuse set circuit 12 includes a plurality of fuse sets, and each fuse set is provided corresponding to a redundant row driver in the X decoder 6a (details will be described later).
When one of the H level address hit signals AH1 to AHn is input, the X decoder 6a does not select the word line to be originally selected (the word line at the position specified by the external row address), but the redundant Select a row driver. The redundant row driver selects a memory cell connected to the redundant word line. As a result, replacement of the defective memory cell in the main area with the redundant memory cell in the redundant area is executed in units of rows.

  Further, following the ACT command, the address / command decoder circuit 5 receives a read command (READ command) for instructing reading of data from the memory cells or a write command (WRIT command) for instructing data writing to the memory cells. Entered. Then, the address / command decoder circuit 5 takes in the column address simultaneously with this READ command or WRIT command, and outputs the internal column address Y to the fuse set circuit 12 as the internal address IADD. The fuse set circuit 12 compares the internal column address signal Y with the relief address stored in the built-in fuse set. If they match, one of the address hit signals AH1 to AHn is set to H level to the Y decoder 6b. Output.

When one of the H level address hit signals AH1 to AHn is input, the Y decoder 6b does not select the bit line to be originally selected (the bit line at the position specified by the external column address), but the redundant Select a column driver. The redundant column driver selects a redundant bit line and connects it to the data amplifier. As a result, replacement of defective memory cells in the main area with redundant memory cells in the redundant area is executed in units of columns.
In the present embodiment, the fuse set circuit 12 includes a plurality of fuse sets, and each fuse set is provided corresponding to a redundant row driver in the X decoder 6a. Of course, the fuse set provided in the fuse set circuit 12 can be provided corresponding to the redundant column driver in the Y decoder 6b. In the present embodiment, in the following description, each fuse set included in the fuse set circuit 12 is provided corresponding to a redundant row driver. Details of the fuse set circuit 12 and the test circuit 11 will be described later.

Next, the test operation mode will be described. The semiconductor device 10 has a first test mode (redundant area check function) and a second test mode (CRC function) as test operation modes.
The first test mode can be used, for example, in a first wafer test performed before the trimming process. In the first test mode, the following operation is performed. In other words, a test command (TEST 1 command) indicating a shift to the test mode is input to the address / command decoder circuit 5. The address / command decoder circuit 5 activates the test circuit 11 in response to the TEST1 command. The test circuit 11 selectively sets one of the fuse set selection test mode signals FSTM1 to FSTMn, for example, the fuse set selection test mode signal FSTMj (j = 1 to n) to the H level to the fuse set circuit 12. Output. In order to selectively set the fuse set selection test mode signal FSTMj to the H level, the address / command decoder circuit 5 has a mode register, for example. At the same time that the TEST1 command is fetched into this mode register, the address for selecting the fuse set in the fuse set circuit 12 from the address terminal, for example, 4-bit data continuous from the least significant (X0) bit side of the row address It is. Based on the 4-bit data, test circuit 11 sets fuse set selection test mode signal FSTMj to H level and maintains this state.

  Further, the address / command decoder circuit 5 takes in the ACT command and the row address (all-low (L) level) following the test command TEST1, and uses the internal row address X = # 0000 as the internal address IADD to the fuse set circuit 12. Output. The fuse set circuit 12 compares the internal row address X with the address stored in the built-in fuse set. At this time, if the fuse is normal, that is, in this case, it is not blown, the address stored in the fuse set is all L, and both addresses match.

  As a result, the fuse set circuit 12 outputs one address hit signal AHj (j = 1 to n) of the address hit signals AH1 to AHn to the H level and outputs it to the X decoder 6a. The X decoder 6a selects a redundant row driver corresponding to the fuse set of the fuse set circuit 12 instead of selecting the word line to be originally selected (the word line at the position specified by the internal row address X = # 0000). The redundant row driver selects a memory cell connected to the redundant word line. When a WRIT command is supplied following the ACT command, data is written from the outside to the memory cells in the redundant area. Also, if the commands are input in the order of the TEST1 command, the ACT command, and the READ command, the data written in the memory cell in the redundant area is read, and whether the memory cell in the redundant area is a normal memory cell. It can be determined whether or not.

  As a result, if all the redundant memory cells in the redundant area are non-defective memory cells, it is possible to determine whether or not replacement may be performed in units of rows when there are defective memory cells in the memory area. it can. Note that a test for selecting all redundant row drivers, that is, n redundant row drivers, is performed as follows. That is, the combination of the TEST1 command, the ACT command, the READ command, or the WRIT command described above is executed while changing the row address fetched together with the ACT command (redundancy area check function).

  The second test mode can be used, for example, in a first wafer test performed before the trimming process. In the second test mode, the following operation is performed. That is, a test command (TEST2 command) indicating a shift to the test mode is input to the address / command decoder circuit 5. The address / command decoder circuit 5 activates the test circuit 11 by this TEST2 command. The test circuit 11 selectively outputs one selection test mode signal FSTMj (j = 1 to n) of the fuse set selection test mode signals FSTM1 to FSTMn as the H level to the fuse set circuit 12.

  Note that the fuse set selection test mode signal FSTMj can be selectively set to the H level in the same manner as in the TEST1 command. That is, the address / command decoder circuit 5 includes, for example, a mode register. The mode register captures the 4-bit data continuous from the least significant (X0) bit side of the row address, for example, the address when selecting the fuse set in the fuse set circuit 12 from the address terminal simultaneously with the capture of the TEST2 command. . Based on the 4-bit data, test circuit 11 sets fuse set selection test mode signal FSTMj to H level and maintains this state.

  The address / command decoder circuit 5 takes in the ACT command and the row address (all-low (L) level) following the test command TEST2. The address / command decoder circuit 5 outputs the internal row address X = # 0000 (test address) as the internal address IADD to the fuse set circuit 12, and maintains this H level state. The fuse set circuit 12 compares the internal row address X with the address stored in the built-in fuse set. At this time, if the fuse is normal, that is, not blown, the address stored in the fuse set is all L, and both addresses coincide. As a result, the fuse set circuit 12 outputs the address hit signal AHj to the input / output circuit 8 as the H level.

  That is, when the selection test mode signal FSTMj is input from the test circuit 11, the fuse set circuit 12 determines whether or not the address stored in each fuse set matches the internal row address X = # 0000. If they match, the fuse set circuit 12 outputs an address hit signal AHj to the input / output circuit 8. Thereby, the input / output circuit 8 outputs a signal (DQ signal) indicating whether or not each fuse set in the fuse set circuit 12 is in an unblown state from any one of the data input / output terminals 3a. In this embodiment, when it is determined that all the fuses in the fuse set are in an unblown state, the address hit signal AHj is at the H level, and the input / output circuit 8 outputs an H level DQ signal.

  On the other hand, when it is determined that at least one fuse in the fuse set is in a blown state, the address hit signal AHj is at the L level, and the input / output circuit 8 outputs the DQ signal at the L level. These DQ signals are signals indicating whether or not the fuse should be cut in the trimming process. Therefore, the redundant row driver can be prevented from being unnecessarily used by removing the fuse set determined to be in a blown state from the blown target in the trimming process based on the logic of the DQ signal. Note that a test for selecting all fuse sets, that is, n fuse sets that output an address hit signal, is executed as follows. That is, the combination of the TEST2 command and the ACT command described above is executed while changing the row address fetched together with the TEST2 command (CRC function).

Next, the fuse set circuit 12 that is a characteristic part of the semiconductor device 10 of the present invention will be described in detail. FIG. 2 is a block diagram showing a configuration of fuse set circuit 12 shown in FIG.
The fuse set circuit 12 includes a plurality of fuse sets 12_1 to 12_n (n ≧ 1). Each fuse set is provided in a one-to-one correspondence with each of n redundant row drivers (not shown in FIGS. 1 and 2) in the X decoder 6a. The fuse set 12_i (i = 1 to n) has the same configuration as the fuse set 12_1 shown in FIG. Therefore, the configuration of the fuse set 12_1 will be described, and the description of the configuration of the fuse sets 12_2 to 12_n will be omitted.

  The fuse set 12_1 includes an enable fuse EF12_1, address comparison circuits C12_1_0 to C12_1_13, X = 0 fuse (referred to as a fuse circuit F12_1_0) to X = 13 fuse (referred to as a fuse circuit F12_1_13). The fuse set 12_1 includes an OR circuit OR12_1, NAND circuits NA12_1_1 to NA12_1_4, NOR circuits NO12_1_1 to 12_1_2, and an AND circuit A12_1.

  The enable fuse EF12_1 includes a fuse element that can be blown by a laser. When the fuse circuit F12_1_0 to F12_1_13 is used, the fuse element is blown in the trimming process and stores that the fuse element of the fuse circuit F12_1_0 to the fuse circuit F12_1_13 is used. Note that in the case where all the row addresses are stored in an L level state, none of the fuse elements of the fuse circuits F12_1_0 to F12_1_13 are blown. However, it is used as a fuse element, and the fuse element of the enable fuse EF12_1 is blown. In the present embodiment, when the fuse element of the enable fuse EF12_1 is blown (when blown), the enable fuse EF12_1 outputs an H level signal to the OR circuit OR12_1. On the other hand, if the fuse element is not blown (if it is not blown), the enable fuse EF12_1 outputs an L level signal to the OR circuit OR12_1.

  Each of the fuse circuits F12_1_0 to F12_1_13 includes a fuse element that can be blown by a laser, like the enable fuse EF12_1. The fuse element is blown in a trimming process corresponding to an address indicating a position of a word line for selecting a defective memory cell in the main area. That is, each of the fuse circuits F12_1_0 to F12_1_13 stores the row address of the defective memory cell bit by bit.

  Each of the address comparison circuits C12_1_0 to C12_1_13 (address comparison circuit C12_1_i, i = 0 to 13) compares the i bit of the internal address IADD with the row address stored in the fuse circuit F12_1_i. Each of the address comparison circuits C12_1_0 and C12_1_1 outputs an H level signal to the next stage NAND circuit NA12_1_1 when both addresses match, and outputs an L level signal to the next stage NAND circuit when both addresses do not match. Output to NA12_1_1. Each of the address comparison circuits C12_1_2 to C12_1_5 outputs an H level signal to the next NAND circuit NA12_1_2 when both addresses match, and outputs an L level signal to the next NAND circuit when both addresses do not match. Output to NA12_1_2. Each of the address comparison circuits C12_1_6 to C12_1_9 outputs an H level signal to the next NAND circuit NA12_1_3 when both addresses match, and outputs an L level signal to the next NAND circuit when both addresses do not match. Output to NA12_1_3. Each of the address comparison circuits C12_1_10 to C12_1_13 outputs an H level signal to the next-stage NAND circuit NA12_1_3 when both addresses match. On the other hand, each of the address comparison circuits C12_1_10 to C12_1_13 outputs an L level signal to the next-stage NAND circuit NA12_1_3 when both addresses do not match.

The NOR circuit NO12_1_1 calculates a negative logical sum of output signals of the NAND circuit NA12_1_1 and the NAND circuit NA12_1_2, and outputs the result to the AND circuit A12_1 in the next stage. The NOR circuit NO12_1_2 calculates a negative logical sum of the output signals of the NAND circuit NA12_1_3 and the NAND circuit NA12_1_4, and outputs the result to the AND circuit A12_1 in the next stage.
The AND circuit A12_1 calculates the logical product of the output signals of the NOR circuit NO12_1_1 and the NOR circuit NO12_1_2, and outputs an address hit signal AH1.

  In the normal operation mode, when an ACT command is input to the address / command decoder circuit 5, the address / command decoder circuit 5 captures a row address simultaneously with the ACT command. The address / command decoder circuit 5 outputs the internal row address X to the fuse set circuit 12 as the internal address IADD. The fuse set circuit 12 compares the internal row address X and the relief address stored in the fuse set, and if they match, the address hit signal among the address hit signals AH1 to AHn is set to H level to the X decoder 6a. Output.

When an address hit signal at H level is input, the X decoder 6a selects a redundant row driver instead of selecting a word line to be originally selected, and the redundant row driver selects a memory cell connected to the redundant word line. select. Thereby, replacement of the defective memory cell in the main area with the memory cell in the redundant area is executed in units of rows.
Note that the fuse set circuit 12 compares the internal row address X and the relief address stored in the fuse set, and maintains the address hit signals AH1 to AHn at the L level if they do not match. The X decoder 6a selects a word line to be originally selected, and selects a memory cell connected to the word line. As a result, the memory cell in the main area is selected.

  In the first test mode, when the TEST 1 command is input to the address / command decoder circuit 5, the address / command decoder circuit 5 activates the test circuit 11. Further, the address / command decoder circuit 5 takes in an address when selecting a fuse set in the fuse set circuit 12 from the address terminal simultaneously with taking in the TEST1 command. The address / command decoder circuit 5 takes in, for example, 4-bit data (for example, all 0s) continuous from the least significant (X0) bit side of the row address. Based on the 4-bit data, the test circuit 11 sets, for example, the fuse set selection test mode signal FSTM1 to the H level and maintains this state.

  Further, the address / command decoder circuit 5 takes in the ACT command and the row address (all-low (L) level) following the test command TEST1, and, for example, uses the internal row address X = # 0000 as the internal address IADD to the fuse set circuit 12. Output. The fuse set 12_1 in the fuse set circuit 12 compares the internal row address X with the address stored in the built-in fuse set. At this time, if the fuse is normal, that is, not blown, the address stored in the fuse set is all L, and both addresses coincide.

  As a result, the fuse set circuit 12 outputs the address hit signal AH1 to the X decoder 6a as the H level. The X decoder 6a selects a redundant row driver corresponding to the fuse set of the fuse set circuit 12 instead of selecting the word line to be originally selected (the word line at the position specified by the internal row address X = # 0000). The redundant row driver selects a memory cell connected to the redundant word line. When a WRIT command is supplied following the ACT command, data is written from the outside to the memory cells in the redundant area.

  Also, if the commands are input in the order of the TEST1 command, the ACT command, and the READ command, the data written in the memory cell in the redundant area is read, and whether the memory cell in the redundant area is a normal memory cell. It can be determined whether or not. Thus, if all the memory cells in the redundant area are normal memory cells, it is possible to determine whether or not replacement may be performed in units of rows when there is a defective memory cell in the memory area ( Redundant area check function).

On the other hand, if any one of the fuses in the fuse set 12_1 is in a blown state, the address stored in the fuse set is not all L, and the addresses do not match.
As a result, the fuse setting circuit 12 maintains the address hit signal AH1 at the L level. The X decoder 6a selects a word line to be originally selected (a word line at a position specified by the internal row address X = # 0000), and selects a memory cell connected to the word line. At this time, it is preferable that data (for example, “1”) opposite to the data written in the redundant word line is previously written in the memory cell connected to the word line by a normal write operation. The reason for this will be described below.

  That is, when the WRIT command is supplied following the ACT command, “0” is written to the redundant memory cell as data from the outside, assuming that the memory cell in the redundant area is selected. In addition, the commands are input in the order of the TEST1 command, the ACT command, and the READ command. Then, “0” as data written to the memory cell in the redundant area should be read out to the outside of the semiconductor device 10 as an expected value. However, in actuality, a memory cell connected to a word line to be originally selected (a word line at a position specified by internal row address X = # 0000) is selected, and “1” is read out of the semiconductor device 10 as data. . This also makes it possible to indirectly determine whether any one of the fuses in the fuse set 12_1 is in the blown state via the memory cell array 7, but it is easier to check whether the fuse is in the blown state. Therefore, the semiconductor device 10 has the second test mode.

  In the second test mode, when the TEST2 command is input to the address / command decoder circuit 5, the address / command decoder circuit 5 activates the test circuit 11. The test circuit 11 changes one selection test mode signal FSTMj (j = 1 to n) of the fuse set selection test mode signals FSTM1 to FSTMn to the H level according to the row address fetched simultaneously with the TEST2 command. Test circuit 11 outputs selected test mode signal FSTMj to fuse set circuit 12.

  The address / command decoder circuit 5 takes in the ACT command and the row address (all-low (L) level) following the test command TEST2. The address / command decoder circuit 5 outputs the internal row address X = # 0000 (test address) as the internal address IADD to the fuse set circuit 12, and maintains this H level state. The fuse set 12_1 in the fuse set circuit 12 compares the internal row address X with the address stored in the built-in fuse set. At this time, if the fuse is normal, that is, not blown, the address stored in the fuse set 12_1 is all L, and the two addresses match. As a result, the fuse set circuit 12 outputs the address hit signal AHj to the input / output circuit 8 as the H level.

  Note that a test for selecting all fuse sets, that is, n fuse sets that output an address hit signal, is executed as follows. That is, the combination of the TEST2 command and the ACT command described above is executed while changing the row address fetched together with the TEST2 command and fixing the row address fetched together with the ACT command to all L levels. When the selected test mode signal FSTMj is input from the test circuit 11, the fuse set circuit 12 determines whether the address stored in the fuse set 12_j matches the internal row address X = # 0000. If they match, the fuse set circuit 12 outputs an address hit signal AHj at H level to the input / output circuit 8.

  Thereby, the input / output circuit 8 outputs a signal (DQ signal) indicating whether or not each fuse set in the fuse set circuit 12 is in an unblown state from any one of the data input / output terminals 3a. When the fuse set circuit 12 determines that all the fuses in each fuse set are in an unfused state, the fuse set circuit 12 outputs an H level address hit signal AHj, and the input / output circuit 8 outputs an H level DQ signal. .

  On the other hand, if it is determined that at least one fuse is in a blown state in each fuse set, the fuse set circuit 12 outputs an L level address hit signal AHj, and the input / output circuit 8 outputs an L level DQ signal. Is output. The DQ signal output from these input / output circuits 8 is a signal indicating whether or not the fuse should be cut in the trimming process. Therefore, when the DQ signal corresponding to the fuse set in the fuse set circuit 12 is at the L level, it can be determined that the fuse element in the fuse set is in a blown state although it is not trimmed. As a result, by removing this fuse set from the target for fusing in the trimming process, it is possible to prevent the redundant row decoder from being used unnecessarily (CRC function).

[Second Embodiment]
In the second embodiment, an example will be described in which the mode is shifted to the second test mode described above, the CRC function is enabled, the mode is shifted to the first test mode, and the redundant area check function is enabled.
FIG. 3 is a block diagram showing a schematic configuration of the semiconductor device 10a. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

  First, in order to shift to the second test mode, when a TEST2 command is input to the address / command decoder circuit 5, the address / command decoder circuit 5 controls the test circuit 11a. The test circuit 11a sets the fuse circuit selection test signal FST to the H level and outputs it to the test control circuit 13.

Next, in order to shift to the first test mode, when the TEST1 command is input to the address / command decoder circuit 5, the address / command decoder circuit 5 controls the test circuit 11a. The test circuit 11a sets the redundant row area selection test signal RAST to the H level and outputs it to the test control circuit 13. The test control circuit 13 forcibly generates an internal row address X = # 0000 (test address) as a row address to be input to the address comparison circuit in the fuse set in the fuse set circuit 12a, and to the fuse set circuit 12a. Output.
Each fuse set in the fuse set circuit 12a compares the internal row address X with the address stored in the built-in fuse set. If the fuse is not blown at this time, the address stored in the fuse set is all L, and both addresses match.

The address / command decoder circuit 5 takes in the ACT command and the row address following the TEST1 test command, and outputs the internal address IADD to the test control circuit 13.
The test control circuit 13 decodes 4-bit data continuous from the least significant (X0) bit side of the internal address IADD as an address when selecting a fuse set in the fuse set circuit 12a, and the fuse set circuit 12a Select one of the fuse sets.

  As a result, the fuse set circuit 12a outputs any one of the address hit signals AH1 to AHn as the H level to the X decoder 6a. The X decoder 6a selects a redundant row driver corresponding to the fuse set of the fuse set circuit 12a, and the redundant row driver selects a memory cell connected to the redundant word line. When a WRIT command is supplied following the ACT command, data is written from the outside to the memory cells in the redundant area.

  When the commands are input in the order of the TEST2 command, the TEST1 command, the ACT command, and the READ command, the data written in the memory cell in the redundant area is read out. Based on this data, it is possible to determine whether or not the memory cell in the redundant area is a normal memory cell. Thus, if all the memory cells in the redundant area are normal memory cells, it is possible to determine whether or not replacement may be performed in units of rows when there is a defective memory cell in the memory area ( Redundant area check function).

  In addition, the input / output circuit 8 outputs a signal (DQ signal) indicating whether or not each fuse set in the fuse set circuit 12a is in an unblown state in series (serial), for example, by adding to the read data. To do. Thereby, in addition to the signal indicating whether or not the redundant area corresponding to the fuse set can be used, a signal indicating whether or not the fuse set is subject to fusing in the trimming process can be output (CRC function).

Subsequently, in the second embodiment, the fuse set circuit 12a and the test control circuit 13 which are characteristic portions of the semiconductor device 10a of the present invention will be described in detail. FIG. 4 is a block diagram showing the configuration of the fuse set circuit 12a and the test control circuit 13 shown in FIG. In FIG. 4, the same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.
The test control circuit 13 includes an AND circuit A13, an inverter circuit I13, an address generation circuit for address comparison circuit 13a, and a fuse set selection decoding circuit D13. The address comparison circuit address generation circuit 13a includes AND circuits A13a_0 to A13a_13.

The AND circuit A13 calculates the logical product of the fuse circuit selection test signal FST, which is an output signal of the test circuit 11a, and the redundant row area selection test signal RAST, and outputs the logical product to the inverter circuit I13 and the fuse set selection decoding circuit D13. To do.
The inverter circuit I13 logically inverts the output signal of the AND circuit A13 and outputs it to the AND circuits A13a_0 to A13a_13.
When the output signal of the AND circuit A13 is at the H level, the address generation circuit for address comparison circuit 13a sends the internal row address X = # 0000 (test address) to the fuse set circuit 12 regardless of the value of the internal address IADD. Output. That is, the address generation circuit for address comparison circuit 13a outputs the internal row address X = # 0000 to the fuse set circuit 12 when the fuse circuit selection test signal FST and the redundant row area selection test signal RAST become H level. .

  That is, when the mode is shifted to the second test mode, the CRC function is enabled, and then the mode is shifted to the first test mode, all the internal row addresses inputted to the address comparison circuit are at the L level. In other words, the internal row address input to the address comparison circuit of the fuse set circuit 12a is an L level signal that is the same as the signal level that should be output if the fuse elements in the fuse set are normal, that is, not blown. As a result, if the fuse elements in the fuse set are normal, that is, not blown, all inputs of the four NAND circuits in each fuse set are at the H level except for output signals from the OR circuit.

  Further, the fuse circuit selection test signal FST and the redundant row area selection test signal RAST are at H level. Thereafter, an address for selecting a fuse set in the fuse set circuit 12a is input to the fuse set selection decoding circuit D13 as an internal address IADD together with the ACT command. The fuse set selection decoding circuit D13 decodes 4-bit data continuous from the least significant (X0) bit side, and outputs an H level signal to one input of the OR circuit in each fuse set. That is, the test control circuit 13 selects one fuse set from the fuse sets 12_1 to 12_13 in the fuse set circuit 12a according to the row address input together with the ACT command.

  Accordingly, as described in the first embodiment, the redundant area check function and the CRC function can be enabled by inputting the TEST2 command, the TEST1 command, and the ACT command in this order. Further, in the first embodiment, it is necessary to output n signals (fuse set selection test mode signals FSTM1 to FSTMn) output from the test circuit 11 corresponding to each fuse set of the fuse set circuit 12. On the other hand, in the second embodiment, a single signal (fuse circuit selection test signal FST) output from the test circuit 11a to the test control circuit 13 may be output. That is, since n test signals can be reduced to one test signal, the number of test signal generation circuits and test signal wirings can be reduced as compared with the first embodiment, and the area required for these can be reduced. The chip size can be reduced.

  The operation of the test control circuit 13 in the normal operation mode is as follows. That is, in the normal operation mode, the output signal of the AND circuit A13 is L level, and the fuse set selection decode circuit D13 outputs an L level output signal to the OR circuit in each fuse set. Further, the output signal of the inverter circuit I13 is at the H level, and the address comparison circuit address generation circuit 13a outputs the internal address IADD as it is as a row address signal to each address comparison circuit.

  Thereby, each fuse set in the fuse set circuit 12a changes one address hit signal among the address hit signals AH1 to AHn to the H level according to the information stored in the enable fuse and the address information stored in the relief address fuse. . The fuse setting circuit 12a outputs an H level address hit signal to the X decoder 6a. In other words, in the normal operation mode, row-by-row replacement from the main area to the redundant area is performed as described in the first embodiment.

  As described above, the semiconductor device 10 includes an addressing fuse (fuse circuit F12_1_0 to F12_1_13) that stores the address of the defective memory cell and an enable fuse (enable) that stores information indicating whether or not to use the addressing fuse. A fuse set circuit 12 having a fuse EF12_1). The fuse set circuit 12 indicates that the information of the enable fuse indicates that the addressing fuse is used, and if the address input from the outside matches the address of the defective memory cell, the address hit signal indicating the match AH is output. The semiconductor device 10 also includes a test circuit that performs the following operation when a test address (internal row address X = # 0000) is input together with a test command (TEST2 command). That is, a test mode signal (fuse set selection test mode signals FSTM1 to FSTMn or a fuse circuit selection test signal FST) is output to the fuse set circuit 12, regardless of the information stored in the enable fuse (enable fuse EF12_1, etc.). The test circuit 11 or the test circuit 11a outputs the address hit signal AH by comparing the test address with the address stored in the addressing fuse.

  Thus, in the present invention, the test circuit causes the address hit indicating that the test address matches the address stored in the addressing fuse to the fuse set circuit regardless of the information stored in the enable fuse. Output a signal. That is, before the trimming process, if the check is performed using the CRC function with the external input address set to L level, for example, as an expected value when the addressing fuse is not blown, the fuse set circuit outputs an address hit signal. Output. Thereby, it is possible to provide a semiconductor device capable of detecting whether or not a fuse for storing address information of a defective memory cell is in a cut state before the trimming process. Therefore, since a fuse set that cannot be used for relief can be detected before the trimming process, erroneous programming is not performed in the trimming process, and a decrease in yield in the wafer test can be suppressed.

The technical idea of the present application can be applied to a semiconductor device having a memory function. Furthermore, the circuit format in each circuit block disclosed in the drawings and other circuits for generating control signals are not limited to the circuit format disclosed in the embodiments.
Further, the technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. For example, in general semiconductor devices such as CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), ASSP (Application Specific Standard Product), and memory (Memory), The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), POP (package on package), and the like. The present invention can be applied to a semiconductor device having any of these product forms and package forms.
The transistor may be a field effect transistor (FET), and may be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). it can. It can be applied to various FETs such as transistors. Furthermore, some bipolar transistors may be included in the device.
Further, the NMOS transistor (N-type channel MOS transistor) is a representative example of the first conductivity type transistor, and the PMOS transistor (P-type channel MOS transistor) is a representative example of the second conductivity type transistor.
Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention includes various modifications and corrections that can be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

  DESCRIPTION OF SYMBOLS 10, 10a ... Semiconductor device, 5 ... Address / command decoder circuit, 6a ... X decoder, 6b ... Y decoder, 7 ... Memory cell array, 8 ... Input / output circuit, 9 ... Internal voltage generation circuit, 1a ... Command terminal, 2 ... Address terminal, 3a ... data input / output terminal, 4a ... power supply terminal, 11, 11a ... test circuit, 12, 12a ... fuse set circuit, 13 ... test control circuit, 12_1 ... fuse set, EF12_1 ... enable fuse, C12_1_0 ... address comparison Circuit, F12_1_1 ... fuse circuit, OR12_1 ... OR circuit, NA12_1_1 ... NAND circuit, NO12_1_1 ... NOR circuit, A12_1, A13, A13a_0 ... AND circuit, I13 ... inverter circuit, 13a ... address generation circuit for address comparison circuit, D13 ... fuse set Selection Over de circuit, IADD, X, Y ... internal address, ICMD ... internal command signal, FSTM1 ... fuse set selection test mode signal, AH1 ... address hit signal, FST ... fuse circuit selection test signal, RAST ... redundant row area selection test signal

Claims (4)

An addressing fuse for storing an address of a defective memory cell; and an enable fuse for storing information indicating whether or not to use the addressing fuse. The information for the enable fuse is used for the addressing fuse. And a fuse set circuit that outputs an address hit signal indicating a match when the address input from the outside matches the address of the defective memory cell, and
When a test address is input together with a test command, a test mode signal is output to the fuse set circuit, and the test address and the addressing fuse are stored regardless of the information stored in the enable fuse. A test circuit for comparing the address and outputting the address hit signal;
A semiconductor device comprising: The fuse set circuit includes a plurality of fuse sets,
An input / output circuit that outputs the address hit signal output from each of the plurality of fuse sets to the outside of the semiconductor device;
The semiconductor device according to claim 1, wherein the test circuit selectively outputs the test mode signal to each of the plurality of fuse sets. The address of the defective memory cell stored in the fuse set is a row address indicating a position of the memory cell in the semiconductor device, or a column address,
A redundant row driver or a redundant column driver for selecting a redundant memory cell used for replacement of the defective memory cell;
The redundant row driver or redundant column driver is provided corresponding to each of the plurality of fuse sets.
The semiconductor device according to claim 2. According to the test signal input from the test circuit,
A test control circuit that outputs the test address as the row address or the column address to the plurality of fuse sets and selectively outputs the test mode signal to the plurality of fuse sets. ,
The semiconductor device according to claim 3.

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