JP2013201387A - Three-dimensional transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a three-dimensional transistor that allows reducing the influence of lateral-direction growth due to facet formation and film thickness variation of an epitaxial layer at a pattern edge associated with selective epitaxial silicon growth.SOLUTION: A three-dimensional transistor includes: a semiconductor substrate having a top surface in which a crystal plane direction is (100); an element isolation region formed in the semiconductor substrate and partitioning an element region on the top surface; a gate electrode formed on the element region of the semiconductor substrate via a gate insulating film and in which gate insulating side walls are provided on side surfaces; a source/drain region formed in the element region of the semiconductor substrate in a self-alignment manner with respect to the gate electrode; and a selective epitaxial silicon layer formed on the source/drain region by epitaxial growth. A first side surface portion of the selective epitaxial silicon layer on the element isolation region side has a curved surface shape.

Description

  Embodiments described herein relate generally to a three-dimensional transistor and a manufacturing method thereof.

  In recent years, due to the demand for miniaturization of semiconductor integrated circuits such as logic circuits and memories, various technological developments have been continued toward the realization of miniaturization to MIS (Metal Insulator Transistor) type field effect transistors used as switching elements and drivers. ing.

  In particular, with the miniaturization of the gate length, various ideas have been made to realize a high current driving capability while suppressing the short channel effect. In DRAMs (Dynamic Random Access Memory) with half-pitch 40nm or 50nm generation, planar transistors (hereinafter referred to as SEG type planar transistors) that combine RCAT (Recess Channel Array Transistor) or selective epi growth (SEG) technology as selected cell transistors. It is mainly used.

  Currently, current write type nonvolatile RAMs include MRAM (Magnetic Random Access Memory) and RRAM (Resistance Random Access Memory), which are being developed to realize universal memory. In this current writing type non-volatile RAM, a high-density cell array transistor can be realized at the same time as a DRAM, as well as a DRAM.

  In the case of the RCAT described above, an effective gate length can be increased by digging a silicon substrate, which is effective in suppressing off current. However, RCAT has a problem that it is difficult to dramatically increase the current drive capability. This problem is one of the obstacles in applying to the universal memory.

  On the other hand, a SEG (Selective Epitaxic Growth) type planar transistor is formed in a silicon crystal layer shape in which a source / drain region is lifted by selective epitaxial growth. For this reason, the SEG type planar transistor may be able to realize a high current driving capability while suppressing the short channel effect even with a fine gate length.

  Therefore, the SEG type planar transistor is one option for the cell selection transistor in the universal memory.

J.Y.Kim, “The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm feature size and beyond”, 2003 Symposium on VLSl Technology Digest at Technical Papers, P.11-12. Y.K. Park, “Fully Integrated 56 nm DRAM Technology for 1Gb DRAM”, 2007 Symposium on VLSI Technology Digest of Technical Papers, P.190-191.

  Provided are a three-dimensional transistor capable of reducing the influence of lateral growth by facet formation accompanying selective epitaxial silicon growth and film thickness fluctuation of an epitaxial layer at a pattern edge, and a method for manufacturing the same.

  The three-dimensional transistor according to the embodiment includes a semiconductor substrate having an upper surface whose crystal plane orientation is (100). The three-dimensional transistor includes an element isolation region formed on the semiconductor substrate and defining an element region on the upper surface. The three-dimensional transistor includes a gate electrode formed on the element region of the semiconductor substrate via a gate insulating film and having a gate insulating side wall provided on a side surface. The three-dimensional transistor includes a source / drain region formed in the element region of the semiconductor substrate in a self-aligned manner with respect to the gate electrode. The three-dimensional transistor includes a selective epitaxial silicon layer formed by epitaxial growth on the source / drain regions. The first side surface portion on the element isolation region side of the selective epitaxial silicon layer has a curved surface shape.

FIG. 1 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the first embodiment. 2 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the first embodiment, which is subsequent to FIG. FIG. 3 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the first embodiment, which is subsequent to FIG. FIG. 4 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the second embodiment. FIG. 5 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the third embodiment. FIG. 6 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the third embodiment, which is subsequent to FIG. FIG. 7 is a cross-sectional view showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 4 when the crystal plane orientation of the main surface of the element region is (110). FIG. 8 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the fourth embodiment when the crystal plane orientation of the main surface of the element region is (110) following FIG. FIG. 9 is a cross-sectional view showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 4 when the crystal plane orientation of the main surface of the element region is (100). FIG. 10 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the fourth embodiment when the crystal plane orientation of the main surface of the element region is (100) following FIG. 9. FIG. 11 is a cross-sectional view showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 5 when the crystal plane orientation of the main surface of the element region is (110). FIG. 12 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the fifth embodiment when the crystal plane orientation of the main surface of the element region is (110) following FIG. FIG. 13 is a cross-sectional view showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 5 when the crystal plane orientation of the main surface of the element region is (100). 14 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to Example 5 in the case where the crystal plane orientation of the main surface of the element region is (100), following FIG. 13.

  For example, an SEG type planar transistor is used as a cell selection transistor in the universal memory. In this case, a selective epitaxial growth (SEG) layer is simultaneously formed in peripheral transistors used in the peripheral circuit. For this reason, it is necessary to design a device corresponding to this SEG layer, and in that case, several problems occur.

  First, facets are formed on the surface of the epitaxial silicon layer during selective epi growth, SEG layers are formed in the vertical and horizontal directions, and extend on the element isolation oxide film that separates the peripheral transistors.

  The SEG layer has a minimum required film thickness from the viewpoint of suppressing the short channel effect and suppressing the influence of junction leakage to the substrate when the contact layer is formed on the SEG layer. The SEG layer extends in the lateral direction by the thickness. This extended portion becomes an obstacle in suppressing the element isolation region width.

  Similarly, the film thickness of the SEG layer at the end of the gate electrode tends to be thinner than other regions due to the influence of facets. Therefore, when deep implantation is performed over the SEG layer, deep implantation is deeper at the edge of the gate electrode that has the greatest influence on suppression of the shortest channel effect. This becomes a problem in device design.

  Therefore, in the following embodiments, a three-dimensional transistor capable of reducing the influence of lateral growth due to facet formation accompanying selective epitaxial silicon growth and fluctuations in the thickness of the epitaxial layer at the pattern edge and a manufacturing method thereof are proposed.

  Hereinafter, each embodiment will be described with reference to the drawings.

  First, an example of a method for manufacturing a three-dimensional transistor according to Example 1 will be described.

  1 to 3 are cross-sectional views illustrating an example of each step of the method of manufacturing the three-dimensional transistor according to the first embodiment.

  First, as shown in FIG. 1A, an element isolation region 2 for partitioning an element region is formed on a semiconductor substrate (silicon substrate, eg, silicon wafer) having an upper surface 1a having a crystal plane orientation of (100). . Then, ion implantation for wells and channels (not shown) is performed, and the wells are activated by annealing.

  Next, as shown in FIG. 1B, a gate insulating film 10, a gate electrode material (polysilicon 3a, tungsten 3b), and a cap insulating film (SiN) 12 are sequentially formed on the entire surface of the semiconductor substrate 1, The gate electrode 3 is formed using lithography and RIE techniques. That is, the gate electrode 3 is formed on the element region of the semiconductor substrate 1 via the gate insulating film 10.

  Thereafter, a gate insulating side wall (SiN spacer) 11 having a thickness of, for example, about 5 nm is formed on the side surface of the gate electrode 3 by CVD and RIE.

  Next, for the purpose of suppressing the short channel effect, for example, ions are implanted through the gate insulating side wall 11 at an angle of about 30 degrees to form a diffusion layer. Thereafter, ion implantation is performed for the purpose of reducing the resistance of the portion where the gate electrode 3 and the diffusion layer overlap.

  That is, as shown in FIG. 2, source / drain regions (low-concentration diffusion layers) 4 are formed on the element region in a self-aligned manner with respect to the gate electrode 3.

  Next, after the surface treatment of the semiconductor substrate 1 is performed, epitaxial growth is performed to form a selective epitaxial silicon layer 6 of about 50 nm, for example.

  That is, as shown in FIG. 3A, the selective epitaxial silicon layer 6 is formed on the source / drain regions 4 by epitaxial growth.

  Next, for example, annealing is performed at 900 degrees for 2 minutes in a gas atmosphere (in a hydrogen atmosphere). As a result, migration of silicon atoms occurs in the entire SEG layer, thereby smoothing the facet portion (first side surface portion 6a) appearing on the surface of the selective epitaxial silicon layer 6.

  That is, as shown in FIG. 3B, the first side surface portion 6a having the facet on the element region side of the selective epitaxial silicon layer 6 is changed to a curved first side surface portion 6b by annealing in a gas atmosphere. .

  Thereafter, if necessary, additional epitaxial growth is performed to form the additional portion 13 of the selective epitaxial silicon layer 6 (FIG. 3B). Thereby, the film thickness of the selective epitaxial silicon layer 6 can be increased (adjusted).

  Thereafter, ions are implanted into the semiconductor substrate 1 through the selective epitaxial silicon layer 6 to form a deep diffusion layer 5 having a high impurity concentration and constituting a source / drain region (FIG. 3B).

  After that, an interlayer insulating film is formed of a material such as TEOS, contact holes are opened by lithography and RIE, Si and Ti silicide layers are formed at the bottom of the holes by TiCVD, and the whole is filled with TiN / W. To complete the contact. Thereby, a contact (not shown) connected to the selective epitaxial silicon layer 6 is formed. Thereafter, the LSI structure is completed through the formation of multilayer wiring and vias (not shown).

  Through the above steps, the manufacturing process of the three-dimensional transistor according to the first embodiment is completed.

  That is, the three-dimensional transistor according to Example 1 includes a semiconductor substrate 1 having an upper surface 1a having a crystal plane orientation of (100), and an element isolation region 2 formed on the semiconductor substrate 1 and partitioning an element region on the upper surface 1a. The gate electrode 3 formed on the element region of the semiconductor substrate 1 via the gate insulating film 10 and provided with the gate insulating sidewall 11 on the side surface, and the element region of the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode 3 And a selective epitaxial silicon layer 6 formed by epitaxial growth on the source / drain region 4 (FIG. 3B).

  The first side surface portion 6b on the element isolation region 2 side of the selective epitaxial silicon layer 6 has a curved surface shape. The first side surface portion 6b does not have a facet.

  Further, the second side surface portion 6 c on the gate electrode side of the selective epitaxial silicon layer 6 is in contact with the gate electrode 3 through the gate insulating side wall 11.

  Further, the first side surface portions 6b of the selective epitaxial silicon layers 6 of two adjacent three-dimensional transistors are spaced apart from each other on the element isolation region 2.

  The manufacturing method of the three-dimensional transistor according to the first embodiment described above can suppress the SEG growth in the side surface direction by smoothing the facet portion that once appeared on the surface of the SEG layer by annealing.

  Thereby, the element isolation width required between devices can be reduced, and the chip area can be reduced and the cost can be reduced.

  In addition, lateral SEG growth can be suppressed. As a result, it is possible to accumulate additional selective epitaxial silicon layers.

  Therefore, the process window in subsequent ion implantation and contact formation is widened, and device design is facilitated.

  As described above, according to the three-dimensional transistor and the manufacturing method thereof according to the first embodiment, it is possible to reduce the influence of the lateral growth due to the facet formation accompanying the selective epitaxial silicon growth and the film thickness variation of the epitaxial layer at the pattern edge. Can do.

  Next, an example of a method for manufacturing a three-dimensional transistor according to Example 2 will be described.

  FIG. 4 is a cross-sectional view illustrating an example of each step of the manufacturing method of the three-dimensional transistor according to the second embodiment. 4, the same reference numerals as those in FIGS. 1 to 3 indicate the same configurations as those in the first embodiment.

  First, in the same manner as the steps from FIGS. 1 to 2 described in the first embodiment, an element isolation region that partitions an element region on a semiconductor substrate 1 having an upper surface 1a having a crystal plane orientation of (100). 2 is formed, the gate electrode 3 is formed on the element region via the gate insulating film 10, the gate insulating side wall 11 is formed on the side surface of the gate electrode 3, and the source / drain region 4 is formed.

  Next, as shown in FIG. 4A, after the surface treatment of the semiconductor substrate 1 is performed, epitaxial growth is performed to form a selective epitaxial silicon layer 6. Here, the selective epitaxial silicon layer 6 is grown until it contacts the grown selective epitaxial silicon layer 6 in a device that goes beyond the element isolation region 2.

  Thereafter, the first side surface portion 6a of the selective epitaxial silicon layer 6 formed on the element isolation region 2 is selected by using a photomask and photolithography technique used for element isolation, an RIE technique using hard mask transfer, or the like. To remove.

  Thereafter, the same process as in the first embodiment is performed, and the manufacturing process of the three-dimensional transistor according to the second embodiment is completed.

  Further, as a mask agent used for hard mask transfer, a SiN film, an amorphous silicon film, a TEOS film, an organic insulating film, and a laminated film thereof are used.

  That is, the three-dimensional transistor according to Example 2 includes a semiconductor substrate 1 having an upper surface 1a having a crystal plane orientation of (100), and an element isolation region 2 that is formed on the semiconductor substrate 1 and partitions an element region on the upper surface 1a. The gate electrode 3 formed on the element region of the semiconductor substrate 1 via the gate insulating film 10 and provided with the gate insulating sidewall 11 on the side surface, and the element region of the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode 3 And a selective epitaxial silicon layer 6 formed by epitaxial growth on the source / drain region 4 (FIG. 3B).

  Then, the first side surface portions 6d of the selective epitaxial silicon layers 6 of two adjacent three-dimensional transistors are spaced apart from each other on the element isolation region 2.

  Therefore, the electrical short state in the selective epitaxial silicon layer 6 between different devices can be eliminated.

  The first side surface portion 6 d of the selective epitaxial silicon layer 6 on the element isolation region 2 side is a plane that is substantially perpendicular to the upper surface of the semiconductor substrate 1. For example, the first side surface portion 6 d is a plane that intersects with the upper surface of the semiconductor substrate 1 at 70 degrees to 90 degrees.

  Other configurations of the three-dimensional transistor are the same as those in the first embodiment.

  As described above, according to the three-dimensional transistor according to the second embodiment, it is possible to reduce the influence of the lateral growth due to facet formation accompanying the selective epitaxial silicon growth and the film thickness variation of the epitaxial layer at the pattern edge.

  In particular, according to the three-dimensional transistor according to the second embodiment, the film thickness of the selective epitaxial silicon layer can be set regardless of the element isolation region width.

  Next, an example of a method for manufacturing a three-dimensional transistor according to Example 3 will be described.

  FIG. 5 to FIG. 6 are cross-sectional views showing an example of each process of the manufacturing method of the three-dimensional transistor according to the third embodiment. 5 to 6, the same reference numerals as those in FIGS. 1 to 3 indicate the same configurations as those in the first embodiment.

  First, in the same manner as the steps from FIGS. 1 to 2 described in the first embodiment, an element isolation region that partitions an element region on a semiconductor substrate 1 having an upper surface 1a having a crystal plane orientation of (100). 2 is formed, the gate electrode 3 is formed on the element region via the gate insulating film 10, the gate insulating side wall 11 is formed on the side surface of the gate electrode 3, and the source / drain region 4 is formed.

  Next, as shown in FIG. 5A, a gate insulating side wall (TEOS side wall) 13 is formed, and the entire surface of the semiconductor substrate 1 is covered with SiN stopper films 14a, 14b, and 14c serving as gate insulating side walls.

  That is, the gate insulating side wall 13 and the gate insulating side wall 14c are sequentially formed outside the gate insulating side wall 11.

  Thereafter, RIE (so-called oblique incidence type dry etching) is performed at an incident angle of, for example, 45 degrees while rotating the semiconductor substrate 1 about an axis perpendicular to the upper surface 1a. Thereby, the bottoms of the SiN stopper film 14a and the gate insulating sidewall (SiN stopper film) 14c on the semiconductor substrate 1 are removed.

  Thereafter, by wet etching, a portion of the gate insulating sidewall (TEOS film) 13 exposed by removing the bottom of the gate insulating sidewall 14 is selectively removed (FIG. 5B).

  Next, after the surface treatment of the semiconductor substrate 1 is performed, epitaxial growth is performed to form a selective epitaxial silicon layer 6 of about 50 nm, for example.

  That is, as shown in FIG. 6A, the selective epitaxial silicon layer 6 is formed on the source / drain regions 4 by epitaxial growth.

  Thereafter, ions are implanted into the semiconductor substrate 1 through the selective epitaxial silicon layer 6 to form a deep diffusion layer 5 having a high impurity concentration and constituting a source / drain region (FIG. 6B).

  Since the thickness of the side surface portion 6a of the selective epitaxial silicon layer 6 is small, a part 5a of the diffusion layer 5 below the side surface portion 6a becomes deeper.

  Thereafter, the same process as in the first embodiment is performed, and the manufacturing process of the three-dimensional transistor according to the third embodiment is completed.

  That is, the three-dimensional transistor according to Example 3 includes a semiconductor substrate 1 having an upper surface 1a having a crystal plane orientation of (100), and an element isolation region 2 formed on the semiconductor substrate 1 and partitioning an element region on the upper surface 1a. The gate electrode 3 formed on the element region of the semiconductor substrate 1 via the gate insulating film 10 and provided with the gate insulating sidewall 11 on the side surface, and the element region of the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode 3 The source / drain regions 4 formed on the source / drain regions 4, the selective epitaxial silicon layer 6 formed by epitaxial growth on the source / drain regions 4, and the upper part of the gate electrode 3 are provided so as to cover the isolation region from the gate insulating sidewall 11. Cap insulating layer (SiN stopper film 14b, gate insulating side wall 13, gate insulating side wall (SiN stopper film) extending to 2 side And 4c), provided with a (FIG. 6 (B)).

  Then, the gate electrode of the selective epitaxial silicon layer 6 is formed under the portion of the cap insulating layer (SiN stopper film 14b, gate insulating side wall 13, gate insulating side wall (SiN stopper film) 14c) extending to the element isolation region 2 side. The second side surface portion 6c on the side is located (FIG. 6B). The second side surface portion 6c and the bottom portion 11a of the gate insulating side wall 11 are in contact with each other.

  Other configurations of the three-dimensional transistor are the same as those in the first embodiment.

  As described above, according to the three-dimensional transistor according to the third embodiment, it is possible to reduce the influence of the lateral growth due to facet formation accompanying the selective epitaxial silicon growth and the film thickness variation of the epitaxial layer at the pattern edge.

  In particular, in the three-dimensional transistor according to the third embodiment, the cap insulating layer is formed thicker than the gate electrode and the gate insulating sidewall 11.

  Thereby, since the cap insulating layer shields ion implantation to the semiconductor substrate, it is difficult to introduce deep implants below the cap insulating layer.

  As a result, deep implantation around the gate electrode in which the selective epitaxial silicon layer is formed thinner than other regions is suppressed. This makes it possible to efficiently suppress the short channel effect of the device.

  In the fourth embodiment, an example in which a FIN type transistor is selected as a three-dimensional transistor will be described.

  7 to 8 are cross-sectional views showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 4 when the crystal plane orientation of the main surface of the element region is (110). 9 to 10 are cross-sectional views showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 4 when the crystal plane orientation of the main surface of the element region is (100).

  First, a hard mask layer 21 is selectively formed on a region to be an element region on the semiconductor substrate 1 by lithography (FIGS. 7A and 9A).

  Then, as shown in FIGS. 7A and 9A, by anisotropic etching, the semiconductor substrate 1 is vertically etched using the hard mask layer 21 as a mask, so that the upper surface of the semiconductor substrate 1 is etched. An element region 20 having a vertical plate shape and a crystal plane orientation of (100) or (110) of the principal surface 20a perpendicular to the upper surface of the semiconductor substrate 1 is formed.

  Then, as shown in FIGS. 7A and 9A, the element isolation insulating film 22 is exposed so that at least the upper part 20b of the element region 20 is exposed on a region where the element region 20 does not exist on the semiconductor substrate 1. Form.

  As shown in FIGS. 7A and 9A, the gate insulating film 30 is formed in a plate shape perpendicular to the upper surface 1a of the semiconductor substrate 1, perpendicular to the element region 20 and in the element region 20. A gate electrode 23 in contact therewith is formed on the element isolation insulating film 22.

  Next, as shown in FIGS. 7B and 9B, the hard mask layer 21 covering the upper surface of the device region 20 is used as a mask, and the device region 20 that is not covered with the hard mask layer 21 is formed by epitaxial growth. A selective epitaxial silicon layer 26 is selectively formed on the main surface 20a.

  At this point, the selective epitaxial silicon layer 26 is sufficiently thick and the selective epitaxial silicon layers 26 of adjacent three-dimensional transistors are in contact with each other. The shape of the selective epitaxial silicon layer 26 differs depending on the crystal plane orientation of the main surface 20a and the direction of the three-dimensional transistor.

  Then, as shown in FIGS. 8A and 10A, a mask layer 27 covering the hard mask layer 21 is formed. Then, a part of the selective epitaxial silicon layer 26 is selectively etched substantially vertically by anisotropic etching (for example, RIE) using the mask layer 27 as a mask.

  Thereafter, as shown in FIGS. 8B and 10B, the mask layer 27 is removed, and then an implantation process, an interlayer film formation process, a contact formation process, and a multilayer wiring process are performed, and the implementation is a FIN transistor. The manufacturing process of the three-dimensional transistor according to Example 4 is completed.

  That is, the three-dimensional transistor according to the fourth embodiment is formed on the semiconductor substrate 1 in a plate shape perpendicular to the semiconductor substrate 1 and the upper surface 1 a of the semiconductor substrate 1, and the main transistor is perpendicular to the upper surface of the semiconductor substrate 1. An element region 20 whose crystal plane orientation of the surface 20a is (110) or (110), a hard mask layer 21 covering the upper surface of the element region 20, and a region where the element region 20 on the semiconductor substrate 1 does not exist An element isolation insulating film 22 formed so as to expose at least the upper portion 20b of the region 20 and a plate shape perpendicular to the upper surface 1a of the semiconductor substrate 1 are formed on the element isolation insulating film 22 and The gate electrode 23 that is orthogonal to the element region 20 and is in contact with the element region 20 via the gate insulating film 30 and the hard mask layer 21 is not covered with the hard mask layer 21 in the element region 20 (further, And a selective epitaxial silicon layer 26 formed by epitaxial growth on the main surface 20a in which the gate insulating film 30 is not formed, that is, not in contact with the gate electrode 23 via the gate insulating film 30 (FIG. 8B). ), FIG. 10 (B)).

  The side surface portion 26 d of the selective epitaxial silicon layer 26 is a plane that is substantially perpendicular to the upper surface of the semiconductor substrate 1. For example, the side surface portion 26 d is a flat surface that is inclined by 70 to 90 degrees with respect to the upper surface of the semiconductor substrate 1.

  As described above, according to the three-dimensional transistor according to the fourth embodiment, it is possible to reduce the influence of the lateral growth due to facet formation accompanying the selective epitaxial silicon growth and the film thickness variation of the epitaxial layer at the pattern edge.

  In particular, according to the three-dimensional transistor according to the fourth embodiment, the film thickness of the selective epitaxial silicon layer can be set regardless of the element isolation region width. As a result, the resistance of the source / drain region of the FIN transistor can be lowered to a desired value.

  In the fifth embodiment, another example in which a FIN type transistor is selected as a three-dimensional transistor will be described.

  FIG. 11 to FIG. 12 are cross-sectional views showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 5 when the crystal plane orientation of the main surface of the element region is (110). FIGS. 13 to 14 are cross-sectional views showing an example of each step of the manufacturing method of the three-dimensional transistor according to Example 5 when the crystal plane orientation of the main surface of the element region is (100).

  First, the hard mask layer 21 is selectively formed on the semiconductor substrate 1 and the region to be an element region by lithography (FIGS. 11A and 13A).

  Then, as shown in FIGS. 11A and 13A, by anisotropic etching, the semiconductor substrate 1 is etched perpendicularly using the hard mask layer 21 as a mask, so that the upper surface of the semiconductor substrate 1 is etched. An element region 20 having a vertical plate shape and a crystal plane orientation of (100) or (110) of the principal surface 20a perpendicular to the upper surface of the semiconductor substrate 1 is formed.

  Then, as shown in FIGS. 11A and 13A, the element isolation insulating film 22 is exposed so that at least the upper part 20b of the element region 20 is exposed on a region where the element region 20 does not exist on the semiconductor substrate 1. Form.

  11A and 13A, the gate insulating film 30 has a plate shape perpendicular to the upper surface 1a of the semiconductor substrate 1, is orthogonal to the element region 20, and is formed in the element region 20. A gate electrode 23 in contact therewith is formed on the element isolation insulating film 22.

  Next, as shown in FIG. 11B and FIG. 13B, the hard mask layer 21 covering the upper surface of the device region 20 is used as a mask, and the device region 20 not covered with the hard mask layer 21 is formed by epitaxial growth. A selective epitaxial silicon layer 26 is selectively formed on the main surface 20a.

  At this point, the selective epitaxial silicon layer 26 is sufficiently thick and the selective epitaxial silicon layers 26 of adjacent three-dimensional transistors are in contact with each other. The shape of the selective epitaxial silicon layer 26 differs depending on the crystal plane orientation of the main surface 20a and the direction of the three-dimensional transistor.

  Then, as shown in FIGS. 12A and 14A, an insulating sidewall (SiN sidewall layer) 28 is formed on the side surface of the hard mask layer 21.

  Then, as shown in FIGS. 12B and 14B, a part of the selective epitaxial silicon layer 26 is formed by anisotropic etching (for example, RIE) using the hard mask layer 21 and the insulating sidewall 28 as a mask. The etching is selectively performed substantially vertically.

  The insulating sidewall 28 may be a SiO2 material such as TEOS or a metal oxide insulating film such as alumina.

  Thereafter, through the implantation process, the interlayer film forming process, the contact forming process, and the multilayer wiring process, the manufacturing process of the three-dimensional transistor according to the fifth embodiment which is a FIN type transistor is completed.

  That is, the three-dimensional transistor according to the fifth embodiment is formed on the semiconductor substrate 1 in a plate shape perpendicular to the semiconductor substrate 1 and the upper surface 1 a of the semiconductor substrate 1, and the main transistor is perpendicular to the upper surface of the semiconductor substrate 1. An element region 20 whose crystal plane orientation of the surface 20a is (110) or (110), a hard mask layer 21 covering the upper surface of the element region 20, and a region where the element region 20 on the semiconductor substrate 1 does not exist An element isolation insulating film 22 formed so as to expose at least the upper portion 20b of the region 20 and a plate shape perpendicular to the upper surface 1a of the semiconductor substrate 1 are formed on the element isolation insulating film 22 and A gate electrode 23 orthogonal to the element region 20 and in contact with the element region 20 via a gate insulating film 30 and a hard mask layer 21; an insulating sidewall 28 formed on a side surface of the hard mask layer 21; It is formed by epitaxial growth on the main surface 20a not covered with the hard mask layer 21 in the region 20 (further, the gate insulating film 30 is not formed, that is, not in contact with the gate electrode 23 via the gate insulating film 30). And a selective epitaxial silicon layer 26 having substantially the same width as that of the insulating sidewall 28 (FIGS. 12B and 14B).

  The side surface portion 26 d of the selective epitaxial silicon layer 26 is a plane that is substantially perpendicular to the upper surface of the semiconductor substrate 1. For example, the side surface portion 26 d is a flat surface that is inclined by 70 to 90 degrees with respect to the upper surface of the semiconductor substrate 1.

  As described above, according to the three-dimensional transistor of the fifth embodiment, it is possible to reduce the influence of the lateral growth due to facet formation accompanying the selective epitaxial silicon growth and the film thickness variation of the epitaxial layer at the pattern edge.

  In particular, according to the three-dimensional transistor of Example 5, the thickness of the selective epitaxial silicon layer can be set regardless of the element isolation region width. As a result, the resistance of the source / drain region of the FIN transistor can be lowered to a desired value.

  Furthermore, the selective epitaxial silicon layer can be processed using the sidewall formed by the sidewall leaving technique.

  For this reason, the thickness of the selective epitaxial silicon layer can be made uniform, and it can also be applied to generations that have a FIN-FIN distance exceeding the limit of the alignment margin of ordinary lithography technology. It becomes the technology which applied.

  In addition, embodiment is an illustration and the range of invention is not limited to them.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Gate electrode 4 Source / drain region 5 Diffusion layer 6 Selective epitaxial silicon layer 10 Gate insulating film 12 Cap insulating film 11 Gate insulating side wall

Claims (14)

A semiconductor substrate having an upper surface with a crystal plane orientation of (100);
An element isolation region formed on the semiconductor substrate and defining an element region on the upper surface;
A gate electrode formed on the element region of the semiconductor substrate via a gate insulating film, and provided with a gate insulating sidewall on a side surface;
Source / drain regions formed in the element region of the semiconductor substrate in a self-aligned manner with respect to the gate electrode;
A selective epitaxial silicon layer formed by epitaxial growth on the source / drain region, and
The three-dimensional transistor according to claim 1, wherein the first side surface portion of the selective epitaxial silicon layer on the element isolation region side has a curved surface shape.   The three-dimensional transistor according to claim 1, wherein the first side surface portion has no facet. A semiconductor substrate having an upper surface with a crystal plane orientation of (100);
An element isolation region formed on the semiconductor substrate and defining an element region on the upper surface;
A gate electrode formed on the element region of the semiconductor substrate via a gate insulating film, and provided with a gate insulating sidewall on a side surface;
Source / drain regions formed in the element region of the semiconductor substrate in a self-aligned manner with respect to the gate electrode;
A selective epitaxial silicon layer formed by epitaxial growth on the source / drain region, and
The three-dimensional transistor, wherein the first side surface portion on the element isolation region side of the selective epitaxial silicon layer is a plane substantially perpendicular to the upper surface of the semiconductor substrate. 4. The three-dimensional transistor according to claim 3, wherein the first side surface portion is a plane that intersects at 70 degrees to 90 degrees with respect to the upper surface of the semiconductor substrate. A semiconductor substrate having an upper surface with a crystal plane orientation of (100);
An element isolation region formed on the semiconductor substrate and defining an element region on the upper surface;
A gate electrode formed on the element region of the semiconductor substrate via a gate insulating film, and provided with a gate insulating sidewall on a side surface;
Source / drain regions formed in the element region of the semiconductor substrate in a self-aligned manner with respect to the gate electrode;
A selective epitaxial silicon layer formed by epitaxial growth on the source / drain regions;
A cap insulating layer provided so as to cover an upper portion of the gate electrode and extending from the gate insulating side wall to the element isolation region side,
The three-dimensional transistor characterized in that a second side surface portion on the gate electrode side of the selective epitaxial silicon layer is located under a portion extending to the element isolation region side of the cap insulating layer. The second side surface portion on the gate electrode side of the selective epitaxial silicon layer is in contact with the gate electrode through a gate side wall.
The three-dimensional transistor according to any one of claims 1 to 5, wherein The first side surface portion of the selective epitaxial silicon layer of two adjacent three-dimensional transistors is spaced apart and opposed on the element isolation region. The three-dimensional transistor according to item. A semiconductor substrate;
An element region which is formed on the semiconductor substrate in a plate shape perpendicular to the upper surface of the semiconductor substrate, and a crystal plane orientation of a main surface perpendicular to the upper surface of the semiconductor substrate is (100) or (110) When,
A hard mask layer covering the upper surface of the element region;
An element isolation insulating film formed on a region where the element region does not exist on the semiconductor substrate so that at least an upper portion of the element region is exposed;
A gate electrode formed on the element isolation insulating film in a plate shape perpendicular to the upper surface of the semiconductor substrate, orthogonal to the element region on the semiconductor substrate, and in contact with the element region via a gate insulating film; ,
A selective epitaxial silicon layer formed by epitaxial growth on the main surface not covered with the hard mask layer in the element region,
3. The three-dimensional transistor according to claim 1, wherein the side surface portion of the selective epitaxial silicon layer is a plane substantially perpendicular to the upper surface of the semiconductor substrate. A semiconductor substrate;
An element region which is formed on the semiconductor substrate in a plate shape perpendicular to the upper surface of the semiconductor substrate, and a crystal plane orientation of a main surface perpendicular to the upper surface of the semiconductor substrate is (100) or (110) When,
A hard mask layer covering the upper surface of the element region;
An element isolation insulating film formed on a region where the element region does not exist on the semiconductor substrate so that at least an upper portion of the element region is exposed;
A gate electrode formed on the element isolation insulating film in a plate shape perpendicular to the upper surface of the semiconductor substrate, orthogonal to the element region on the semiconductor substrate, and in contact with the element region via a gate insulating film; ,
An insulating sidewall formed on a side surface of the hard mask layer;
A selective epitaxial silicon layer formed by epitaxial growth on the main surface of the element region that is not covered with the hard mask layer and having a width substantially the same as the width of the insulating sidewall;
3. The three-dimensional transistor according to claim 1, wherein the side surface portion of the selective epitaxial silicon layer is a plane substantially perpendicular to the upper surface of the semiconductor substrate. The three-dimensional transistor according to claim 8 or 9, wherein the side surface portion is a plane inclined by 70 to 90 degrees with respect to the upper surface of the semiconductor substrate.   The three-dimensional transistor according to claim 1, wherein the semiconductor substrate is a silicon substrate. Forming an element isolation region for partitioning an element region on a semiconductor substrate having an upper surface with a crystal plane orientation of (100);
Forming a gate electrode on the element region via a gate insulating film;
Forming a gate insulating sidewall on a side surface of the gate electrode;
Forming source / drain regions on the element region in a self-aligned manner with respect to the gate electrode;
A selective epitaxial silicon layer is formed on the source / drain regions by epitaxial growth,
The method for manufacturing a three-dimensional transistor, wherein the first side surface portion on the element region side of the selective epitaxial silicon layer is formed into a curved shape by annealing in a gas atmosphere. Forming an element isolation region for partitioning an element region on a semiconductor substrate having an upper surface with a crystal plane orientation of (100);
Forming a gate electrode on the element region via a gate insulating film;
Forming a first gate insulating sidewall on a side surface of the gate electrode;
Source / drain regions are formed by ion implantation,
Forming a second gate insulating sidewall and a third gate insulating sidewall sequentially on the outside of the first gate insulating sidewall;
The bottom of the third gate insulating sidewall is removed by oblique incidence type dry etching,
By wet etching, the exposed portion of the second gate insulating sidewall is removed by removing the bottom of the third gate insulating sidewall;
A method of manufacturing a three-dimensional transistor, comprising forming a selective epitaxial silicon layer on the source / drain regions by epitaxial growth. A hard mask layer is selectively formed on a region to be an element region on a semiconductor substrate by lithography technology,
By etching the semiconductor substrate perpendicularly using the hard mask layer as a mask by anisotropic etching, a main body perpendicular to the upper surface of the semiconductor substrate and perpendicular to the upper surface of the semiconductor substrate is obtained. Forming an element region whose crystal plane orientation is (100) or (110),
Forming an element isolation insulating film on a region of the semiconductor substrate where the element region does not exist so that at least an upper portion of the element region is exposed;
A gate electrode perpendicular to the upper surface of the semiconductor substrate and perpendicular to the element region and in contact with the element region via a gate insulating film is formed on the element isolation insulating film;
A selective epitaxial silicon layer is selectively formed on the main surface of the element region not covered with the hard mask layer by epitaxial growth using the hard mask layer covering the upper surface of the element region as a mask,
Forming an insulating sidewall on a side surface of the hard mask layer;
A method for manufacturing a three-dimensional transistor, characterized in that a part of the selective epitaxial silicon layer is selectively etched substantially perpendicularly by anisotropic etching using the hard mask layer and the insulating sidewall as a mask.

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