JP2013201335A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in a semiconductor device in which a MOSFET and a MONOS memory element having different drive voltages are mounted on the same semiconductor substrate and a manufacturing method of the semiconductor device, which is caused because a gate insulation film and a memory insulation film having different film thicknesses are separately formed by performing deposition, masking and etching in the method in the past.SOLUTION: A high-voltage MOSFET comprises a gate insulation film having a four-layer structure which includes a high-voltage gate insulation film or a low-voltage gate insulation film as an underlying insulation film and a memory insulation film of a nonvolatile semiconductor storage element on top of the underlying insulation film. Accordingly, securing of withstand voltage of the high-voltage MOSFET and dielectric strength voltage of the low-voltage MOSFET and shortening of a manufacturing process are supported at the same time.

Description

  The present invention relates to a semiconductor device in which MOSFETs and semiconductor memory elements having different withstand voltages are provided in different element regions on the same semiconductor substrate, and a manufacturing method thereof.

  Semiconductor devices in which a large number of semiconductor memory elements and semiconductor switching elements are integrated are used in ICs for driving liquid crystal display devices, including microcomputers that control electronic devices such as electronic watches and mobile phones.

  As such a semiconductor memory element, a nonvolatile memory element that can electrically rewrite data and can retain stored data even when the power is turned off is frequently used. Conventionally, most of such nonvolatile memory elements are floating gate type memory elements, but in recent years, MONOS type memory elements have been used.

  The MONOS memory element is a nonvolatile memory element having a structure of a metal (metal), an oxide film (Oxide), a nitride film (Nitride), an oxide film (Oxide), and a semiconductor (Semiconductor).

  The MONOS type memory device sequentially stacks a tunnel oxide film made of a silicon oxide film, a memory nitride film made of a silicon nitride film for accumulating charges, and a top oxide film made of a silicon oxide film on a silicon substrate which is a semiconductor substrate. Then, an ONO film is formed, and a memory gate electrode made of polysilicon or the like is formed on the top oxide film.

  The MONOS type memory element has a feature that data can be written and erased at a relatively low voltage as compared with a conventional floating gate type memory element, and has recently begun to be adopted in many semiconductor devices.

Data writing and erasing to the MONOS type memory device having such a configuration is performed by changing the voltage applied between the memory gate electrode and the silicon substrate.
For example, at the time of writing, by applying a write voltage to the memory gate electrode and setting the silicon substrate to the ground potential, charges near the surface of the silicon substrate pass through the tunnel oxide film and are accumulated in the memory nitride film. At the time of erasing, the memory gate electrode is set to the ground potential and an erasing voltage is applied to the silicon substrate, whereby charges accumulated in the memory nitride film pass through the tunnel oxide film and are extracted to the silicon substrate.

  When a plurality of MONOS memory elements are mounted on a semiconductor device, an address transistor for selecting the memory element is required for each memory element in order to correctly rewrite and read data for each memory element. is there. As such an address transistor, a MOSFET is used.

As already described, the MONOS memory element can make the write voltage lower (for example, 10 V or less) than the conventional one, so that the MOSFET as the address transistor also needs to have a special high breakdown voltage structure. There is no sex.
Therefore, a normal low breakdown voltage MOSFET can be used as an address transistor and can be provided adjacent to each MONOS type memory element. Such a configuration sees many proposals.

  However, in order to configure a highly integrated or multifunctional semiconductor device, it is necessary to mount an input / output circuit, a booster circuit, and the like that exchange signals with other devices on the same semiconductor substrate. Such a circuit is often composed of a high-breakdown-voltage MOSFET having a higher drive voltage.

  As is known, the MOSFET is composed of a metal (Metal), an oxide film (Oxide), and a semiconductor (Semiconductor). A gate insulating film made of a silicon oxide film is formed on a silicon substrate, and polysilicon or the like is formed thereon. A gate electrode is provided. And, MOSFETs having different withstand voltages have different gate insulating film thicknesses. That is, the gate insulating film is thicker in the high breakdown voltage MOSFET than in the normal low breakdown voltage MOSFET.

  As described above, a semiconductor device in which a MONOS type memory element, a low breakdown voltage MOSFET, and a high breakdown voltage MOSFET are mixedly mounted on the same semiconductor substrate is known (for example, see Patent Document 1).

A manufacturing method related to the prior art shown in Patent Document 1 will be described with reference to FIG.
In the description, a manufacturing method for forming a MOSFET, a gate insulating film and an ONO film in a MONOS memory element will be described, and description of other manufacturing methods will be omitted.

  In FIG. 7, 91 is a semiconductor substrate, 92 is an element isolation insulating film, 94 is a top oxide film, 95 is a charge storage insulating film, 96 is a tunnel insulating film, 98 is a high breakdown voltage element area, 99 is a low breakdown voltage element area, Reference numeral 100 denotes a MONOS type memory element region, 103 denotes a low breakdown voltage gate insulating film, and 104 denotes a high breakdown voltage gate insulating film. The top insulating film 94, the charge storage insulating film 95, and the tunnel insulating film 96 constitute a memory insulating film 97.

  FIG. 7A shows how the memory insulating film 97 is formed after element isolation. FIG. 7B shows a state where the low breakdown voltage gate insulating film 103 is formed. FIG. 7C shows how the high breakdown voltage gate insulating film 104 is formed.

  The manufacturing method according to the prior art disclosed in Patent Document 1 includes a memory insulating film 97 in the MONOS type memory element region 100, a high breakdown voltage, as can be understood by sequentially viewing FIGS. 7 (a) to 7 (c). The high withstand voltage gate insulating film 104 in the element region 98 and the low withstand voltage gate insulating film 103 in the low withstand voltage element region 99 are formed separately, and then processed into a predetermined shape.

JP 2002-324860 A (5th page, FIG. 1)

  The manufacturing method according to the prior art disclosed in Patent Document 1 is manufactured by forming the memory insulating film 97, the low withstand voltage gate insulating film 103, and the high withstand voltage gate insulating film 104 individually for each structure of the mounted element. There was a problem of a long process.

  In addition, there is a problem that electrical characteristics deteriorate due to damage received when a film of another element among the elements to be mounted is formed and manufacturing variations of the elements to be mounted.

For example, the low breakdown voltage element region 99 and the high breakdown voltage element region 98 are damaged by etching the surface of the semiconductor substrate 91 twice by the etching process of the memory insulating film 97 and the etching process of the high breakdown voltage gate insulating film 104. In particular, the low breakdown voltage gate insulating film 103 provided in the low breakdown voltage element region 99 is thinner in film quality than the high breakdown voltage gate insulating film 104 provided in the high breakdown voltage element region 98. This increases the risk of causing a pressure breakdown failure. If this breakdown voltage failure occurs, the function as a MOSFET is impaired, which is a problem.

Further, for example, the high breakdown voltage gate insulating film 104 of the MOSFET formed in the high breakdown voltage element region 98 may not be formed with a film thickness as designed due to variations in manufacturing processes. If the film thickness is reduced, the withstand voltage is lowered, and the electrical characteristics as a high withstand voltage element are deteriorated.
The MOSFET formed in the high breakdown voltage element region 98 constitutes an input / output circuit, a booster circuit, a circuit for generating a data write voltage and an erase voltage for the MONOS type memory element, etc., and thus does not function normally as a semiconductor device. It is a problem.

  The present invention has been made to solve such a problem. In a semiconductor device in which a memory element, a low breakdown voltage MOSFET, and a high breakdown voltage MOSFET are mixedly mounted on a semiconductor substrate, the breakdown voltage of the high breakdown voltage MOSFET is ensured. An object of the present invention is to provide a technique that achieves both the maintenance of the withstand voltage of the low breakdown voltage MOSFET and the shortening of the manufacturing process.

  In order to achieve the above object, a method for manufacturing a semiconductor device of the present invention employs the following method.

A MOSFET type nonvolatile semiconductor memory element having a three-layer memory insulating film formed by laminating a tunnel insulating film, a charge storage insulating film, and a top insulating film, and a predetermined operation of the nonvolatile semiconductor memory element A semiconductor device in which a low breakdown voltage MOSFET having a low breakdown voltage gate insulating film and a high breakdown voltage MOSFET having a high breakdown voltage gate insulating film are respectively provided in a memory element region, a low breakdown voltage element region, and a high breakdown voltage element region provided in a semiconductor substrate. A manufacturing method of
A first insulating film forming step for simultaneously forming a base insulating film in the memory element region, the low withstand voltage element region, and the high withstand voltage element region; a base insulating film removing step for removing the base insulating film in the memory element region; After the insulating film removal step, a tunnel insulating film, a charge storage insulating film, and a top insulating film are sequentially stacked from the semiconductor substrate side at the same time in the high withstand voltage element region, the low withstand voltage element region, and the memory element region. A second insulating film forming step to be formed; and a third insulating film forming step for forming a low breakdown voltage gate insulating film in the low breakdown voltage element region after the second insulating film forming step. And

  In this case, since the gate insulating film of the high breakdown voltage MOSFET is composed of the base insulating film and the memory insulating film, the breakdown voltage of the high breakdown voltage MOSFET can be secured and can be formed with a small number of manufacturing processes. It can be shortened. Since the surface of the semiconductor substrate is less likely to be exposed to etching, the withstand voltage of the low voltage MOSFET can be maintained.

  The base insulating film is a low withstand voltage gate insulating film, and the third insulating film forming step may form the low withstand voltage gate insulating film by removing the memory insulating film in the low withstand voltage element region.

  In this case, since the gate insulating film of the high breakdown voltage MOSFET can be composed of the gate insulating film of the low breakdown voltage MOSFET and the memory insulating film, the breakdown voltage of the high breakdown voltage MOSFET can be secured without increasing the number of manufacturing steps.

The base insulating film is a high breakdown voltage gate insulating film. In the third insulating film forming step, the memory insulating film and the base insulating film in the low breakdown voltage element region are removed to expose the surface of the semiconductor substrate. A gate insulating film may be formed.

  In this case, since the gate insulating film of the high voltage MOSFET can be constituted by the gate insulating film and the memory insulating film of the high voltage MOSFET, the high voltage MOSFET can secure a higher voltage without increasing the number of manufacturing steps.

  The base insulating film is a high withstand voltage gate insulating film. In the third insulating film forming step, the memory insulating film in the low withstand voltage element region is removed, and a part of the base insulating film is removed. An insulating film may be formed.

  In this case, since the gate insulating film of the low breakdown voltage MOSFET can be formed by thinly processing the gate insulating film of the high breakdown voltage MOSFET, the manufacturing process does not increase.

  In order to achieve the above object, the semiconductor device of the present invention employs the following structure.

  A MOSFET type nonvolatile semiconductor memory element having a three-layer memory insulating film formed by laminating a tunnel insulating film, a charge storage insulating film, and a top insulating film, and a predetermined operation of the nonvolatile semiconductor memory element In addition, a low breakdown voltage MOSFET having a low breakdown voltage gate insulating film and a high breakdown voltage MOSFET having a high breakdown voltage gate insulating film are mixedly mounted on the same semiconductor substrate, and the high breakdown voltage MOSFET is used as a base insulating film. It has a high-voltage gate insulating film or a low-voltage gate insulating film, and has a four-layer gate insulating film provided with a memory insulating film on the gate insulating film.

  With such a configuration, the high breakdown voltage MOSFET becomes a gate insulating film having a four-layer structure, so that the breakdown voltage characteristics are improved.

  The low breakdown voltage gate insulation film and the high breakdown voltage gate insulation film are made of the same material, and the low breakdown voltage gate insulation film is thinner than the high breakdown voltage gate insulation film and thicker than the tunnel insulation film. May be made thicker.

  By adopting such a configuration, it is possible to prevent the tunnel effect from occurring and reduce the threshold voltage of the low breakdown voltage MOSFET without increasing the number of manufacturing steps.

  According to the present invention, securing the withstand voltage of the high withstand voltage MOSFET and maintaining the withstand voltage of the low withstand voltage MOSFET can be formed with few manufacturing processes.

It is sectional drawing shown typically in order to demonstrate the structure of 1st Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of 1st Embodiment of the semiconductor device of this invention. It is sectional drawing shown typically in order to demonstrate the structure of 2nd Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of 2nd Embodiment of the semiconductor device of this invention. It is sectional drawing shown typically in order to demonstrate the structure of 3rd Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of 3rd Embodiment of the semiconductor device of this invention. It is sectional drawing for demonstrating a known semiconductor device.

  The semiconductor device of the present invention does not form a memory insulating film of a MOSFET type nonvolatile semiconductor memory element, a gate insulating film of a high breakdown voltage element, and a gate insulating film of a low breakdown voltage element separately, The gate insulating film of the MOSFET is composed of a base insulating film and a memory insulating film.

  This base insulating film can secure a sufficient withstand voltage as a gate insulating film of a high withstand voltage MOSFET, so-called high withstand voltage gate insulating film itself, or a so-called low withstand voltage sufficient as a gate insulating film of a low withstand voltage MOSFET. Either of the withstand voltage gate insulating films can be used.

  That is, when the base insulating film is the high breakdown voltage gate insulating film itself, the gate insulating film of the high breakdown voltage MOSFET is composed of two films, the high breakdown voltage gate insulating film and the memory insulating film. On the other hand, when the base insulating film is a low breakdown voltage gate insulating film, the gate insulating film of the high breakdown voltage MOSFET is composed of two films, a low breakdown voltage gate insulating film and a memory insulating film.

  In both cases, the memory insulating film is formed by sequentially stacking three insulating films, ie, a tunnel insulating film, a charge storage insulating film, and a top insulating film, from the semiconductor substrate side. Either the three insulating films that are the base insulating film and the four-layer insulating film of the high-voltage gate insulating film or the four-layer insulating film of the three insulating films and the low-voltage gate insulating film It becomes.

  The gate insulating film of the high voltage MOSFET has a thickness of this four-layer structure that is larger than that required when the gate insulating film has a conventionally known configuration. For this reason, the high voltage MOSFET can have a higher withstand voltage.

Hereinafter, an embodiment of the semiconductor device of the present invention will be described. As an example 1, an example in which a low withstand voltage gate insulating film which is a gate insulating film of a low withstand voltage MOSFET is used as a base insulating film will be described.
As Example 2, an example in which a high-breakdown-voltage gate insulating film that is a gate insulating film of a high-breakdown-voltage MOSFET is used as a base insulating film will be described.
As Example 3, as in Example 2, a high withstand voltage gate insulating film, which is a gate insulating film of a high withstand voltage MOSFET, is used as a base insulating film, and a part of this insulating film is removed to thereby insulate the gate of the low withstand voltage MOSFET. An example of forming a film will be described.

  In the description of the embodiments, a MONOS type nonvolatile semiconductor memory element having a three-layer memory insulating film formed by laminating a tunnel insulating film, a charge storage insulating film, and a top insulating film is used. An example using a memory element will be described.

The description will be made with reference to the drawings, which are schematic diagrams showing only the portions necessary for explaining the invention. For example, descriptions of a gate electrode, a source region, a drain region, and the like are omitted except for some drawings. In addition, descriptions of configurations that are not directly related to the invention, such as metal wirings and final protective films constituting the semiconductor device, are omitted.
In the description, the same number is assigned to the same configuration, and the description is omitted.

Hereinafter, a first embodiment of a semiconductor device will be described with reference to FIGS.
As described above, the first embodiment is an example in which a low breakdown voltage gate insulating film that is a gate insulating film of a low breakdown voltage MOSFET is used as a base insulating film.

[Structure of First Embodiment: FIG. 1]
First, the structure will be described with reference to FIG.
FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device. FIG. 1A schematically shows that a gate insulating film and a memory insulating film are formed in a high breakdown voltage element region, a low breakdown voltage element region, and a MONOS type memory element region, respectively, by a manufacturing method described later. It is a sectional view,
FIG. 1B is a cross-sectional view schematically showing a place where a gate electrode, a source region, and a drain region are provided thereafter.

  In FIG. 1, 1 is a semiconductor substrate and 2 is an element isolation insulating film. Reference numeral 3 denotes a base insulating film, which is a low breakdown voltage gate insulating film which is a gate insulating film of a low breakdown voltage MOSFET. 4 is a top insulating film, 5 is a charge storage insulating film, 6 is a tunnel insulating film, 8 is a high breakdown voltage element region, 9 is a low breakdown voltage element region, and 10 is a MONOS type memory element region. The top insulating film 4, the charge storage insulating film 5, and the tunnel insulating film 6 constitute a memory insulating film 7.

  Similarly, in FIG. 1, reference numeral 1 a denotes a region in the vicinity of the surface of the semiconductor substrate 1 in the MONOS type memory element region 10, which is a part for forming a source region and a drain region constituting the MONOS type memory element.

  Reference numeral 12a denotes a gate electrode of the high breakdown voltage MOSFET, 12b denotes a gate electrode of the low breakdown voltage MOSFET, and 12c denotes a memory gate electrode of the MONOS type memory element. Reference numerals 11a, 11b, and 11c denote a source region and a drain region of a high breakdown voltage MOSFET, a high breakdown voltage MOSFET, and a MONOS type memory element, respectively.

  For example, a silicon substrate can be used as the semiconductor substrate 1. The base insulating film 3, the tunnel insulating film 6, and the top insulating film 4 can be composed of a silicon oxide film. The charge storage insulating film 5 can be formed of a silicon nitride film.

A base insulating film 3 is formed on the surface of the semiconductor substrate 1 in the high breakdown voltage element region 8. Since the base insulating film 3 is a low breakdown voltage gate insulating film, it is also provided on the surface of the semiconductor substrate 1 in the low breakdown voltage element region 9.
The film thickness is determined in accordance with the operating voltage of the low breakdown voltage MOSFET. For example, when the operating voltage of the low breakdown voltage MOSFET is 1.5 V (absolute value), the film thickness is about 100 mm.

  A memory insulating film 7 in which a tunnel insulating film 6, a charge storage insulating film 5, and a top insulating film 4 are sequentially stacked on the base insulating film 3 provided on the surface of the semiconductor substrate 1 in the high breakdown voltage element region 8. Is formed. The memory insulating film 7 is also provided on the surface of the semiconductor substrate 1 in the MONOS type memory element region 10. When data is written, charges are trapped in the charge storage insulating film 5.

  That is, the memory insulating film 7 is a part of the high-voltage gate insulating film in the high-voltage element region 8 and is a memory insulating film in the MONOS type memory element region 10.

The film thicknesses of the tunnel insulating film 6, the charge storage insulating film 5, and the top insulating film 4 are determined by the electrical characteristics of the MONOS memory element.
As an example, if the write voltage and the erase voltage are set to 9.0 V (absolute value), the tunnel insulating film 6 is about 20 mm, the charge storage insulating film 5 is about 90 mm, and the top insulating film 4 is about 40 mm.

  The gate insulating film of the high breakdown voltage MOSFET provided in the high breakdown voltage element region 8 has a four-layer structure when the base insulating film 3 and the memory insulating film 7 are combined. Since the tunnel insulating film 6 and the base insulating film 3 are between the semiconductor substrate 1 and the charge storage insulating film 5, the film thickness is large, and the tunnel effect does not occur during or after the manufacture of the semiconductor device. The charge storage insulating film 5 is not charged.

  As shown in FIG. 1B, the gate electrode 12 a of the high voltage MOSFET formed in the high voltage element region 8 is provided in a predetermined shape on the base insulating film 3 and the memory insulating film 7. The gate electrode 12 b of the low breakdown voltage MOSFET formed in the low breakdown voltage element region 9 is provided in a predetermined shape on the base insulating film 3. The memory gate electrode 12 c of the MONOS type memory element formed in the MONOS type memory element region 10 is provided in a predetermined shape on the semiconductor substrate 1.

  The gate electrodes 12a and 12b and the memory gate electrode 12c can be formed of, for example, polysilicon.

  In the example shown in FIG. 1, the base insulating film 3 is not provided above the region 1a of the MONOS type memory element region 10, but the base insulating film 3 may be provided in this portion. This will be described in detail in a second embodiment described later.

In the example shown in FIG. 1, when source regions and drain regions (11 a and 11 b) are formed in the high breakdown voltage element region 8 and the low breakdown voltage element region 9, when impurity ions are introduced into the semiconductor substrate 1 using an ion implantation technique. May be ion-implanted so as to penetrate the base insulating film 3.
Similarly, when a source region or a drain region (11c) is formed in the MONOS type memory element region 10, ions may be implanted into the region 1a. A source region and a drain region are formed in the semiconductor substrate 1 by performing a predetermined thermal diffusion process after the ion implantation.

[Description of Manufacturing Method of First Embodiment: FIGS. 1 and 2]
Next, a manufacturing method will be described mainly using FIG.
FIG. 2 is a cross-sectional view schematically showing a method for manufacturing the structure shown in FIG. 1 in order. FIG. 2A shows a state in which the base insulating film 3 is formed after the element isolation step. FIG. 2B shows a state in which the memory insulating film 7 is sequentially formed. FIG. 2C shows a state in which the memory insulating film 7 is masked into a predetermined shape and etched.

  A feature of the manufacturing method of the first embodiment is that, after forming a high breakdown voltage element region 8, a low breakdown voltage element region 9, and a MONOS type memory element region 10 in an element isolation film provided on a semiconductor substrate, A low breakdown voltage gate insulating film (a gate insulating film of a low breakdown voltage MOSFET) is formed as a base insulating film at a time.

[First Insulating Film Forming Step: FIG. 2A]
As shown in FIG. 2A, the semiconductor substrate 1 is selectively oxidized to form an element isolation insulating film 2. This manufacturing process is formed by a known selective oxidation method called a LOCOS (LOCal Oxidation of Silicon) method. The film thickness of the element isolation insulating film 2 is, for example, about 5000 mm.

After the element isolation insulating film 2 is formed, the surface of the semiconductor substrate 1 is exposed, and this part is an element formation region. These element forming regions are a high withstand voltage element region 8, a low withstand voltage element region 9, and a MONOS type memory element region 10, respectively, and are regions for forming components such as a gate insulating film. Further, the element isolation insulating film 2 ensures electrical insulation from the adjacent element formation region.

  Next, the base insulating film 3 is formed. The base insulating film 3 is formed by a general thermal oxidation method. In the thermal oxidation method, an oxide film is grown by oxidizing silicon on the surface of the semiconductor substrate 1, so that the base insulating film 3 is formed in the entire region of the surface of the semiconductor substrate 1 where silicon is exposed.

Although the formation of the base insulating film 3 is performed by oxidizing the semiconductor substrate 1 in the above manufacturing method, the present invention is not limited to this.
For example, a silicon oxide film may be deposited on the upper portion of the semiconductor substrate 1 by a known CVD (Chemical Vapor Deposition) method or the like.

The base insulating film 3 is determined according to the operating voltage of the low breakdown voltage MOSFET.
As an example, when the operating voltage is 1.5 V (absolute value), it is about 100 V.

[Underlying film removal process]
Next, the surface of the semiconductor substrate 1 in the high withstand voltage element region 8 and the low withstand voltage element region 9 is masked, and only the base insulating film 3 in the MONOS type memory element region 10 is removed by etching. As a result, the surface of the semiconductor substrate 1 is exposed in the MONOS type memory element region 10.

  For example, a positive resist can be used as the coating film by masking. When this film is used, etching is performed using a hydrofluoric acid solution for about 20 seconds.

[Second Insulating Film Forming Step: FIG. 2B]
As shown in FIG. 2B, in order to form the memory insulating film 7 on the surface of the semiconductor substrate 1, first, the surface of the semiconductor substrate 1 is oxidized to form the tunnel insulating film 6. In the MONOS type memory element region 10, a tunnel insulating film 6 is formed on the surface of the semiconductor substrate 1, and in the high breakdown voltage element region 8 and the low breakdown voltage element region 9, tunnel insulation is formed above the base insulating film 3. A film 6 is formed.

  Then, the charge storage insulating film 5 is formed on the upper surface of the tunnel insulating film 6 by a known CVD method or the like, and the surface of the charge storage insulating film 5 is oxidized again to form the top insulating film 4.

  As an example, the oxidation condition of the tunnel insulating film 6 is 25 minutes at 900 ° C. when the film thickness is 20 mm. The oxidation condition of the top insulating film 4 is 29 minutes at 950 ° C. when the film thickness is 40 mm. The formation condition of the charge storage insulating film 5 by the CVD method is 6 minutes at 700 ° C. when the film thickness is 90 mm.

[Third Insulating Film Forming Step: FIG. 2 (c)]
As shown in FIG. 2C, masking is performed with a resist (not shown) so as to cover portions of the high breakdown voltage element region 8 and the MONOS type memory element region 10 where a gate electrode will be formed later. At this time, no resist for masking is provided in the low withstand voltage element region 9.

  Then, the top insulating film 4, the charge storage insulating film 5, and the tunnel insulating film 6 are etched by an etching process. This etching may be performed in a plurality of times by changing the etching conditions. As a result, the memory insulating film 7 in the high breakdown voltage element region 8 and the MONOS type memory element region 10 is processed into a predetermined shape and remains low. The memory insulating film 7 in the withstand voltage element region 9 is completely removed and etched so that only the base insulating film 3 remains.

  When the etching conditions for the etching process at this time are divided into a plurality of times by changing the etching conditions, for example, the top insulating film 4 is wet etched with a hydrofluoric acid solution for 15 seconds for each insulating film. The charge storage insulating film 5 is dry-etched for 1 minute with a fluorocarbon gas, and the tunnel insulating film 6 is wet-etched for 35 seconds with a hydrofluoric acid solution.

  By this etching process, the memory insulating film 7 disappears in the low breakdown voltage element region 9 and the base insulating film 3 is exposed, whereby a low breakdown voltage gate insulating film (a gate insulating film of a low breakdown voltage MOSFET) is formed. .

  Through the above manufacturing process, a four-layer gate insulating film composed of the base insulating film 3 and the memory insulating film 7 is formed on the surface of the high withstand voltage element region 8, and a single layer composed of the base insulating film 3 is formed on the surface of the low withstand voltage element region 9. A low-breakdown-voltage gate insulating film is formed, and three layers of memory gate insulating films made of the memory insulating film 7 are formed on the surface of the MONOS type memory element region 10.

  Later, polysilicon is formed on the upper portion of the semiconductor substrate 1 with a predetermined film thickness, and the high breakdown voltage element region 8, the low breakdown voltage element region 9, and the MONOS type memory element region 10 are formed in FIG. As shown in (b), the gate electrodes 12a and 12b and the memory gate electrode 12c are formed in a predetermined shape.

  Moreover, since the manufacturing process after this, for example, the formation process of the source region and the drain region (11a to 11c) and the metal wiring formation process, etc. are used, a description thereof will be omitted.

Hereinafter, a second embodiment of the semiconductor device will be described with reference to FIGS.
As described above, the second embodiment is an example in which a high withstand voltage gate insulating film which is a gate insulating film of a high withstand voltage MOSFET is used as the base insulating film.

[Structure of Second Embodiment: FIG. 3]
First, the structure will be described with reference to FIG.
FIG. 3 is a cross-sectional view schematically showing the structure of the semiconductor device. A gate insulating film and a high breakdown voltage element region, a low breakdown voltage element region, and a MONOS type memory element region are respectively formed by a manufacturing method described later. It is sectional drawing which shows typically the place which formed the memory insulating film.

  In FIG. 3, reference numeral 13 denotes a base insulating film, which in this embodiment is a high voltage gate insulating film. Reference numeral 3a denotes a gate insulating film of the low breakdown voltage MOSFET, which is an insulating film corresponding to the base insulating film 3 in the first embodiment.

A base insulating film 13 is formed on the surface of the semiconductor substrate 1 in the high voltage element region 8. The film thickness is determined in consideration of the operating voltage of the high breakdown voltage MOSFET, but since the memory insulating film 7 is also provided on the base insulating film 13, the high breakdown voltage MOSFET has a four-layer structure. What is necessary is just to design so that a pressure | voltage resistance may be ensured.
As an example, when the operating voltage is 9.0 V (absolute value), it is about 150 V.

  Of course, the base insulating film 13 alone may have a thickness sufficient to ensure the gate breakdown voltage of the high breakdown voltage MOSFET. Then, since the film thickness of the memory insulating film 7 on the upper side is also added, a higher breakdown voltage can be obtained.

In any case, in the high breakdown voltage element region 8, the tunnel insulating film 6 and the base insulating film 13 exist between the semiconductor substrate 1 and the charge storage insulating film 5. Alternatively, the tunnel effect does not occur even after manufacture, and the charge storage insulating film 5 is not charged.

Of the surface of the semiconductor substrate 1 in the high breakdown voltage element region 8, a low breakdown voltage gate insulating film 3 a that is a gate insulating film of a low breakdown voltage MOSFET is provided on the surface where the base insulating film 13 is not provided.
Similarly, the low-breakdown-voltage gate insulating film 3a is a surface of the surface of the semiconductor substrate 1 in the low-breakdown-voltage element region 9 and the surface of the semiconductor substrate 1 in the MONOS type memory element region 10 where the memory insulating film 7 is not provided. Also provided.

  In the first embodiment already described, the MONOS type memory element region 10 has the region 1a exposed, and when the source region or the drain region (11c) is formed, ions are implanted into this portion. Depending on the implantation conditions, ion implantation may cause damage due to ion collisions on the surface of the semiconductor substrate 1 in the region 1a.

  However, in the second embodiment shown in FIG. 3, the gate insulating film 3a for low withstand voltage is provided on the surface of the semiconductor substrate 1 in the region where each element is formed. When impurity ions are introduced into the semiconductor substrate 1, the gate insulating film 3a for low breakdown voltage is penetrated. In this way, the surface of the semiconductor substrate 1 is not damaged by ion collision regardless of the ion implantation conditions.

[Description of Manufacturing Method of Second Embodiment: FIGS. 3 and 4]
Next, a manufacturing method will be described mainly with reference to FIG.
FIG. 4 is a schematic cross-sectional view for sequentially explaining the manufacturing method of the structure shown in FIG. FIG. 4A shows a state in which the base insulating film 13 is formed and the memory insulating film 7 is formed thereon after the element isolation step. The base insulating film 13 is not provided in the MONOS type memory element region 10. FIG. 4B shows a state in which the memory insulating film 7 is masked and etched into a predetermined shape and all the base insulating film 13 is removed in the low breakdown voltage element region 9. FIG. 4C shows a state in which a low breakdown voltage gate insulating film 3a which is a gate insulating film of a low breakdown voltage MOSFET is formed on the surface of the semiconductor substrate 1 in each element region.

  The feature of the manufacturing method of the second embodiment is that after the high breakdown voltage element region 8, the low breakdown voltage element region 9, and the MONOS type memory element region 10 are formed in the element isolation insulating film 2 provided on the semiconductor substrate 1, these three A high-voltage gate insulating film (a gate insulating film of a high-voltage MOSFET) is formed as a base insulating film 13 at a time in the region, and the base insulating film 13 in each element region other than the high-voltage element region 8 is removed, Thus, a low breakdown voltage gate insulating film 3a (a gate insulating film of a low breakdown voltage MOSFET) is newly formed.

[First Insulating Film Forming Step: FIG. 4A]
As shown in FIG. 4A, an element isolation insulating film 2 is formed on a semiconductor substrate 1.
Next, the base insulating film 13 is formed. The base insulating film 13 is formed by a general thermal oxidation method. Since the oxide film is grown by oxidizing the silicon on the surface of the semiconductor substrate 1 in the thermal oxidation method, the base insulating film 13 is formed in the entire region of the surface of the semiconductor substrate 1 where silicon is exposed.

  The base insulating film 13 may be formed by being deposited by a known CVD method or the like as already described.

[Step of removing base insulating film: FIG. 4A]
Similarly, as shown in FIG.
The high breakdown voltage element region 8 and the low breakdown voltage element region 9 are covered and formed on the surface of the semiconductor substrate 1 in the MONOS type memory element region 10 using masking and etching techniques so that the MONOS type memory element region 10 is exposed. The underlying insulating film 13 is removed by etching. The condition at this time is, for example, wet etching with a hydrofluoric acid solution for about 20 seconds.

[Second Insulating Film Forming Step: FIGS. 4A and 4B]
Similarly, as shown in FIG. 4A, in order to form the memory insulating film 7 on the surface of the semiconductor substrate 1, first, the surface of the semiconductor substrate 1 is oxidized to form the tunnel insulating film 6. Then, the charge storage insulating film 5 is formed on the upper surface of the formed tunnel insulating film 6 by a known CVD method or the like, and the surface of the charge storage insulating film 5 is oxidized again to form the top insulating film 4. .

[Third Insulating Film Forming Step: FIG. 4B]
Next, the memory insulating film 7 is processed into a predetermined shape. In the high breakdown voltage element region 8 and the MONOS type memory element region 10, the shape of the memory insulating film 7 is formed using masking and etching techniques in accordance with the shape of the element. All 7 are removed.

  Next, masking is performed so that the surface of the semiconductor substrate 1 in the low breakdown voltage element region 9 is exposed, and the base insulating film 3 in the low breakdown voltage element region 9 is removed by etching. The condition at this time is, for example, wet etching with a hydrofluoric acid solution for about 20 seconds.

Next, as shown in FIG. 4C, a low breakdown voltage gate insulating film 3 a is formed on the semiconductor substrate 1.
Since the semiconductor substrate 1 is exposed in the low-breakdown-voltage element region 9 by a previous manufacturing process, the low-breakdown-voltage gate insulating film 3a is formed in accordance with the electrical characteristics of the low-breakdown-voltage MOSFET. It is good to decide. As an example, when the operating voltage of the low breakdown voltage MOSFET is 1.5 V (absolute value), it is about 100 V.

  Through the above manufacturing process, a four-layer gate insulating film composed of the base insulating film 13 and the memory insulating film 7 is formed on the surface of the high-breakdown-voltage element region 8, and a single-layer low-breakdown-voltage gate is formed on the surface of the low-breakdown-voltage element region 9. The insulating film 3a is formed by forming three layers of memory gate insulating films made of the memory insulating film 7 on the surface of the MONOS type memory element region 10, respectively.

  Note that description of the subsequent manufacturing steps (for example, a source region and a drain region formation step, a metal wiring formation step, etc.) is omitted.

Hereinafter, a third embodiment of the semiconductor device will be described with reference to FIGS.
In the third embodiment, as in the second embodiment, a high-breakdown-voltage gate insulating film that is a gate insulating film of a high-breakdown-voltage MOSFET is used as the base insulating film. The low breakdown voltage element region 9 is an example in which a part of the high breakdown voltage gate insulating film provided here is removed to form a gate insulating film of the low breakdown voltage MOSFET.

[Structure of Third Embodiment: FIG. 5]
First, the structure will be described with reference to FIG.
FIG. 5 is a cross-sectional view schematically showing the structure of the semiconductor device. A gate insulating film and a high breakdown voltage element region, a low breakdown voltage element region, and a MONOS type memory element region are respectively formed by a manufacturing method described later. It is sectional drawing which shows typically the place which formed the memory insulating film.

  In FIG. 5, 13a is a gate insulating film of a low breakdown voltage MOSFET formed by processing the base insulating film 13 which is also a gate insulating film of the high breakdown voltage MOSFET.

  A base insulating film 13 is formed on the surface of the semiconductor substrate 1 in the high voltage element region 8. The film thickness is about 150 mm when the operating voltage is 9.0 V (absolute value) as already exemplified.

  On the surface of the semiconductor substrate 1 in the low breakdown voltage element region 9, a low breakdown voltage gate insulating film 13 a is formed by processing the base insulating film 13 to reduce the film thickness. The film thickness of the low breakdown voltage gate insulating film 13a is, for example, about 100 mm when the operating voltage is 1.5 V (absolute value).

[Description of Manufacturing Method of Third Embodiment: FIGS. 5 and 6]
Next, a manufacturing method will be described mainly with reference to FIG.
FIG. 6 is a cross-sectional view schematically showing the method for manufacturing the structure shown in FIG. 5 in order. FIG. 6A shows a state in which the base insulating film 13 is formed and the memory insulating film 7 is formed thereon after the element isolation step. The base insulating film 13 is not provided in the MONOS type memory element region 10. FIG. 6B shows a state in which the base insulating film 13 in the low breakdown voltage element region 9 is processed to form a gate insulating film of the low breakdown voltage MOSFET.

  A feature of the manufacturing method of the third embodiment is that after the high breakdown voltage element region 8, the low breakdown voltage element region 9, and the MONOS type memory element region 10 are formed in the element isolation insulating film 2 provided on the semiconductor substrate 1, A high breakdown voltage gate insulating film (a gate insulating film of a high breakdown voltage MOSFET) is formed as a base insulating film 13 at a time in the region, and the base insulating film 13 formed in the low breakdown voltage element region 9 is thinly processed to reduce the low breakdown voltage. This is in the point of being a breakdown voltage gate insulating film 13a.

  The manufacturing method will be described below, but the steps already described will be omitted, and only the characteristic part will be described.

  As shown in FIG. 6A, the element isolation insulating film 2 and the base insulating film 13 are formed on the semiconductor substrate 1. Although not shown, the semiconductor substrate of the MONOS type memory element region 10 is covered by masking and etching techniques so as to cover the high withstand voltage element region 8 and the low withstand voltage element region 9 and expose the MONOS type memory element region 10. The base insulating film 13 formed on the surface of 1 is removed by etching. Thereafter, a memory insulating film 7 is formed on the surface of the semiconductor substrate 1.

[Third Insulating Film Forming Step: FIG. 6B]
Next, a mask 40 is formed using a masking technique so as to cover the high breakdown voltage element region 8 and the MONOS type memory element region 10 and expose the low breakdown voltage element region 9. Thereafter, all the memory insulating film 7 in the exposed low withstand voltage element region 9 is removed by an etching technique.

  Then, a part of the base insulating film 13 exposed in the low breakdown voltage element region 9 is removed using an etching technique. Specifically, the surface is removed by etching so as to reduce the film thickness. As an example, when the film pressure of the base insulating film 13 is about 150 mm, the low breakdown voltage gate insulating film 13a is set to about 100 mm. The condition at this time is, for example, dry etching for about 30 seconds using a fluorocarbon gas.

  According to the semiconductor device of the present invention, securing the withstand voltage of the high withstand voltage MOSFET and maintaining the withstand voltage of the low withstand voltage MOSFET can be formed with a small number of manufacturing steps, and therefore, it is suitable for a semiconductor device for electronic equipment with severe performance and cost.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation insulating film 3, 13 Base insulating film 3a, 13a Low breakdown voltage gate insulating film 4 Top insulating film 5 Charge storage insulating film 6 Tunnel insulating film 7 Memory insulating film 8 High breakdown voltage element region 9 Low breakdown voltage element Region 10 MONOS type memory device region

Claims (6)

A MOSFET type nonvolatile semiconductor memory element having a memory insulating film having a three-layer structure in which a tunnel insulating film, a charge storage insulating film, and a top insulating film are stacked;
In order to control a predetermined operation of the nonvolatile semiconductor memory element, a low breakdown voltage MOSFET having a low breakdown voltage gate insulating film and a high breakdown voltage MOSFET having a high breakdown voltage gate insulating film;
In a method for manufacturing a semiconductor device provided in a memory element region, a low breakdown voltage element region, and a high breakdown voltage element region provided in a semiconductor substrate,
A first insulating film forming step of simultaneously forming a base insulating film in the memory element region, the low withstand voltage element region, and the high withstand voltage element region;
A base insulating film removing step for removing the base insulating film in the memory element region;
After the base insulating film removal step, the tunnel insulating film, the charge storage insulating film, and the top insulating film are simultaneously formed on the high withstand voltage element region, the low withstand voltage element region, and the memory element region from the semiconductor substrate side. A second insulating film forming step in which a memory insulating film is formed by sequentially stacking layers,
A third insulating film forming step of forming the low breakdown voltage gate insulating film in the low breakdown voltage element region after the second insulating film forming step;
A method for manufacturing a semiconductor device, comprising: The base insulating film is the low breakdown voltage gate insulating film;
2. The semiconductor according to claim 1, wherein the third insulating film forming step forms the low withstand voltage gate insulating film by removing the memory insulating film in the low withstand voltage element region. 3. Device manufacturing method. The base insulating film is the high voltage gate insulating film;
In the third insulating film forming step, the memory insulating film and the base insulating film in the low breakdown voltage element region are removed to expose the surface of the semiconductor substrate, and then the low breakdown voltage gate insulating film is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device. The base insulating film is the high voltage gate insulating film;
In the third insulating film forming step, the low-voltage gate insulating film is formed by removing the memory insulating film in the low-breakdown-voltage element region and removing a part of the base insulating film. The method of manufacturing a semiconductor device according to claim 1. A MOSFET type nonvolatile semiconductor memory element having a memory insulating film having a three-layer structure in which a tunnel insulating film, a charge storage insulating film, and a top insulating film are stacked;
In order to control a predetermined operation of the nonvolatile semiconductor memory element, a low breakdown voltage MOSFET having a low breakdown voltage gate insulating film and a high breakdown voltage MOSFET having a high breakdown voltage gate insulating film;
In a semiconductor device mixedly mounted on the same semiconductor substrate,
The high-breakdown-voltage MOSFET has the high-breakdown-voltage gate insulation film or the low-breakdown-voltage gate insulation film as a base insulation film, and has a four-layer structure gate insulation film provided with the memory insulation film thereon. A semiconductor device. The low breakdown voltage gate insulating film and the high breakdown voltage gate insulating film are made of the same material,
6. The semiconductor device according to claim 5, wherein the low breakdown voltage gate insulating film is thinner than the high breakdown voltage gate insulating film and thicker than the tunnel insulating film.

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