JP2013197340A - Manufacturing method of semiconductor light-emitting element wafer, semiconductor light-emitting element wafer, and susceptor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor light-emitting element wafer in which total number lighting inspection can be carried out in the early stage of the manufacturing process of a semiconductor light-emitting element at a low cost, and to provide a semiconductor light-emitting element wafer, and a susceptor.SOLUTION: In the manufacturing method of a semiconductor light-emitting element wafer including a semiconductor growth step for forming a semiconductor structure layer by laminating a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type, sequentially on a substrate, the semiconductor growth step includes an electrode formation step for generating an abnormal growth portion where at least a part of the first semiconductor layer is exposed by performing abnormal growth at a temperature lower than the growth temperature of the semiconductor structure layer in a partial region on the substrate, forming a first electrode on the second semiconductor layer of a normal growth portion other than the abnormal growth portion after ending the semiconductor growth step, and forming a second electrode connected with the first semiconductor layer exposed from the abnormal growth portion.

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting element wafer, a semiconductor light emitting element wafer, and a susceptor.

  Conventionally, the manufacturing process of a semiconductor light emitting device is roughly divided into three. The first is a semiconductor growth step, the second is a semiconductor process step, and the third is a package step. First, in the semiconductor growth process, in the case of a GaN-based semiconductor, crystal growth is performed by a vapor phase growth method using a wafer material such as sapphire, Si, or SIC as a crystal growth substrate. On the growth substrate by crystal growth, for example, as shown in Patent Document 1, a buffer layer made of Ga (x) Al (1-x) N, an n-type cladding layer doped with Si, and In A semiconductor structure layer of a light-emitting element is formed which includes an active layer made of (x) Ga (1-x) N and a p-type cladding layer doped with Mg.

  In the semiconductor process, processes such as p-type electrode formation, n-type electrode formation, element division, and light extraction structure formation are performed on the semiconductor structure layer on the growth substrate, thereby manufacturing the light-emitting element body.

  In the packaging process, processes such as wiring, phosphor coating, resin sealing, and the like are performed on the light emitting element body, and the product shape of the light emitting element is manufactured.

  An inspection process is required in each of these semiconductor growth processes, semiconductor process processes, and package processes. Typical examples of inspection processes from the semiconductor growth process to the semiconductor process process include the PL inspection process (PL-mapping: Photoluminescence-mapping) inspection process, the microscopic inspection process, and the 100% lighting inspection process. .

  The PL inspection process is the most common in the inspection process immediately after the growth of the semiconductor. The active layer is selectively excited by light irradiation to inspect whether the active layer is normal, and the film thickness using light interference is used. It consists of a process to check for abnormalities. The PL inspection process is an inspection process that can be performed at the earliest stage. The purpose of the PL inspection is not to flow a wafer with many defects in the subsequent process. However, not all factors that are judged to be defective by the PL inspection process can be specified. Therefore, a wafer having a defect due to an unspecified factor flows to a subsequent process.

  In the microscope observation step, the surface state of the semiconductor structure layer is observed with a microscope immediately after the growth of the semiconductor to find small pits and non-light emitting portions that cannot be found by the PL inspection. Further, for example, it is visually inspected by a microscope whether a resist patterned at the time of forming an electrode in a semiconductor process step is cleaned so as not to cause a defect in the next step. As described above, the microscope observation process is used in the inspection between the processes, and is used for confirming whether each process is normally performed rather than for the purpose of finding a defect of the wafer. Therefore, not all factors of defects can be specified even in the microscope observation process, and therefore wafers having defects due to factors that cannot be specified flow to the subsequent process.

  In the 100% lighting inspection process, a lighting inspection is performed in a state where all the light emitting elements are formed with electrodes and divided into elements, leaving the growth substrate. In this 100% lighting inspection process, when a defective portion is detected, the defective portion is removed. Since the current-voltage characteristic (IV characteristic) of the light emitting element can be easily inspected, the defect inspection process is the most reliable inspection process in the manufacturing stage of the semiconductor light emitting element.

  As described above, there are various inspection processes in the manufacturing process of the semiconductor light emitting device, and inspection is set up so that defective ones are not passed as much as possible to the subsequent processes.

  However, the most reliable 100% lighting inspection is performed at a stage close to the final process of the semiconductor manufacturing process.

JP-A-4-321280 JP 2005-93682 A

  The problem with the prior art lies in the defect detection process when a wafer is supplied to the semiconductor process process immediately after the semiconductor growth process is completed.

  For example, when manufacturing the light emitting element shown in Patent Document 1 or Patent Document 2, a PL inspection is first performed as a defect detection process immediately after the semiconductor growth process. There are three things that can be grasped by this PL inspection: (1) what is the emission wavelength, (2) discovery of a non-light emitting portion due to defective active layer, and (3) total film thickness of all layers. Therefore, if the defect is applicable to the above three, the abnormality of the wafer can be detected by the PL inspection immediately after the completion of the semiconductor growth process, and the defect does not flow to the subsequent process. However, the cause of failure is not only the failure of the active layer. For example, defects in the n-type cladding layer and the p-type cladding layer cannot be grasped by the PL inspection. The defect of the cladding layer includes, for example, that the n-type dopant (Si) and the p-type dopant (Mg) are not doped at an assumed concentration, and the crystallinity of the cladding layer is lowered. Moreover, the defect by interaction of each layer etc. can also be considered.

  It is also possible to insert a dedicated inspection process for these defects that cannot be grasped by the PL inspection. For example, for the dopant concentration inspection, hole measurement, secondary ion mass spectrometry (SIMS), carrier concentration analysis (ECV), or the like may be used. For crystallinity inspection, X-ray diffraction (XRD) may be used. However, it is practically impossible to perform all of these analyses. This is because the preparation time, analysis time, analysis time and the like necessary for each analysis in each process lead to a significant cost increase. Moreover, depending on the analysis, it becomes a destructive test, and after performing the analysis, it cannot be sent to the semiconductor process step.

  Furthermore, since there are too many ways to determine the cause of defects due to the interaction between layers, many analyzers are required to determine each factor.

  Therefore, there are not a few factors that cause a failure to be noticed until the final lighting test in the final stage of the semiconductor process is performed, and defects in the semiconductor growth stage are in units of wafers, so a large number of defects flow to the subsequent process. .

  After all, as long as the purpose of the semiconductor light-emitting element is to turn on, the lighting inspection is the most reliable method for determining whether a failure is caused or not. Therefore, performing the lighting inspection at an early stage of the manufacturing process of the semiconductor light emitting element is a method for preventing the most defects from being passed to the subsequent process.

  Therefore, when an attempt is made to perform a lighting test simply so that these defects can be found immediately after the completion of the semiconductor growth process, an n-type cladding layer is formed on the growth substrate immediately after the completion of the semiconductor growth process. Since the active layer and the p-type cladding layer are laminated semiconductor layers, the p-type electrode can be easily formed on the exposed p-type cladding layer, but the n-type cladding layer is not exposed. A mold electrode cannot be formed. When the n-type electrode is exposed, the p-type cladding layer and the active layer must be removed using an apparatus such as a dry etching apparatus, so that not only the inspection process is increased, but also the removal process of the p-type cladding layer and the active layer ( A new process of forming an n-type electrode and a p-type electrode must be incorporated. By introducing an inspection process aimed at reducing costs by early detection of defects, man-hours increase, which may lead to cost increases.

  Accordingly, an object of the present invention has been made in view of the above points, and a method for manufacturing a semiconductor light-emitting element wafer and a semiconductor capable of performing a complete lighting inspection at an early stage of the manufacturing process of the semiconductor light-emitting element at low cost A light emitting device wafer and a susceptor are provided.

  According to the method of manufacturing a semiconductor light emitting device wafer of the present invention, a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type are stacked in that order on a substrate. A method of manufacturing a semiconductor light emitting device wafer having a semiconductor growth step of forming a semiconductor substrate, wherein in the semiconductor growth step, the first region is abnormally grown at a temperature lower than a growth temperature of the semiconductor structure layer in a partial region on the substrate. Forming an abnormally grown portion in which at least a part of one semiconductor layer is exposed, and forming a first electrode on the second semiconductor layer of a normally grown portion other than the abnormally grown portion after the completion of the semiconductor growth step; It includes an electrode forming step of forming a second electrode connected to the first semiconductor layer exposed from the abnormally grown portion.

  The semiconductor light emitting device wafer of the present invention has a semiconductor structure layer on the surface of which a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type are grown and formed in that order. The light emitting device wafer, wherein the semiconductor structure layer is abnormally grown in which at least a part of the first semiconductor layer that is abnormally grown at a growth temperature lower than a growth temperature of the semiconductor structure layer is exposed in a partial region of the surface A first electrode disposed on the second semiconductor layer in a normal growth portion other than the abnormal growth portion, and a second electrode disposed on the first semiconductor layer exposed from the abnormal growth portion, It is characterized by having.

  The susceptor of the present invention is a susceptor on which a substrate is mounted for semiconductor growth, and has a low thermal conductivity portion having a low thermal conductivity to the substrate on a part of the mounting surface side of the substrate.

  According to the method for manufacturing a semiconductor light emitting device wafer of the present invention, in the semiconductor growth process, at least a part of the first semiconductor layer is exposed by abnormal growth at a temperature lower than the growth temperature of the semiconductor structure layer in a partial region on the substrate. After the semiconductor growth process is completed, a first electrode is formed on the second semiconductor layer of the normal growth portion other than the abnormal growth portion, and is connected to the first semiconductor layer exposed from the abnormal growth portion. Since the second electrode is formed, lighting inspection of the light emitting element on the wafer can be performed by supplying a current between the first electrode and the second electrode, and the manufacturing process of the semiconductor light emitting element is quick. It is possible to inspect all of the light emitting elements on the wafer at a low cost.

  According to the semiconductor light emitting device wafer of the present invention, at least a part of the first semiconductor layer abnormally grown at a growth temperature lower than the growth temperature of the semiconductor structure layer is exposed in a partial region of the semiconductor structure layer. A first electrode disposed on the second semiconductor layer of the normal growth portion other than the abnormal growth portion, including the abnormal growth portion, and a second electrode disposed on the first semiconductor layer exposed from the abnormal growth portion, Therefore, the lighting inspection of the light emitting element on the wafer can be performed by supplying a current between the first electrode and the second electrode. Further, if such a semiconductor light emitting element wafer is used, it is possible to perform a complete lighting inspection at a low cost at an early stage of the manufacturing process of the semiconductor light emitting element.

  According to the susceptor of the present invention, the first conductivity type is formed on the substrate by using the susceptor in the semiconductor growth process because the susceptor has a low thermal conductivity portion having a low thermal conductivity to the substrate on a part of the mounting surface side of the substrate. When a semiconductor structure layer of a light emitting element is formed by sequentially stacking a first semiconductor layer having an active layer and a second semiconductor layer having a second conductivity type in that order, the semiconductor is partially formed on the substrate in the semiconductor growth process. Abnormal growth at which at least a part of the first semiconductor layer is exposed can be generated by abnormal growth at a temperature lower than the growth temperature of the structural layer. After completion of the semiconductor growth process, the first electrode is formed on the second semiconductor layer in the normal growth portion other than the abnormal growth portion, and the second electrode is formed on the first semiconductor layer exposed from the abnormal growth portion. By supplying a current between the first electrode and the second electrode, it is possible to perform a lighting inspection of the light emitting element, and it is possible to perform a total lighting lighting inspection at a low cost at an early stage of the manufacturing process of the light emitting element.

It is a side view which shows the semiconductor growth apparatus used for the manufacturing method of the Example of this invention. It is the top view and side view which show the susceptor of the apparatus of FIG. It is sectional drawing which shows the semiconductor structure layer formed on the wafer of a semiconductor growth process. It is a top view, a cross-sectional view, and an enlarged cross-sectional view of a semiconductor structure layer in an electrode forming step. It is a figure which shows the metal mask used at an electrode formation process. It is a figure which shows the electric current path in the semiconductor structure layer at the time of a full lighting test process. It is a figure which shows the area | region removal of the light emitting element of a wafer. It is a figure which shows the state of the 100% lighting inspection process in the manufacturing method of the conventional semiconductor light-emitting device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a semiconductor growth apparatus used in the semiconductor growth process of the manufacturing method of the embodiment. The semiconductor growth apparatus includes a susceptor 11 and a heater 12. The susceptor 11 is made of carbon and is a disk-shaped pedestal on which the growth substrate 20 is mounted. The heater 12 is disposed on the lower surface side of the susceptor 11 and heats the growth substrate 20 via the susceptor 11.

  FIG. 2A shows the upper surface of the susceptor 11, that is, the mounting surface on which the growth substrate 20 is mounted, and FIG. 2B shows the side surface of the susceptor 11. As shown in FIGS. 1 and 2A and 2B, the susceptor 11 has a stepped portion 13 on the outer peripheral portion on the mounting surface side of the growth substrate 20. The step portion 13 is 0.5 to 1.0 mm in the radial direction from the outer periphery of the susceptor 11, and has a depth of 0.1 to 1.0 μm from the mounting surface. The step 13 is a portion that does not come into contact with the growth substrate 20, so that the growth temperature of the non-contact portion of the growth substrate 20 is lower by 20 ° C. or more than the normal growth temperature of the growth substrate 20 other than the step 13 of the susceptor 11. Is formed. The step portion 13 corresponds to a low thermal conductivity portion with low thermal conductivity to the substrate 20.

  The growth substrate 20 is a substrate such as a sapphire substrate and has insulating properties and translucency. The growth substrate 20 has a region where semiconductor structure layers for a plurality of light emitting elements can be formed.

  In the semiconductor growth process, using the semiconductor growth apparatus shown in FIG. 1, as shown in FIG. 3, a gallium nitride (GaN) based semiconductor is grown on the growth substrate 20 by using MOCVD (metal organic chemical vapor deposition). A semiconductor light-emitting element wafer having a normal growth portion 21 of the semiconductor structure layer and an abnormal growth portion 22 adjacent to the normal growth portion 21 is formed. The normal growth portion 21 is a growth portion corresponding to a portion other than the step portion 13 on the mounting surface of the susceptor 11 and is a portion that is normally grown at a normal growth temperature. The abnormal growth portion 22 is a growth portion corresponding to the step portion 13 on the mounting surface, and as described above, is a portion abnormally grown at a growth temperature that is 20 ° C. lower than the normal growth temperature.

  An n-type cladding layer 25 (first semiconductor layer), an active layer 26 having a multiple quantum well structure, and a p-type cladding layer 27 (second semiconductor layer) are stacked in that order from the growth substrate 20 side in the normal growth portion 21. A semiconductor structure layer is formed. On the other hand, the abnormal growth portion 22 is grown at a temperature lower than the growth temperature of the normal growth portion 21, and the abnormal growth portion 22 is formed with an n-type cladding layer 25, an active layer 26, and a p-type cladding layer 27 that are abnormally grown. . However, the boundaries between the abnormally grown n-type cladding layer 25, active layer 26, and p-type cladding layer 27 are indicated by broken lines in FIG. 3, but they may not be clear. Further, the surface of the abnormally grown portion 22 is an uneven surface, and a part of the n-type cladding layer 25 of the abnormally grown portion 22 is exposed as shown as the exposed portion 28 in FIG.

As a specific method for forming the semiconductor structure layer, for example, first, the growth substrate 20 is carried into the above-described MOCVD method semiconductor growth apparatus and subjected to a heat treatment in a hydrogen atmosphere at 1000 ° C. for about 10 minutes. . Subsequently, the ambient temperature is adjusted to about 500 ° C., and TMG (trimethyl gallium) (flow rate: 10.4 μmol / min) and NH ₃ (flow rate: 3.3 LM) are supplied for about 3 minutes. Not shown). Thereafter, the ambient temperature is raised to about 1000 ° C., and this state is maintained for about 30 seconds, whereby the low-temperature buffer layer is crystallized. Subsequently, TMG (flow rate: 45 μmol / min) and NH ₃ (flow rate: 4.4 LM) are supplied for about 20 minutes while the ambient temperature is maintained at about 1000 ° C., so that the film thickness is about 1 μm. A base GaN layer 13 is formed. Next, when the ambient temperature is about 1000 ° C., TMG (flow rate: 45 μmol / min), NH ₃ (flow rate: 4.4 LM) and SiH ₄ (flow rate: 2.7 × 10 ⁻⁹ mol / min) as the dopant gas are about By supplying for 100 minutes, the n-type GaN layer which is the n-type cladding layer 25 having a film thickness of about 5 μm is formed.

Subsequently, an InGaN / GaN layer having a multiple quantum well structure as the active layer 26 is formed on the n-type cladding layer 25. In the active layer 26, growth is performed for five periods with InGaN / GaN as one period. Specifically, TMG (flow rate: 3.6 μmol / min), TMI (trimethylindium) (flow rate: 10 μmol / min), and NH ₃ (flow rate 4.4 LM) are supplied for about 33 seconds in an ambient temperature of about 700 ° C. As a result, an InGaN well layer having a thickness of about 2.2 nm is formed. Subsequently, TMG (flow rate: 3.6 μmol / min) and NH ₃ (flow rate: 4.4LM) are supplied for about 320 seconds, thereby forming a GaN barrier layer having a thickness of about 15 nm. The active layer 26 is formed by repeating this process for five cycles.

Next, the ambient temperature was raised to about 800 ° C., TMG (flow rate: 8.1 μmol / min), TMA (trimethylaluminum) (flow rate: 7.5 μmol / min), NH ₃ (flow rate: 4.4 LM) and Cp as a dopant. ₂ Mg (bis-cyclopentadienyl magnesium) (flow rate: 2.9 × 10 ⁻⁷ μmol / min) is supplied for about 5 minutes, so that a p-type AlInGaN layer (not shown) having a film thickness of about 40 nm is formed. ) Is formed. Subsequently, while maintaining the ambient temperature at about 800 ° C., TMG (flow rate: 18 μmol / min), NH ₃ (flow rate: 4.4 LM) and Cp ₂ Mg as a dopant (flow rate: 2.9 × 10 ⁻⁷ μmol / min) min) is supplied for about 7 minutes, whereby a p-type GaN layer which is a p-type cladding layer 27 having a thickness of about 150 nm is formed.

  After completion of the semiconductor growth process, an electrode formation process is performed. In the electrode formation step, as shown in FIGS. 4A to 4C, a p-electrode 31 (first electrode) is formed on the p-type cladding layer 27 of the normal growth portion 21 in units of light emitting elements, and abnormal An n-electrode 32 (second electrode) is formed so as to fill the uneven surface of the growth portion 22, whereby the n-electrode 32 comes into contact with the exposed portion 28 of the n-type cladding layer 25. 4A is a top view of the semiconductor structure layer during the electrode formation process, FIG. 4B is a cross-sectional view taken along the line XX in FIG. 4A, and FIG. It is a cross-sectional enlarged view of the abnormal growth part 22 of FIG.4 (b).

  The electrodes 31 and 32 are formed by a resistance heating vapor deposition method using a metal mask 35 as shown in FIG. In the metal mask 35, through holes 35a for p electrodes and through holes 35b for n electrodes are formed for a plurality of wafers. As the electrodes 31 and 32, Ni (film thickness of about 100 μm) / Au (film thickness of about 100 μm) electrodes can be used. Ni is used for making contact with the GaN crystal, and Au is used for preventing oxidation of Ni and reducing contact resistance with the probes (reference numerals 42 and 43 in FIG. 6). As shown in FIG. 5, the metal mask 35 can further improve the efficiency of the electrode formation process by allowing electrodes to be formed simultaneously on a plurality of wafers (that is, a plurality of the growth substrates 20 described above).

  After the electrode formation, as shown in FIG. 6, a lighting inspection process is performed using the n electrode 32 formed in the abnormal growth portion 22 as a common n electrode for each of the plurality of p electrodes 31. In the lighting inspection process, a current is supplied from the power supply device 41 between the plurality of p electrodes 31 and the common n electrode 32. Further, probes 42 and 43 are used for connection with the electrodes 31 and 32 for supplying current from the power supply device 41.

  The p-type cladding layer 27 of the GaN-based semiconductor light-emitting element formed in the normal growth portion 21 formed in the above-described semiconductor growth process has a very large electric resistance with respect to the n-cladding layer 25, and particularly perpendicular to the stacking direction. Current does not flow in any direction. Therefore, even if the n-electrode 32 is in contact with the side surface of the p-type cladding layer 27, no current is diffused in the p-type cladding layer 27 as shown by the current path A in FIG. Since current is diffused in the cladding layer 25, it is possible to use the common n-electrode 32 of the abnormal growth portion 22. Therefore, even when only the p-electrode 31 is separately provided for each light-emitting element, the current does not diffuse in the p-type cladding layer 27. Therefore, if the normal growth portion 21 is a normal semiconductor structure layer for each light-emitting element, the p-electrode is used. The active layer 26 immediately below 31 emits light. The light emission state of the active layer 26 immediately below each p-electrode 31 is observed from the growth substrate 20 side. In this way, the characteristics of light emission can be evaluated in units of light emitting elements. Therefore, an inspection equivalent to the full lighting inspection of the semiconductor light emitting elements performed at the end of the semiconductor process is performed just by forming the electrodes 31 and 32 immediately after the semiconductor growth process. Can be done.

  In the lighting inspection process, the lighting inspection for all the light emitting elements on the growth substrate 20 is not limited, and the lighting inspection for some of the light emitting elements may be performed. In addition, the lighting inspection may be performed by forming the p-electrode 31 in units of regions of the semiconductor structure layer corresponding to a plurality of light emitting elements, without being limited to the lighting inspection in units of light emitting elements.

  After the lighting inspection process, the p electrode 31 and the n electrode 32 are removed by washing with aqua regia (electrode removal process). Thereafter, it is possible to shift to a normal semiconductor process step and a packaging step.

  Since the surface of the abnormally grown portion 22 on which the n-electrode 32 is formed is an uneven surface, it is difficult to completely remove the electrode even with aqua regia cleaning, but the abnormally grown portion 22 is not necessary in the subsequent element dividing step. Since it becomes an area, even if there is a residue of the n-electrode 32, there is no adverse effect on the subsequent process.

  As described above, by performing the electrode formation process and the lighting inspection process after the semiconductor growth process and before the semiconductor process process, the conventional PL inspection or the like immediately after the semiconductor growth process is completed. The semiconductor light emitting element wafer, which has been difficult to determine as defective in the inspection, is no longer passed to the subsequent semiconductor process step. Further, since the above lighting inspection is a non-destructive inspection, the semiconductor light emitting element wafer after the lighting inspection process can be used as it is for the production of a semiconductor light emitting element in the semiconductor process step.

  Further, as the abnormal growth portion 22, a region that is not used as a light emitting element region in the wafer is used. FIG. 7 shows the area of the light emitting element on the wafer 51, and the square indicated by reference numeral 52 is the area of one light emitting element. A region B on the outer peripheral side of each region 52 of the light emitting element is a region in which the light emitting element cannot normally be formed. Since such an outer peripheral region is used for the abnormal growth portion 22, the final number of semiconductor light emitting elements is not reduced.

  FIG. 8 shows the state of the 100% lighting inspection process in the conventional method for manufacturing a semiconductor light emitting device. This 100% lighting inspection process is performed after p-type electrode formation, n-type electrode formation, and element division are performed in the semiconductor process for each light emitting element on the growth substrate 61. In FIG. 8, an n-type cladding layer 62, an active layer 63, and a p-type cladding layer 64 are stacked in this order on a growth substrate 61 to form semiconductor structure layers for two light emitting elements. An n-electrode 65 is formed on the n-type cladding layer 62, and a p-electrode 66 is formed on the p-type cladding layer 64. In the 100% lighting inspection step of FIG. 8, a current is supplied from a power supply device (not shown) using a probe (not shown) between the n electrode 65 and the p electrode 66 in units of light emitting elements. A current flows between the n-electrode 65 and the p-electrode 66 for each light-emitting element as shown by a current path C in FIG. 8, thereby checking whether the active layer 63 emits light.

  The total number lighting inspection process in this conventional method for manufacturing a semiconductor light emitting device can only be performed at the final stage in which the p-type electrode formation, the n-type electrode formation, and the element division are performed in the semiconductor process. The lighting inspection process shown in the example can be executed immediately after the completion of the semiconductor growth process, and in addition, the light emitting quality of all the light emitting elements on the wafer can be inspected in the same manner as the conventional 100% lighting inspection process. With respect to defects in the entire wafer that could not be detected in the normal inspection process in the semiconductor growth process, conventionally, the defective wafer is not recognized until the final stage of the semiconductor process process, but the manufacturing process proceeds according to the embodiment. Then, it is possible to determine a defective wafer at an early stage such as immediately after the completion of the semiconductor growth process in all the manufacturing processes. Therefore, it is not necessary to transfer the defective wafer in the state where the semiconductor growth process is completed to the semiconductor process process by executing the lighting inspection process shown in the embodiment.

  Further, in the manufacturing method of the embodiment, a simple IV characteristic or in-wafer plane can be obtained by measuring the current flowing through the electrode 31 or 32 from the power supply device 41 or the voltage between the electrodes 31 and 32 for each element. It is also possible to grasp the dispersion characteristics of the wafers and to repel wafers with poor characteristics.

  Further, conventionally, in order to perform the complete lighting inspection process immediately after the completion of the semiconductor growth process, it is necessary to expose the n cladding layer and provide the n electrode. Immediately after the completion of the semiconductor growth process, for example, a resist coating process, a photolithography process, a resist forming process, a dry etching process, a resist cleaning process, an electrode forming process, a total lighting inspection, and an electrode removal cleaning process must be incorporated. However, it is inevitable to increase the cost by incorporating such many processes. On the other hand, in the manufacturing method shown in the embodiment, since the abnormally grown portion 22 where the n-type cladding layer 25 is exposed is formed in the semiconductor growth process in order to provide the n electrode, the conventional n electrode is provided. A large number of steps (from the resist coating step to the resist cleaning step in the above example) are unnecessary, and the cost can be reduced.

  In the above-described embodiment, the susceptor 11 is provided with the step portion 13 as the low heat conduction portion in order to form the abnormal growth portion 22, and the temperature of the portion of the growth substrate 20 corresponding to the step portion 13 is lowered by 20 degrees or more. However, the method of forming the abnormal growth portion 22 in the present invention is not limited to this, and is formed on a part of the mounting surface side of the growth substrate 20 by, for example, a member having low thermal conductivity to the growth substrate 20. Any susceptor may be used as long as the growth temperature of a part of the substrate is lower than that of other parts, such as having a low heat conduction part. Further, a stepped portion or a groove portion may be provided on the lower surface of the region where the abnormally grown portion of the growth substrate 20 is to be formed.

  In the above-described embodiment, the GaN-based semiconductor structure layer in which the n-type cladding layer 25, the active layer 26, and the p-type cladding layer 27 are stacked in that order from the growth substrate 20 side is shown. The present invention is not limited to the semiconductor structure layer, and can be applied to other crystal systems, for example, other crystal system semiconductor structure layers such as GaAs. In the above-described embodiments, the first conductivity type is n-type, and the second conductivity type opposite to the first conductivity type is p-type. However, the present invention sets the first conductivity type to p-type. The present invention can also be applied to a semiconductor structure layer in which the second conductivity type is n-type. That is, in the present invention, a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type are stacked in this order on a growth substrate, thereby providing a semiconductor for a plurality of light emitting elements. Any semiconductor light-emitting element having a semiconductor growth process for forming a structural layer can be applied, and a complete lighting test can be performed at an early stage of the manufacturing process of the semiconductor light-emitting element at a low cost.

20, 61 Growth substrate 21 Normal growth portion 22 Abnormal growth portion 25, 62 n-type cladding layer 26, 63 active layer 27, 64 p-type cladding layer 28 exposed portion 31, 66 p-electrode 32, 65 n-electrode

Claims (10)

A semiconductor light emitting device wafer having a semiconductor growth step in which a semiconductor structure layer is formed by sequentially stacking a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type on a substrate. A manufacturing method of
In the semiconductor growth step, an abnormal growth portion in which at least a part of the first semiconductor layer is exposed by abnormal growth at a temperature lower than a growth temperature of the semiconductor structure layer in a partial region on the substrate is generated,
After completion of the semiconductor growth step, a first electrode is formed on the second semiconductor layer in a normal growth portion other than the abnormal growth portion, and a second electrode connected to the first semiconductor layer exposed from the abnormal growth portion is formed. The manufacturing method characterized by including the electrode formation process which forms an electrode. The semiconductor structure layer is a GaN (gallium nitride) based semiconductor structure layer,
The manufacturing method according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The manufacturing method according to claim 1, further comprising: a lighting inspection step of supplying a current between the first electrode and the second electrode to perform a lighting inspection of the semiconductor light emitting element wafer. .   The manufacturing method according to claim 3, further comprising an electrode removal step of removing the first electrode and the second electrode after the lighting inspection step.   5. The susceptor having a low thermal conductivity portion having a low thermal conductivity to the substrate is used in a part of the substrate mounting surface side in the semiconductor growth step. Production method. A semiconductor light emitting device wafer having a semiconductor structure layer on a surface of which a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type are grown and formed in that order;
The semiconductor structure layer includes an abnormally grown portion in which at least a part of the first semiconductor layer that is abnormally grown at a growth temperature lower than the growth temperature of the semiconductor structure layer is exposed in a partial region of the surface;
A first electrode disposed on the second semiconductor layer in a normal growth portion other than the abnormal growth portion;
And a second electrode disposed on the first semiconductor layer exposed from the abnormally grown portion. The semiconductor structure layer is a GaN (gallium nitride) based semiconductor structure layer,
The semiconductor light-emitting element wafer according to claim 6, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The semiconductor light emitting element wafer according to claim 6, wherein the partial region is an outer peripheral portion of the surface. A susceptor for mounting a substrate for semiconductor growth,
A susceptor comprising a low thermal conductivity portion having a low thermal conductivity to the substrate on a part of the mounting surface side of the substrate.   The susceptor according to claim 9, wherein the low thermal conductivity portion is a stepped portion that is recessed in a direction perpendicular to the mounting surface.

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