JP2013190960A - Semiconductor memory reuse processor and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory reuse processor which can simplify the system configuration of a memory system and reduce a product cost.SOLUTION: A reuse processor 10 comprises: a storage unit 26 that stores a plurality of logics L0 to L5; an acquisition unit 21 that acquires, from a collected semiconductor memory 1, management information S1 for specifying a deteriorated block out of a plurality of blocks included in the semiconductor memory 1; a logic specification unit 22 that specifies an optimum logic, out of the plurality of logics L0 to L5, for which the number of deteriorated blocks in an area is most leveled between areas on the basis of the management information S1; and a logic update unit 23 that updates a logic selected by the collected semiconductor memory 1 to the optimum logic by outputting selection information S3 for selecting the optimum logic specified by the logic specification unit 22 to the semiconductor memory 1.

Description

  The present invention relates to a semiconductor memory reuse processing apparatus and a semiconductor memory.

  In a rewritable semiconductor memory such as a flash memory, there is a utilization form in which a semiconductor memory that has been used once is collected, and the semiconductor memory that has been used once is reused by re-shipping after rewriting the data. .

  Also, wear leveling is known as a technique for improving the number of rewritable times in a rewritable semiconductor memory.

  For example, Patent Document 1 below discloses a flash memory system including a controller and a flash memory. The flash memory is divided into a plurality of zones, and each zone includes a plurality of blocks as data erasing units. In order to prevent bad blocks from concentrating on a specific zone, the controller maps the virtual block address to the physical block address so that the number of bad blocks classified into each of the zones is averaged. Set the relationship.

JP-A-2005-209140

  However, if the wear leveling function is mounted on the memory system, the system configuration becomes complicated and the product cost increases. Therefore, particularly in a utilization form in which the semiconductor memory is reused, it is desired to improve the reliability of the reused semiconductor memory by a simple and low-cost system configuration in which the wear leveling function is not mounted on the memory system. Yes.

  SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and in a utilization mode in which a semiconductor memory is reused, the system configuration of the memory system is simplified by omitting the implementation of the wear leveling function on the memory system. An object of the present invention is to obtain a semiconductor memory reuse processing apparatus and semiconductor memory capable of reducing the product cost.

  A semiconductor memory reuse processing apparatus according to a first aspect of the present invention collects used semiconductor memory for a semiconductor memory that manages defective blocks in area units including a plurality of blocks that are data erasing units. A semiconductor memory reuse processing apparatus that performs predetermined reuse processing on the semiconductor memory before reshipment for reuse, and includes a plurality of logical-physical address conversion logics held in the semiconductor memory. A storage unit that stores a plurality of corresponding logical-physical address conversion logics; an acquisition unit that acquires predetermined management information for identifying a deteriorated block among a plurality of blocks included in the semiconductor memory; Based on the management information acquired by the acquisition unit, the plurality of logical-physical address changes stored in the storage unit. A logic specifying unit that specifies an optimum logical-physical address conversion logic in which the number of deteriorated blocks in the area is leveled most among the areas, and the optimal logical-physical address specified by the logic specifying unit. By outputting selection information for selecting a conversion logic to the collected semiconductor memory, the logical-physical address conversion logic selected by the semiconductor memory is updated to the optimum logical-physical address conversion logic. And a logic updating unit.

  According to the semiconductor memory reuse processing apparatus according to the first aspect, the acquisition unit acquires management information for identifying a deteriorated block from the collected semiconductor memory. In addition, the logic identification unit equalizes the number of deteriorated blocks in the area most frequently among the areas among a plurality of logical-physical address conversion logics stored in the storage unit based on the management information acquired by the acquisition unit. Identify the optimal logical-to-physical address translation logic to be used. Then, the logic updating unit outputs selection information for selecting the optimum logical-physical address conversion logic specified by the logic specifying unit to the collected semiconductor memory, whereby the logic selected by the semiconductor memory is output. Update the physical address translation logic to the optimal logical-physical address translation logic. Therefore, even if the deteriorated blocks are concentrated in a specific area in the collected semiconductor memory, the semiconductor memory re-shipped after the reuse process is updated to the optimum logical-physical address conversion logic. The area is reconstructed so that the number of deteriorated blocks is leveled. Therefore, it is possible to avoid a situation in which the reshipped semiconductor memory immediately fails. In addition, since the logical-physical address conversion logic is updated by the reuse process, it is not necessary to implement the wear leveling function in the semiconductor memory. As a result, it is possible to simplify the system configuration of the semiconductor memory and reduce the product cost.

  The semiconductor memory reuse processing apparatus according to the second aspect of the present invention corresponds to the optimum logical-physical address conversion logic identified by the logic identification unit, particularly in the semiconductor memory reuse processing apparatus according to the first aspect. A table creation unit that creates a new bad block management table, and the new bad block management table created by the table creation unit is output to the collected semiconductor memory, whereby the semiconductor memory holds the table. And a table updating unit that updates the new bad block management table to the new bad block management table.

  According to the semiconductor memory reuse processing apparatus according to the second aspect, the table creation unit creates a new defective block management table corresponding to the optimum logical-physical address conversion logic identified by the logic identification unit. Then, the table update unit outputs the new bad block management table created by the table creation unit to the collected semiconductor memory, so that the bad block management table held by the semiconductor memory is changed to a new defective block. Update the block management table. Therefore, in the semiconductor memory that is reshipped after the reuse process, it is possible to appropriately manage the defective blocks based on the updated new defective block management table.

  The semiconductor memory reuse processing apparatus according to the third aspect of the present invention is characterized in that, in the semiconductor memory reuse processing apparatus according to the first or second aspect, the deteriorated block includes an acquired defective block. It is what.

  According to the semiconductor memory reuse processing apparatus according to the third aspect, the deteriorated block includes the acquired defect block. Therefore, in the re-shipped semiconductor memory, the number of deteriorated blocks including acquired defective blocks is leveled between areas, so that the occurrence of failures due to concentration of deteriorated blocks in a specific area is avoided. It becomes possible to do.

  The semiconductor memory reuse processing apparatus according to the fourth aspect of the present invention is the semiconductor memory reuse processing apparatus according to any one of the first to third aspects, in particular, the degraded block has a predetermined number of rewrites. It is characterized in that the exceeding block is included.

  According to the semiconductor memory reuse processing apparatus of the fourth aspect, the deteriorated block is a block whose number of rewrites exceeds a predetermined value, that is, a block that is likely to become an acquired defective block due to frequent rewrites (quasi-defective block). Is included. Therefore, in the re-shipped semiconductor memory, the number of deteriorated blocks including the quasi-defective blocks is leveled between the areas, so that the occurrence of a failure due to the concentration of the deteriorated blocks in a specific area is avoided. It becomes possible.

  The semiconductor memory reuse processing apparatus according to the fifth aspect of the present invention is the semiconductor memory reuse processing apparatus according to any one of the first to fourth aspects. In particular, the logic specifying unit has a total number of deteriorated blocks. A semiconductor memory having a predetermined value or more is determined as a defective product.

  According to the semiconductor memory reuse processing apparatus according to the fifth aspect, the logic specifying unit determines that a semiconductor memory having a total number of deteriorated blocks equal to or larger than a predetermined value is defective. Therefore, a semiconductor memory having the total number of deteriorated blocks equal to or larger than a predetermined value is disposed as a defective product and is not reshipped, so that it is possible to avoid in advance a situation in which the reshipped semiconductor memory immediately fails.

  The semiconductor memory reuse processing apparatus according to the sixth aspect of the present invention is the semiconductor memory reuse processing apparatus according to any one of the first to fifth aspects, in particular, the logic specifying unit is a semiconductor after reshipment. When there is an unused area that is not used in the memory, a logical-physical address conversion logic in which an area where degraded blocks occur frequently in the semiconductor memory at the time of collection is assigned to the unused area is referred to as the optimal logic. -It is specified as physical address translation logic.

  According to the semiconductor memory reuse processing apparatus of the sixth aspect, when there is an unused area that is not used in the semiconductor memory after re-shipment, the logic specifying unit has a deteriorated block in the semiconductor memory at the time of collection. The logical-physical address conversion logic assigned to the unused area is specified as the optimum logical-physical address conversion logic. By assigning an area where degraded blocks occur frequently to an unused area, the number of degraded blocks in other areas (that is, used areas) is reduced, so that the reliability of re-shipped semiconductor memory can be improved. It becomes possible.

  The semiconductor memory reuse processing apparatus according to the seventh aspect of the present invention is the semiconductor memory reuse processing apparatus according to any one of the first to sixth aspects, in particular, the logic specifying unit includes a deterioration block in the area. The best logic having the smallest number is specified as the optimum logical-physical address conversion logic.

  According to the semiconductor memory reuse processing apparatus of the seventh aspect, the logic specifying unit specifies the best logic having the smallest maximum number of deteriorated blocks in the area as the optimum logical-physical address conversion logic. By selecting the best logic with the smallest maximum number of deteriorated blocks, the number of deteriorated blocks in the area is effectively leveled, so that the reliability of the re-shipped semiconductor memory can be improved. .

  The semiconductor memory reuse processing apparatus according to the eighth aspect of the present invention is the semiconductor memory reuse processing apparatus according to the seventh aspect, in particular, when the logic specifying unit includes a plurality of best logics. Among these best logics, the logic having the smallest difference between the maximum value and the minimum value of the number of deteriorated blocks in the area is specified as the optimum logical-physical address conversion logic.

  According to the semiconductor memory reuse processing apparatus according to the eighth aspect, when there are a plurality of best logics, the logic specifying unit includes a maximum value and a minimum number of degraded blocks in the area among the plurality of best logics. The logic having the smallest difference from the value is specified as the optimum logical-physical address conversion logic. By selecting the logic with the smallest difference between the maximum value and the minimum value of the number of deteriorated blocks, the number of deteriorated blocks in the area is leveled to the maximum, thereby improving the reliability of the re-shipped semiconductor memory. It becomes possible.

  The semiconductor memory reuse processing apparatus according to the ninth aspect of the present invention is the semiconductor memory reuse processing apparatus according to the eighth aspect, in which the logic specifying unit has the smallest difference between the maximum value and the minimum value. When there are a plurality of logics, an arbitrary logic among the plurality of logics is specified as the optimum logical-physical address conversion logic.

  According to the semiconductor memory reuse processing apparatus according to the ninth aspect, when there are a plurality of logics having the smallest difference between the maximum value and the minimum value, the logic specifying unit can select any of the plurality of logics. The logic is identified as the optimal logical-physical address translation logic. This makes it possible to appropriately select one logic used for area reconstruction.

  A semiconductor memory reuse processing apparatus according to a tenth aspect of the present invention is the semiconductor memory reuse processing apparatus according to any one of the seventh to ninth aspects, in particular, the logic specifying unit includes a deterioration block in the area. When the maximum value of the number is equal to or greater than a predetermined value for all logics, the semiconductor memory is determined to be defective.

  According to the semiconductor memory reuse processing apparatus of the tenth aspect, the logic specifying unit rejects the semiconductor memory when the maximum number of deteriorated blocks in the area is equal to or greater than a predetermined value for all logics. Judge as good. Therefore, by avoiding re-shipment of a semiconductor memory in which the level of the number of deteriorated blocks is not expected even if any logic is applied, it is avoided in advance that the re-shipped semiconductor memory immediately fails. It becomes possible.

  A semiconductor memory according to an eleventh aspect of the present invention includes a holding unit that holds a plurality of logical-physical address conversion logics, and a plurality of logical-physical address conversion logics that are held by the holding unit. And a selection unit that selects the logical-physical address conversion logic of the storage unit. The selection unit is configured to select the logical unit based on selection information input from a logic update unit included in the reuse processing device according to claim 1. One logical-physical address conversion logic is selected from the plurality of logical-physical address conversion logics held.

  According to the semiconductor memory of the eleventh aspect, the selection unit is configured to select a plurality of logic held by the holding unit based on the selection information input from the logic update unit included in the reuse processing device according to the first aspect. -Select one logical-physical address translation logic from the physical address translation logic. Therefore, even if the deteriorated blocks are concentrated in a specific area in the collected semiconductor memory, the semiconductor memory re-shipped after the reuse process is updated to the optimum logical-physical address conversion logic. The area is reconstructed so that the number of deteriorated blocks is leveled. Therefore, it is possible to avoid a situation in which the reshipped semiconductor memory immediately fails. In addition, since the logical-physical address conversion logic is updated by the reuse process, it is not necessary to implement the wear leveling function in the semiconductor memory. As a result, it is possible to simplify the system configuration of the semiconductor memory and reduce the product cost.

  A semiconductor memory according to a twelfth aspect of the present invention is characterized in that information relating to a deteriorated block is stored in order to perform a reuse process by the reuse processing apparatus according to the first aspect.

  According to the semiconductor memory of the twelfth aspect, by storing information about the deteriorated block in the semiconductor memory, the acquisition unit of the reuse processing apparatus acquires information about the deteriorated block from the collected semiconductor memory in the reuse process. can do. As a result, it is possible to appropriately execute the optimal logical-physical address conversion logic specifying process by the logic specifying unit and the logical-physical address conversion logic updating process by the logic updating unit.

  According to the present invention, a semiconductor memory reuse processing apparatus capable of simplifying the system configuration of the memory system and reducing the product cost by omitting the implementation of the wear leveling function on the memory system. A semiconductor memory can be obtained.

It is a figure which simplifies and shows the system configuration | structure of a semiconductor memory. It is a figure which shows an example of the memory space of a memory cell array. It is a figure which shows a management information area | region. It is a figure which shows a bad block management table. It is a figure which shows the structure which performs a reuse process with respect to a semiconductor memory. It is a figure which extracts and shows a part of structure of a semiconductor memory. It is a figure which extracts and shows a part of structure of a reuse processing apparatus. It is a flowchart for demonstrating the process which a logic specific | specification part performs. It is a figure which shows area rotation. It is a flowchart for demonstrating selection of a distributed logic. It is a figure which shows a logic. It is a figure which shows a logic. It is a figure which shows a logic. It is a figure which shows a logic. It is a figure which shows a logic. It is a figure which shows an example of selection of a distributed logic. It is a figure which shows an example of selection of a distributed logic.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

  FIG. 1 is a diagram showing a simplified system configuration of the semiconductor memory 1. The semiconductor memory 1 includes a memory controller 2 and a memory cell array 3. The memory controller 2 holds a logical-physical address conversion table for converting a logical address given by an external device such as a host device into a physical address indicating a position in the memory cell array 3. The memory cell array 3 is composed of, for example, a NAND flash memory. However, it may be constituted by another memory such as a NOR flash memory.

  FIG. 2 is a diagram illustrating an example of the memory space of the memory cell array 3. The memory space is divided into a plurality of blocks B (4096 blocks B0 to B4095 in this example). Block B is a data erasing unit. Further, the memory space is divided into a plurality of areas A (32 areas A0 to A31 in this example). Area A is a defective block management unit. In this example, each area A includes 128 blocks B.

  Blocks B0 and B1 in area A0 are defined as management information area R1. The blocks B2 to B127 in the area A0 are defined as a defective block save area R2. Areas A1 to A31 are defined as a user data area R3 accessible by the user.

  FIG. 3 is a diagram showing the management information area R1. A plurality of areas R11 to R14 are defined in the management information area R1. The area R11 stores system information D1 related to the memory system. In the area R12, a bad block management table D2 for managing bad blocks is stored. The region R13 stores a rewrite information management table D3 for managing rewrite information. The region R14 is defined as a spare region.

  FIG. 4 is a diagram showing the bad block management table D2 stored in the region R12. For each of the areas A1 to A31 in the user data area R3, a bad block address list and a save destination address are stored in pairs. In the example of the present embodiment, a maximum of 7 blocks of save destinations can be managed for each area A. Therefore, if eight or more defective blocks occur in a specific area A, the management block cannot manage the save destination of the defective block, and the semiconductor memory 1 is in failure.

  In the example of the present embodiment, the semiconductor memory 1 is used for ROM purposes. When the semiconductor memory 1 is used for a certain product, data used in the product is written into the semiconductor memory 1 and shipped. Thereafter, when the same semiconductor memory 1 is used for another product, the semiconductor memory 1 is collected, rewritten to data used in the other product, and then reshipped. As described above, the semiconductor memory 1 is used in a utilization form in which a semiconductor memory once used is reused. The rewriting of data is performed by a reuse processing apparatus 10 described later. In addition, when the data is rewritten, the reuse processing apparatus 10 rebuilds the area A and updates the logical-physical address conversion table (details will be described later).

  In addition, the semiconductor memory 1 has a refresh function. By satisfying certain conditions based on the bit error rate, the number of times of reading, and the like, the refresh operation is performed in units of blocks without being instructed by an external host device or the like ( That is, rewriting to the same data) is performed. Accordingly, in the semiconductor memory 1, data rewrite processing is generated by the refresh function while being premised on use for ROM. When data is rewritten by the refresh function, the address of the rewritten block and the number of rewrites are stored in the rewrite information management table D3 (or other arbitrary redundant area) shown in FIG. The semiconductor memory 1 can be used for purposes other than ROM use. When data is rewritten by the user, the address of the rewritten block and the number of rewrites (the sum of the number of rewrites by the refresh function) are shown in FIG. Is stored in the rewrite information management table D3.

  FIG. 5 is a diagram showing a configuration for performing a reuse process on the semiconductor memory 1. By connecting the semiconductor memory 1 to the reuse processing device 10, the reuse processing of the semiconductor memory 1 is performed.

  FIG. 6 is a diagram illustrating a part of the configuration of the semiconductor memory 1. The semiconductor memory 1 includes a selection unit 31 and a holding unit 32 inside the memory controller 2 shown in FIG. The holding unit 32 holds a plurality of logical-physical address conversion logics (six logics L0 to L5 in the example of the present embodiment) corresponding to the logical-physical address conversion table.

  FIG. 7 is a diagram illustrating a part of the configuration of the reuse processing apparatus 10. The reuse processing apparatus 10 includes an acquisition unit 21, a logic specification unit 22, a logic update unit 23, a table creation unit 24, a table update unit 25, and a storage unit 26.

  The storage unit 26 stores a plurality of logics L0 to L5 corresponding to a plurality of logics held by the holding unit 32 of the semiconductor memory 1.

  The acquisition unit 21 acquires, from the collected semiconductor memory 1, predetermined management information S1 for identifying a deteriorated block among the plurality of blocks B128 to B4095 in the user data area R3 of the semiconductor memory 1. Degraded blocks include acquired defective blocks caused by normal use of the semiconductor memory 1 and blocks whose number of rewrites exceeds a predetermined threshold. This threshold is set based on the guaranteed number of rewrites and the like, and is set to 100, for example. The management information S1 regarding acquired defective blocks can be acquired from the defective block management table D2 in the semiconductor memory 1. Further, the management information S1 regarding the block whose number of rewrites exceeds the threshold value can be acquired from the rewrite information management table D3 in the semiconductor memory 1.

  In order to reconstruct the area, the logic specifying unit 22 is based on the management information S1 acquired by the acquisition unit 21, and the deterioration block in the area is selected from the plurality of logics L0 to L5 stored in the storage unit 26. A logic whose number is most leveled between the areas A1 to A31 in the user data area R3 (hereinafter referred to as “optimum logic”) is specified. Here, “reconstruction” means changing the correspondence between the area number and the physical address while maintaining the correspondence between the area number and the logical address. Therefore, by reconstructing the area, the correspondence relationship between the logical address and the physical address is changed.

  Information S2 indicating the optimum logic specified by the logic specifying unit 22 is input to the logic updating unit 23 and the table creating unit 24.

  The logic updating unit 23 generates selection information S3 for causing the semiconductor memory 1 to select the optimum logic specified by the logic specifying unit 22 based on the information S2. In addition, the logic updating unit 23 outputs the generated selection information S3 toward the collected semiconductor memory 1, thereby updating the logic currently selected by the semiconductor memory 1 to the optimum logic. Referring to FIG. 6, in semiconductor memory 1, system information D1 is updated based on selection information S3 input from reuse processing apparatus 10. The selection unit 31 refers to the system information D1 updated based on the selection information S3, thereby selecting one optimum logic from among the plurality of logics L0 to L5 held by the holding unit 32.

  Referring to FIG. 7, the table creation unit 24 manages a new defective block management table D2 (that is, a defective block management table reflecting area reconstruction) corresponding to the optimum logic specified by the logic specifying unit 22. Created based on information S1 and information S2. In addition, the table creation unit 24 inputs data S4 related to the created new defective block management table D2 to the table update unit 25.

  The table updating unit 25 outputs the management table update information S5 including the data S4 to the collected semiconductor memory 1 to thereby convert the defective block management table D2 currently held in the semiconductor memory 1 to a new defective block. The management table D2 is updated.

  FIG. 8 is a flowchart for explaining processing executed by the logic specifying unit 22.

  First, in step SP01, the logic specifying unit 22 calculates the number of deteriorated blocks for each of the areas A1 to A31 in the collected semiconductor memory 1. The number of deteriorated blocks is obtained as the sum of the number of acquired defective blocks and the number of blocks whose number of rewrites exceeds a threshold value.

  Next, in step SP02, the logic specifying unit 22 determines whether or not the total (total number) of deteriorated blocks in each of the areas A1 to A31 obtained in step SP01 is equal to or greater than a predetermined threshold value TH1. The threshold value TH1 is set based on the number of prepared save destination blocks. In the example of the present embodiment, since 126 save destination blocks (blocks B2 to B127) are prepared, the threshold value TH1 is set to “100”, which is about 80% thereof.

  If the total number of deteriorated blocks is equal to or greater than the threshold value TH1, then in step SP08, the logic specifying unit 22 determines that the semiconductor memory 1 is a defective product and excludes it from the reuse target.

  If the total number of deteriorated blocks is less than the threshold value TH1, then in step SP03, the logic specifying unit 22 determines whether or not all of the areas A1 to A31 are used in the usage mode after reuse. Information about whether or not the entire area is used after reuse is input to the reuse processing apparatus 10 in advance. If there is an area (unused area) that is not used after reuse, information about the unused area is also input to the reuse processing apparatus 10 in advance.

  If the entire area is used after reuse, the area is reconstructed by selecting a distributed logic in step SP07. The selection of the distributed logic will be described later.

  If there is an unused area that is not used after reuse, then in step SP04, the logic specifying unit 22 specifies the minimum value from the number of deteriorated blocks in each area A1 to A31 obtained in step SP01, and the minimum The number of areas whose difference from the value is equal to or greater than a predetermined threshold value TH2 is counted. The threshold value TH2 is set based on the number of deteriorated blocks allowed in one area. In the example of the present embodiment, since the number of allowable deteriorated blocks in one area is “7”, the threshold value TH2 is set to “4”, for example. When the minimum value of the number of deteriorated blocks in each of the areas A1 to A31 is “1”, for example, the logic specifying unit 22 counts the number of areas in which the number of deteriorated blocks is “5” or more.

  Next, in step SP05, the logic specifying unit 22 determines whether or not the count value counted in step SP04 is “1”.

  If the count value is not “1”, then in step SP07, the distributed logic is selected and the area is reconstructed (details will be described later).

  If the count value is “1”, then area rotation is performed in step SP06. In this case, the logic specifying unit 22 sets an area where degraded blocks are frequently generated in the semiconductor memory 1 at the time of collection (that is, an area where the number of degraded blocks is “5” or more in the above example) as an unused area after reuse. Rebuild the area to allocate. Even when there are a plurality of areas where degraded blocks are present, if there are more unused areas after reuse, the same area rotation may be performed for the plurality of frequent areas.

  FIG. 9 is a diagram illustrating area rotation. For simplicity of explanation, only four areas A1 to A4 each including five blocks are shown. The left side is the memory space at the time of collection (before reuse) (that is, the memory space corresponding to the logic L0 used before reuse), and the right side is the memory space at the time of reshipment (after reuse) (that is, the logic to be used after reuse) Memory space corresponding to L6). In both logics L0 and L6, area A1 corresponds to logical addresses P0 to P5, area A2 corresponds to logical addresses P6 to P11, and area A3 corresponds to logical addresses P12 to P17. Area A4 corresponds to logical addresses P18 to P23.

  In the memory space before reuse (logic L0), area A1 corresponds to physical addresses Q0 to Q5, area A2 corresponds to physical addresses Q6 to Q11, and area A3 corresponds to physical addresses Q12 to Q17. The area A4 corresponds to the physical addresses Q18 to Q23.

  Here, it is assumed that deteriorated blocks frequently occur in the area A3 in the semiconductor memory 1 before reuse. Further, in the semiconductor memory 1 after reuse, it is assumed that the area A4 is an unused area. In this case, the area rotation is performed so that the physical addresses Q12 to Q17 corresponding to the deterioration frequent occurrence area A3 before reuse correspond to the unused area A4 after reuse.

  As a result of area rotation, in the memory space after reuse (logic L6), area A1 corresponds to physical addresses Q18 to Q23, area A2 corresponds to physical addresses Q0 to Q5, and area A3 corresponds to physical addresses. Q6 to Q11 correspond, and area A4 corresponds to physical addresses Q12 to Q17.

  FIG. 10 is a flowchart for explaining the selection of the distributed logic shown in step SP07 of FIG. In the example of the present embodiment, six patterns of logic L0 to L5 are prepared in advance as distributed logic.

  11 to 15 are diagrams showing the logics L1 to L5, respectively. In these drawings, as in FIG. 9, only four areas A1 to A4 each including five blocks are shown. The left side is a memory space before reuse, and the right side is a memory space after reuse.

  Referring to FIG. 11, in logic L1, areas are reconstructed by assigning physical addresses Q0 to Q23 before reuse (logic L0) one by one in order from the beginning of each area after reuse. For example, the first physical address Q0 before reuse is assigned to the first in the area A1 after reuse, and the second physical address Q1 before reuse is assigned to the first in the area A2 after reuse.

  As a result of area reconstruction using the logic L1, in the memory space after reuse, the area A1 corresponds to the physical addresses Q0, Q4, Q8, Q12, Q16, and Q20, and the area A2 corresponds to the physical addresses Q1, Q5, and so on. Q9, Q13, Q17, Q21 correspond to area A3 corresponds to physical addresses Q2, Q6, Q10, Q14, Q18, Q22, and area A4 corresponds to physical addresses Q3, Q7, Q11, Q15, Q19, Corresponds to Q23.

  Referring to FIG. 12, in logic L2, areas are reconstructed by assigning two physical addresses Q0 to Q23 before reuse (logic L0) in order from the top of each area after reuse. For example, the first and second physical addresses Q0 and Q1 before reuse are assigned to the first and second of the area A1 after reuse, and the third and fourth physical addresses Q2 and Q3 before reuse are reused. It is assigned to the first and second of the subsequent area A2.

  As a result of area reconstruction using the logic L1, in the memory space after reuse, the area A1 corresponds to the physical addresses Q0, Q1, Q8, Q9, Q16, and Q17, and the area A2 corresponds to the physical addresses Q2, Q3, and Q3. Q10, Q11, Q18, Q19, area A3 corresponds to physical addresses Q4, Q5, Q12, Q13, Q20, Q21, and area A4 corresponds to physical addresses Q6, Q7, Q14, Q15, Q22, Corresponds to Q23.

  Referring to FIG. 13, in logic L3, areas are reconstructed by allocating one by one to the memory space after reuse one by one in order from the beginning of each area before reuse (logic L0). For example, the first physical address Q0 of the area A1 before reuse is assigned to the first of the area A1 after reuse, and the first physical address Q6 of the area A2 before reuse is the second of the area A1 after reuse. Assigned to.

  As a result of area reconstruction using the logic L3, in the memory space after reuse, the area A1 corresponds to the physical addresses Q0, Q6, Q12, Q18, Q1, Q7, and the area A2 corresponds to the physical addresses Q13, Q19, Q2, Q8, Q14, Q20, area A3 corresponds to physical addresses Q3, Q9, Q15, Q21, Q4, Q10, and area A4 corresponds to physical addresses Q16, Q22, Q5, Q11, Q17, Corresponds to Q23.

  Referring to FIG. 14, in logic L4, areas are reconstructed by assigning two in order from the beginning of each area before reuse (logic L0) to the memory space after reuse. For example, the first and second physical addresses Q0 and Q1 of the area A1 before reuse are allocated to the first and second of the area A1 after reuse, and the first and second physical addresses of the area A2 before reuse. Q6 and Q7 are assigned to the third and fourth of the area A1 after reuse.

  As a result of the area reconstruction using the logic L4, in the memory space after reuse, the area A1 corresponds to the physical addresses Q0, Q1, Q6, Q7, Q12, Q13, and the area A2 has the physical addresses Q18, Q19, Q2, Q3, Q8, Q9, area A3 corresponds to physical addresses Q14, Q15, Q20, Q21, Q4, Q5, and area A4 corresponds to physical addresses Q10, Q11, Q16, Q17, Q22, Corresponds to Q23.

  Referring to FIG. 15, in logic L5, an even address before reuse (logic L0) is assigned to the first half of the memory space after reuse, and an odd address before reuse is assigned to the second half of the memory space after reuse. The area is rebuilt.

  As a result of area reconstruction using the logic L5, in the memory space after reuse, the area A1 corresponds to the physical addresses Q0, Q2, Q4, Q6, Q8, Q10, and the area A2 corresponds to the physical addresses Q12, Q14, Q16, Q18, Q20, Q22, area A3 corresponds to physical addresses Q1, Q3, Q5, Q7, Q9, Q11, and area A4 corresponds to physical addresses Q13, Q15, Q17, Q19, Q21, Corresponds to Q23.

  The distributed logic illustrated in FIGS. 11 to 15 is an example, and the logic can be applied by preparing any other logic. Further, the types of logic to be prepared are not limited to six patterns, and any plural patterns of logic may be prepared.

  Referring to FIG. 10, first, in step SP071, the logic specifying unit 22 tries to reconstruct areas by applying logics L0 to L5. And about each logic L0-L5, the number of deterioration blocks in each area A1-A31 after reconstruction is calculated. Further, the maximum value X, the minimum value Y, and the difference Z between the maximum value X and the minimum value Y are calculated for each of the logics L0 to L5.

  Next, in step SP072, the logic specifying unit 22 determines whether or not the maximum value X is greater than or equal to a predetermined threshold TH3 in all of the logics L0 to L5. The threshold value TH3 is set based on the number of deteriorated blocks allowed in one area. In the example of the present embodiment, since the number of allowable deteriorated blocks in one area is “7”, the threshold value TH3 is set to “5”, for example.

  If the maximum value X of all the logics L0 to L5 is equal to or greater than the threshold value TH3, then in step SP073, the logic specifying unit 22 determines that the semiconductor memory 1 is defective and excludes it from the reuse target.

  If the maximum value X is less than the threshold value TH3 in at least one of the logics L0 to L5, then in step SP074, the logic specifying unit 22 selects the logic having the smallest maximum value X among the logics L0 to L5 (best logic). ).

  If there is only one best logic, then in step SP075, the logic specifying unit 22 selects the one best logic and adopts an area reconstructed using the best logic.

  If there are a plurality of best logics, then in step SP076, the logic specifying unit 22 specifies the best logic having the smallest difference Z among the plurality of best logics.

  If there is only one best logic having the smallest difference Z, then in step SP075, the logic specifying unit 22 selects the one best logic and adopts the area reconstructed using the best logic. To do.

  If there are a plurality of best logics having the smallest difference Z, then in step SP077, the logic specifying unit 22 selects any one of the best logics from the plurality of best logics having the smallest difference Z. For example, the best logic with the smallest number assigned to the logics L0 to L5 is selected. Then, the area reconstructed using the best logic is adopted.

  FIG. 16 is a diagram illustrating an example of selection of distributed logic in the example of the simple memory space illustrated in FIGS. Here, a total of 8 blocks of physical addresses Q1, Q2, Q3, Q5, Q6, Q14, Q17, and Q21 are defective blocks, and a total of 4 blocks of physical addresses Q9, Q10, Q11, and Q12 exceed the threshold. It is assumed that the block is a block (a block in which the number of rewrites exceeds 100 in the above example).

  In this case, the number of deteriorated blocks in the semiconductor memory 1 before reuse (logic L0) is “4” in area A1, “4” in area A2, and “3” in area A3, as shown in FIG. In area A4, “1” is set.

  Further, as shown in FIG. 16B, the number of deteriorated blocks when the logic L1 is applied is “1” in the area A1, “5” in the area A2, “4” in the area A3, and “4” in the area A4. The maximum value X is “5”, the minimum value Y is “1”, and the difference Z is “4”. Similarly, the number of deteriorated blocks when the logic L2 is applied is “3” in the area A1, “4” in the area A2, “3” in the area A3, “2” in the area A4, and the maximum value X is “4”. ”, The minimum value Y is“ 2 ”, and the difference Z is“ 2 ”. Similarly, the number of deteriorated blocks when the logic L3 is applied is “3” in the area A1, “2” in the area A2, “4” in the area A3, “3” in the area A4, and the maximum value X is “4”. ”, The minimum value Y is“ 2 ”, and the difference Z is“ 2 ”. Similarly, the number of deteriorated blocks when the logic L4 is applied is “3” in the area A1, “3” in the area A2, “3” in the area A3, “3” in the area A4, and the maximum value X is “3”. ”, The minimum value Y is“ 3 ”, and the difference Z is“ 0 ”. Similarly, the number of deteriorated blocks when the logic L5 is applied is “5” in the area A1, “2” in the area A2, “3” in the area A3, “2” in the area A4, and the maximum value X is “5”. ”, The minimum value Y is“ 2 ”, and the difference Z is“ 3 ”. Accordingly, in this example, the logic L4 having the smallest maximum value X of “3” is selected.

  In the above description, the total number of acquired defective blocks and the number of blocks in which the number of rewrites exceeds a predetermined threshold is used as the number of deteriorated blocks, but only one of them can be used.

  FIG. 17 is a diagram illustrating an example in which distributed logic is selected using only the number of defective blocks, corresponding to FIG.

  In this case, the number of defective blocks in the semiconductor memory 1 before reuse (logic L0) is “4” in area A1, “1” in area A2, and “2” in area A3, as shown in FIG. In area A4, “1” is set.

  As shown in FIG. 17B, when the logic L1 is applied, the number of defective blocks is “0” in area A1, “4” in area A2, “3” in area A3, and “3” in area A4. The maximum value X is “4”, the minimum value Y is “0”, and the difference Z is “4”. Similarly, the number of defective blocks when the logic L2 is applied is “2” in the area A1, “2” in the area A2, “2” in the area A3, “2” in the area A4, and the maximum value X is “2”. ”, The minimum value Y is“ 2 ”, and the difference Z is“ 0 ”. Similarly, the number of defective blocks when the logic L3 is applied is “2” in the area A1, “2” in the area A2, “2” in the area A3, “2” in the area A4, and the maximum value X is “2”. ”, The minimum value Y is“ 2 ”, and the difference Z is“ 0 ”. Similarly, the number of defective blocks when the logic L4 is applied is “2” in the area A1, “2” in the area A2, “3” in the area A3, “1” in the area A4, and the maximum value X is “3”. ”, The minimum value Y is“ 1 ”, and the difference Z is“ 2 ”. Similarly, the number of defective blocks when the logic L5 is applied is “3” in the area A1, “2” in the area A2, “2” in the area A3, “1” in the area A4, and the maximum value X is “3”. ”, The minimum value Y is“ 1 ”, and the difference Z is“ 2 ”. Accordingly, in this example, the logic L2 having the smallest number assigned to the logic is selected from the logics L2 and L3 having the smallest maximum value X of “2”.

  As described above, according to the reuse processing apparatus 10 according to the present embodiment, the acquisition unit 21 acquires the management information S1 for specifying the deteriorated block from the collected semiconductor memory 1. Moreover, the logic specific | specification part 22 is based on management information S1 which the acquisition part 21 acquired, among the several logics L0-L5 which the memory | storage part 26 has memorize | stored, the deterioration block number in an area is area A1-A31. Identify the optimal logic that is most leveled between. Then, the logic updating unit 23 outputs selection information S3 for selecting the optimum logic specified by the logic specifying unit 22 to the collected semiconductor memory 1 to thereby select the logic selected by the semiconductor memory 1 Is updated to the optimal logic. Accordingly, even if the deteriorated blocks are concentrated in a specific area in the collected semiconductor memory 1, the number of deteriorated blocks is updated in the semiconductor memory 1 re-shipped after the reuse process by updating to the optimum logic. The area has been restructured so that is leveled. Therefore, it is possible to avoid a situation in which the re-shipped semiconductor memory 1 immediately fails. In addition, since the logic is updated by the reuse process, it is not necessary to mount the wear leveling function in the semiconductor memory 1. As a result, the system configuration of the semiconductor memory 1 can be simplified and the product cost can be reduced.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the table creation unit 24 creates a new defective block management table D2 corresponding to the optimum logic identified by the logic identification unit 22. Then, the table update unit 25 outputs the new bad block management table D2 created by the table creation unit 24 to the collected semiconductor memory 1, thereby the bad block management table held by the semiconductor memory 1 D2 is updated to a new bad block management table D2. Therefore, in the semiconductor memory 1 that is reshipped after the reuse process, it is possible to appropriately manage the defective blocks based on the updated new defective block management table D2.

  Moreover, according to the reuse processing apparatus 10 which concerns on this Embodiment, an acquired defect block is contained in a deterioration block. Therefore, in the re-shipped semiconductor memory 1, since the number of deteriorated blocks including the acquired defective blocks is leveled between areas, a failure caused by concentration of deteriorated blocks in a specific area is not generated. It can be avoided.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the deteriorated block is a block in which the number of rewrites exceeds a predetermined value, that is, a block that is likely to become an acquired defective block due to frequent rewrites (quasi-defective block). Is included. Therefore, in the re-shipped semiconductor memory 1, the number of deteriorated blocks including the quasi-defective blocks is leveled between the areas, so that the occurrence of a failure due to the concentration of the deteriorated blocks in a specific area is avoided. It becomes possible to do.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the logic specifying unit 22 determines that the semiconductor memory 1 in which the total number of deteriorated blocks is equal to or greater than the predetermined threshold value TH1 is defective. Accordingly, the semiconductor memory 1 having the total number of deteriorated blocks equal to or greater than the threshold value TH1 is disposed as a defective product and is not reshipped, so that it is possible to avoid in advance a situation in which the reshipped semiconductor memory 1 immediately fails. .

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the logic specifying unit 22 is configured such that when there is an unused area that is not used in the semiconductor memory 1 after reshipment, the semiconductor memory 1 at the time of collection is stored. The logic in which an area where degraded blocks frequently occur is assigned to the unused area is specified as the optimum logic. By assigning an area in which degraded blocks occur frequently to an unused area, the number of degraded blocks in other areas (that is, used areas) is reduced, so that the reliability of the re-shipped semiconductor memory 1 is improved. Is possible.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the logic specifying unit 22 specifies the best logic having the smallest maximum value X of the number of deteriorated blocks in the area as the optimum logic. By selecting the best logic having the smallest maximum value X of the number of deteriorated blocks, the number of deteriorated blocks in the area is effectively leveled, so that the reliability of the re-shipped semiconductor memory 1 can be improved. It becomes.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, when there are a plurality of best logics, the logic specifying unit 22 among the plurality of best logics, the maximum value X of the number of deteriorated blocks in the area. The logic having the smallest difference Z between the minimum value Y and the minimum value Y is specified as the optimum logic. By selecting the logic having the smallest difference Z between the maximum value X and the minimum value Y of the number of deteriorated blocks, the number of deteriorated blocks in the area is leveled to the maximum, so that the reliability of the re-shipped semiconductor memory 1 is improved. It becomes possible to improve the property.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, when there are a plurality of logics having the smallest difference Z between the maximum value X and the minimum value Y, the logic specifying unit 22 Arbitrary logic is specified as the optimum logic. This makes it possible to appropriately select one logic used for area reconstruction.

  Further, according to the reuse processing apparatus 10 according to the present embodiment, the logic specifying unit 22 determines that the maximum value X of the number of deteriorated blocks in the area is equal to or greater than a predetermined threshold value TH3 for all logics. The semiconductor memory 1 is determined as a defective product. Accordingly, the semiconductor memory 1 that cannot be expected to equalize the number of deteriorated blocks no matter which logic is applied is disposed of as a defective product and is not reshipped. It can be avoided.

  Further, according to the semiconductor memory 1 according to the present embodiment, the selection unit 31 includes a plurality of holding units 32 held based on the selection information S3 input from the logic update unit 23 included in the reuse processing apparatus 10. One optimal logic is selected from the logics L0 to L5. Accordingly, even if the deteriorated blocks are concentrated in a specific area in the collected semiconductor memory 1, the number of deteriorated blocks is updated in the semiconductor memory 1 re-shipped after the reuse process by updating to the optimum logic. The area has been restructured so that is leveled. Therefore, it is possible to avoid a situation in which the re-shipped semiconductor memory 1 immediately fails. In addition, since the logic is updated by the reuse process, it is not necessary to mount the wear leveling function in the semiconductor memory 1. As a result, the system configuration of the semiconductor memory 1 can be simplified and the product cost can be reduced.

  Further, according to the semiconductor memory 1 according to the present embodiment, the acquisition unit 21 of the reuse processing apparatus 10 stores the collected semiconductor in the reuse processing by storing the management information S1 regarding the deteriorated block in the semiconductor memory 1. The management information S1 regarding the deteriorated block can be acquired from the memory 1. As a result, it is possible to appropriately execute the optimal logical-physical address conversion logic specifying process by the logic specifying unit 22 and the logical-physical address conversion logic updating process by the logic updating unit 23.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory 2 Memory controller 3 Memory cell array 10 Reuse processing apparatus 21 Acquisition part 22 Logic specific part 23 Logic update part 24 Table creation part 25 Table update part 26 Memory | storage part 31 Selection part 32 Holding part

Claims (12)

Targeting a semiconductor memory that manages defective blocks in units of areas including a plurality of blocks that are data erasure units, the semiconductor memory used for collecting and reusing the semiconductor memory is predetermined before reshipment. A semiconductor memory reuse processing device that performs the reuse processing of
A storage unit for storing a plurality of logical-physical address conversion logics corresponding to the plurality of logical-physical address conversion logics held by the semiconductor memory;
An acquisition unit for acquiring predetermined management information for identifying a deteriorated block among a plurality of blocks included in the semiconductor memory from the collected semiconductor memory;
Based on the management information acquired by the acquisition unit, among the plurality of logical-physical address conversion logic stored in the storage unit, the number of deteriorated blocks in the area is most optimally leveled between the areas. A logic specifying unit for specifying a logical-physical address conversion logic;
By outputting selection information for selecting the optimum logical-physical address conversion logic specified by the logic specifying unit to the collected semiconductor memory, logical-physical address conversion selected by the semiconductor memory A logic update unit that updates the logic to the optimum logical-physical address conversion logic;
A semiconductor memory reuse processing apparatus. A table creation unit for creating a new bad block management table corresponding to the optimum logical-physical address conversion logic identified by the logic identification unit;
By outputting the new bad block management table created by the table creation unit to the collected semiconductor memory, the bad block management table held by the semiconductor memory is changed to the new bad block management table. A table update unit to be updated;
The semiconductor memory reuse processing apparatus according to claim 1, further comprising:   The reuse processing apparatus for a semiconductor memory according to claim 1, wherein the deteriorated block includes an acquired defective block.   The reuse processing apparatus for a semiconductor memory according to claim 1, wherein the deteriorated block includes a block whose number of rewrites exceeds a predetermined value.   5. The semiconductor memory reuse processing apparatus according to claim 1, wherein the logic specifying unit determines that a semiconductor memory having a total number of deteriorated blocks equal to or greater than a predetermined value is a defective product.   When there is an unused area that is not used in the semiconductor memory after reshipment, the logic specifying unit assigns an area in which deteriorated blocks frequently occur in the semiconductor memory at the time of collection to the unused area. The semiconductor memory reuse processing apparatus according to claim 1, wherein a physical address conversion logic is specified as the optimum logical-physical address conversion logic.   The semiconductor memory according to claim 1, wherein the logic specifying unit specifies the best logic having the smallest number of deteriorated blocks in the area as the optimum logical-physical address conversion logic. Reuse processing equipment.   When there are a plurality of best logics, the logic specifying unit selects a logic having the smallest difference between the maximum value and the minimum value of the number of deteriorated blocks in the area among the plurality of best logics. The semiconductor memory reuse processing apparatus according to claim 7, which is specified as a physical address translation logic.   When there are a plurality of logics having the smallest difference between the maximum value and the minimum value, the logic specifying unit specifies any logic among the plurality of logics as the optimum logic-physical address conversion logic. The semiconductor memory reuse processing apparatus according to claim 8.   The logic specifying unit determines that the semiconductor memory is defective if the maximum value of the number of deteriorated blocks in the area is equal to or greater than a predetermined value for all logics. A semiconductor memory reuse processing apparatus according to claim 1. A holding unit for holding a plurality of logical-physical address conversion logic;
A selection unit that selects one logical-physical address translation logic from the plurality of logical-physical address translation logics held by the holding unit;
With
The selection unit is based on selection information input from a logic update unit included in the reuse processing device according to claim 1, and is selected from the plurality of logical-physical address conversion logics held by the holding unit, A semiconductor memory that selects one logical-physical address translation logic.   A semiconductor memory for storing information relating to a deteriorated block in order to perform a reuse process by the reuse processing apparatus according to claim 1.

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