JP2013183409A - Skew adjustment circuit, method of designing skew adjustment circuit, and program for designing skew adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the design of a circuit for adjusting a skew between two signals.SOLUTION: A skew adjustment circuit 1 has first and second circuits 2, 3 whose delay characteristics are relatively comparable. An additional block 32 (23) that is one of a plurality of functional blocks 21, 22, 23 constituting the first circuit 2 which is substantially unnecessary for the second circuit 3 is inserted in the second circuit 3, so that the first circuit 2 and the second circuit 3 comprise the same types of functional blocks. The second circuit 3 further has means 35 for prohibiting a substantial logical operation of the additional block 32.

Description

  The present invention relates to a circuit for adjusting a skew between two signals and a design method thereof.

  Patent Document 1 discloses a conventional clock skew adjustment circuit and a design method thereof. In this document, a delay circuit (110, 112) is configured by interconnecting a plurality of drive circuits under a power supply trunk line (114), and a clock signal is sent to the macro cell (104, 105) via this delay circuit. A configuration for supplying the power is disclosed. This eliminates the need for an extra area for the delay circuit, and delays clock signal lines that do not straddle the hierarchy, so that delay calculation and layout verification are facilitated. In addition, by adjusting the size, number of stages, number of fanouts, wiring length, wiring width of interconnected drive circuits, or by making the configuration of the clock tree in the logic circuit block approximately the same, the wiring delay of the clock signal line, gate The delay ratio is unlikely to change, and the clock skew between the logic circuit block and the macro cell can be reduced.

Japanese Unexamined Patent Publication No. 2000-236025 (see paragraphs 0036 and 0037, FIG. 1, etc.)

  The amount of delay in the circuit varies depending on process variations, voltage conditions, temperature, and the like. Further, the amount of variation differs depending on the type of functional block such as a flip-flop circuit in the path (type of semiconductor elements constituting the function block, combination, etc.).

  FIG. 4 illustrates a circuit 101 for adjusting the skew between two signals. The circuit 101 supplies a clock signal output from the oscillation source 102 and transfer data from the output source 103 that outputs predetermined transfer data to an external circuit via the clock output terminal 104 and the data output terminal 105. In this case, the skew between the clock signal and the transfer data is adjusted. The clock signal and the transfer data are input to the flip-flop circuit 106, and the transfer data is output from the data output terminal 105 in synchronization with the clock signal. The clock signal is output from the clock output terminal 104 via the delay circuit 107. The delay circuit 107 absorbs delay generated in the transmission path of transfer data, and is often configured by connecting buffers and inverters in multiple stages or using a DLL (Delay Locked Loop) circuit. The delay circuit 107 according to this example is designed so that the same delay as that caused mainly by the operation of the flip-flop circuit 106 occurs.

  In the circuit 101 shown in FIG. 4, the delay by the flip-flop circuit 106 is absorbed by the delay circuit 107. However, as described above, since the delay amount by the flip-flop circuit 106 varies, the design of the delay circuit 107 is difficult. That is, the difficulty in circuit design is due to the fact that the functional blocks provided in each of the two-signal transmission paths are different and the delay characteristics are different for each functional block.

  The first aspect of the present invention includes first and second circuits whose delay characteristics are relatively compared, and among the plurality of functional blocks constituting the first circuit, the second circuit includes The skew adjustment circuit is configured such that the first circuit and the second circuit are configured by the same type of functional blocks by inserting a substantially unnecessary additional block into the second circuit.

  A second aspect of the present invention is a method for designing a skew adjustment circuit having first and second circuits whose delay characteristics are relatively compared, and includes a plurality of functional blocks constituting the first circuit. Of these, the first circuit and the second circuit are configured by the same type of functional block by inserting an additional block which is substantially unnecessary for the second circuit into the second circuit. .

  A third aspect of the present invention is a program for designing a skew adjustment circuit for causing a computer to implement the method according to the second aspect.

  According to the said aspect, the 1st and 2nd circuit (each transmission path of 2 signals) is comprised by the same kind of functional block. As a result, the delay characteristic (variation in delay amount) peculiar to the functional block is common between the first and second circuits, so that the skew between the two circuits is reduced and the circuit design for eliminating the skew is easy. It becomes.

  According to the present invention, it is easy to design a circuit that adjusts a skew between two signals.

It is a figure which shows the structure of the skew adjustment circuit which concerns on Embodiment 1 of this invention. 6 is a timing chart showing the operation of the clock output circuit according to the first and second embodiments. It is a figure which shows the structure of the skew adjustment circuit which concerns on Embodiment 2 of this invention. It is a figure which illustrates the circuit for adjusting the skew between two signals.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a skew adjustment circuit 1 according to Embodiment 1 of the present invention. The skew adjustment circuit 1 adjusts the skew between the clock CLK output from the clock signal oscillation source 11 and the transfer data from the output source 12 that outputs predetermined transfer data. The skew adjustment circuit 1 includes a clock output circuit 2 and a data output circuit 3. The clock output circuit 2 is connected between the oscillation source 11 and a clock output terminal 15 connected to an external circuit. The data output circuit 3 is connected between the output source 12 and a data output terminal 16 connected to an external circuit. The clock output circuit 2 and the data output circuit 3 have a relationship in which their delay characteristics are relatively compared when adjusting the skew.

  The clock output circuit 2 includes a first flip-flop circuit 21, a second flip-flop circuit 22, and an EXOR circuit 23.

  The first flip-flop circuit 21 receives the clock CLK from the oscillation source 11 and its inverted output Q1B, operates in synchronization with the positive edge of the clock CLK, and is based on the reset signal output from the signal output unit 25. Has a reset function. The output Q 1 of the first flip-flop circuit 21 is input to one input terminal 26 of the EXOR circuit 23.

  The second flip-flop circuit 22 receives the clock CLK from the oscillation source 11 and its inverted output Q2B, operates in synchronization with the positive edge of the clock CLK, and is based on the reset signal output from the signal output unit 25. Has a reset function. The output Q2 of the second flip-flop circuit 22 is input to the other input terminal 27 of the EXOR circuit 23.

  As described above, the EXOR circuit 23 inputs the output Q1 of the first flip-flop 21 to one input terminal 26, and inputs the output Q2 of the second flip-flop 22 to the other input terminal 27. The output terminal of the EXOR circuit 23 is connected to a clock output terminal 15 connected to an external circuit. The clock CLK_OUT whose phase is adjusted by the clock output circuit 2 is output from the clock output terminal 15 to an external circuit.

  FIG. 2 shows the operation of the clock output circuit 2 configured as described above. When the clock CLK from the oscillation source 11 is input at the [L] level, the output Q1 of the first flip-flop 21 is [L], its inverted output Q1B is [H], and the output of the second flip-flop 22 is output. Q2 is [L] and its inverted output Q2B is [H]. Therefore, the output CLK_OUT of the EXOR circuit 23 is [L].

  Thereafter, when the clock CLK becomes [H], the output Q1 is inverted to [H], the inverted output Q1B is inverted to [L], the output Q2 is maintained at [L], and the inverted output Q2B is maintained at [H]. As a result, the output CLK_OUT becomes [H].

  Thereafter, when the clock CLK becomes [L] again, the output Q1 is maintained at [H], the inverted output Q1B is maintained at [L], the output Q2 is inverted to [H], and the inverted output Q2B is inverted to [L]. As a result, the output CLK_OUT becomes [L].

  Thereafter, when the clock CLK becomes [H] again, the output Q1 is inverted to [L], the inverted output Q1B is inverted to [H], the output Q2 is maintained at [H], and the inverted output Q2B is maintained at [L]. As a result, the output CLK_OUT becomes [H]. Thereafter, the above operation is repeated.

  The data output circuit 3 includes a flip-flop circuit 31 and an EXOR circuit 32.

  The flip-flop circuit 31 receives the transfer data from the output source 12 and the clock CLK from the oscillation source 11, and outputs the transfer data in synchronization with the positive edge of the clock CLK.

  The EXOR circuit 32 receives the output (transfer data) of the flip-flop circuit 31 from one input terminal 34, and the other input terminal 35 is grounded (fixed to negative logic). As a result, the logical operation of the EXOR circuit 32 is substantially prohibited, and its output becomes the same value as the output of the flip-flop circuit 31. The output terminal of the EXOR circuit 32 is connected to the data output terminal 16 connected to an external circuit.

  As described above, the clock output circuit 2 includes the first flip-flop circuit 21, the second flip-flop circuit 22, and the EXOR circuit 23, and the data output circuit 3 includes the flip-flop circuit 31 and the EXOR circuit 32. Composed. As described above, in the skew adjustment circuit 1 according to the present embodiment, the clock output circuit 2 and the data output circuit 3 are the same type of functional blocks, that is, the flip-flop circuits 21, 22, 31 and the EXOR circuits 23, 32. It is comprised using.

  The EXOR circuit 32 of the data output circuit 3 is unnecessary for the original logical operation required for the data output circuit 3. However, the presence of the EXOR circuit 32 makes the types of functional blocks constituting the clock output circuit 2 and the data output circuit 3 the same, so that the relative relationship between the two circuits 2 and 3 compared to the case where different functional blocks are included Thus, the difference in delay characteristics becomes small, and the estimation of the difference becomes easy.

  Further, in order to maintain the original logical operation of the data output circuit 3, a means for inhibiting the substantial operation of the EXOR circuit 32 is required. In this embodiment, as this means, the other input terminal 35 of the EXOR circuit 32 is grounded. For the same purpose, when an EXNOR circuit is used, one input terminal thereof may be connected to VDD or the like and fixed to positive logic.

  As described above, in the two circuits 2 and 3 whose delay characteristics are relatively compared, even if the functional block 32 is originally unnecessary in one circuit 3, the functional block 32 is used in the other circuit 2. If so, the functional block 32 is inserted into one of the circuits 3, and means (35 ground) for maintaining the original logical operation of the one circuit 3 is provided, thereby achieving uniform delay characteristics. Or it is possible to facilitate the design for uniformity.

  In order to make the delay characteristics of both circuits 2 and 3 more uniform, it is preferable to match the electrical characteristics (electric capacity) of the wiring between the functional blocks. Specifically, the wiring from the oscillation source 11 to each flip-flop circuit 21, 22, 31, the wiring from each flip-flop circuit 21, 22, 31 to each EXOR circuit 23, 32, each EXOR circuit 23, 32 from each For example, wiring to the output terminals 15 and 16.

Embodiment 2
FIG. 3 shows a configuration of the skew adjustment circuit 51 according to the second embodiment of the present invention. The difference between the skew adjustment circuit 52 and the skew adjustment circuit 1 is in the configuration of the clock output circuit 52. The clock output circuit 52 includes a first flip-flop circuit 61, a second flip-flop circuit 62, and an EXOR circuit 63.

  The first flip-flop circuit 61 receives the clock CLK from the oscillation source 11 and the output signal of the second flip-flop circuit 62, and operates in synchronization with the positive edge of the clock CLK.

  The second flip-flop circuit 62 receives the clock CLK from the oscillation source 11 and a signal obtained by inverting the output signal of the first flip-flop circuit 61, and operates in synchronization with the negative edge of the clock CLK.

  In the EXOR circuit 63, the output signal of the first flip-flop 61 is input to one input terminal 66, the signal obtained by inverting the output signal of the second flip-flop is input to the other input terminal 67, and the output terminal is Connected to clock output terminal 16 connected to an external circuit.

  With the clock output circuit 51 having the above-described configuration, the operation shown in FIG. 2 can be realized in the same manner as the clock output circuit 2 according to the first embodiment. The clock output circuit 62 according to the second embodiment can be configured using a flip-flop circuit that does not have a reset function. As a result, a mechanism for generating a reset signal is not required, and in addition to the effects of the first embodiment, it is possible to reduce costs and downsize the apparatus.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the circuit for adjusting the skew between the clock signal and the transfer data has been described. However, the present invention is not limited to this, and between signals of different combinations. The present invention can also be applied to circuits used for skew adjustment.

  In the above embodiment, the combination of the flip-flop circuit and the EXOR circuit is shown. However, the present invention is not limited to this, and any functional block that is appropriately designed according to the intended logic operation. It is applicable to the combination of

1,51 Skew adjustment circuit 2,52 Clock output circuit (first circuit)
3 Data output circuit (second circuit)
DESCRIPTION OF SYMBOLS 11 Oscillation source 12 Output source 15 Clock signal output terminal 16 Data output terminal 21, 61 1st flip-flop circuit 22, 62 2nd flip-flop circuit 23, 32, 63 EXOR circuit

Claims (10)

Having first and second circuits whose delay characteristics are relatively compared;
Of the plurality of functional blocks constituting the first circuit, an additional block substantially unnecessary for the second circuit is inserted into the second circuit, whereby the first circuit and the second circuit are inserted. The circuit is composed of the same type of functional blocks.
Skew adjustment circuit. The second circuit includes means for inhibiting a substantial logical operation of the additional block.
The skew adjustment circuit according to claim 1. The first circuit is connected between an oscillation source of a clock signal and an external circuit, adjusts the phase of the clock signal from the oscillation source, and outputs the adjusted clock signal to the external circuit;
The second circuit is connected between an output source that outputs transfer data and the external circuit, and outputs the transfer data to the external circuit in synchronization with a clock signal from the oscillation source.
The skew adjustment circuit according to claim 1 or 2. The first circuit includes a flip-flop circuit and either an EXOR circuit or an EXNOR circuit,
The additional block is either the EXOR circuit or the EXNOR circuit.
The skew adjustment circuit according to claim 3. The first circuit includes:
A first flip-flop circuit that inputs a clock signal from the oscillation source and a signal obtained by inverting the output signal of the oscillation source, operates in synchronization with a positive edge of the clock signal, and has a reset function or a set function;
A second flip-flop circuit that inputs a clock signal from the oscillation source and a signal obtained by inverting the output signal of the oscillation source, operates in synchronization with the negative edge of the clock signal, and has a reset function or a set function;
An EXOR circuit in which the output signal of the first flip-flop circuit is input to one input terminal, the output signal of the second flip-flop circuit is input to the other input terminal, and the output terminal is connected to the external circuit Or an EXNOR circuit;
Consisting of
The second circuit includes:
A third flip-flop circuit that inputs a clock signal from the oscillation source and transfer data from the output source, and outputs the transfer data in synchronization with a positive edge of the clock signal;
An EXOR circuit in which the output signal of the third flip-flop circuit is input to one input terminal, the other input terminal is fixed to negative logic, and the output terminal is connected to the external terminal, or the first input terminal is connected to the first input terminal. An EXNOR circuit to which the output signal of the flip-flop circuit 3 is input, the other input terminal is fixed to positive logic, and the output terminal is connected to the external terminal;
Composed of,
The skew adjustment circuit according to claim 4. The first circuit includes:
A first flip-flop circuit that receives a clock signal from the oscillation source and an output signal of the second flip-flop circuit and operates in synchronization with a positive edge of the clock signal;
A second flip-flop circuit that inputs a clock signal from the oscillation source and a signal obtained by inverting the output signal of the first flip-flop circuit and operates in synchronization with a negative edge of the clock signal;
The output signal of the first flip-flop circuit is input to one input terminal, the signal obtained by inverting the output signal of the second flip-flop circuit is input to the other input terminal, and the output terminal is connected to the external circuit. A connected EXOR circuit or EXNOR circuit;
Consisting of
The second circuit includes:
A third flip-flop circuit that inputs a clock signal from the oscillation source and transfer data from the output source, and outputs the transfer data in synchronization with a positive edge of the clock signal;
An EXOR circuit in which the output signal of the third flip-flop circuit is input to one input terminal, the other input terminal is fixed to negative logic, and the output terminal is connected to the external terminal, or the first input terminal is connected to the first input terminal. An EXNOR circuit to which the output signal of the flip-flop circuit 3 is input, the other input terminal is fixed to positive logic, and the output terminal is connected to the external terminal;
Composed of,
The skew adjustment circuit according to claim 4. The wiring in the first circuit and the wiring in the second circuit have the same capacitance;
The skew adjustment circuit according to any one of claims 1 to 6. A design method of a skew adjustment circuit having first and second circuits whose delay characteristics are relatively compared,
Of the plurality of functional blocks constituting the first circuit, an additional block substantially unnecessary for the second circuit is inserted into the second circuit, whereby the first circuit and the second circuit are inserted. Configure the circuit with the same type of functional blocks.
A method for designing a skew adjustment circuit. Means for inhibiting the substantial logical operation of the additional block in the second circuit;
The method of designing a skew adjustment circuit according to claim 8.   A program for designing a skew adjustment circuit for causing a computer to implement the method according to claim 8 or 9.

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